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revision date: dec. 07 , 2005 32 hardware manual renesas 32-bit risc microcomputer superh tm risc engine family / sh7700 series sh7710 HD6417710 rev.2.00 rej09b0079-0200 sh7710 group
rev. 2.00 dec. 07, 2005 page ii of xlii
rev. 2.00 dec. 07, 2005 page iii of xlii 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. keep safety first in your circuit designs! notes regarding these materials
rev. 2.00 dec. 07, 2005 page iv of xlii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product's state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pi n. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresse s. do not access these registers; the system's operation is not guaranteed if they are accessed.
rev. 2.00 dec. 07, 2005 page v of xlii
rev. 2.00 dec. 07, 2005 page vi of xlii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents . for details, see the actual locations in this manual. 11. index
rev. 2.00 dec. 07, 2005 page vii of xlii
rev. 2.00 dec. 07, 2005 page viii of xlii preface the sh7710 risc (reduced instruction set computer) microcomputer includes a renesas technology original risc cpu as its core, and the peripheral functions required to configure a system. target users: this manual was written for users who will be using this lsi in the design of application systems. user s of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardwa re functions and electrical characteristics of this lsi to the above users. refer to the sh-3/sh-3e/sh3-dsp programming manual for a detailed description of the instruction set. notes on reading this manual: ? product names the following products are covered in this manual. product classifications and abbreviations basic classification product code sh7710 HD6417710 ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, periph eral functions and elect rical characteristics. ? in order to understand the details of the cpu's functions read the sh-3/sh-3e/sh3-dsp programming manual.
rev. 2.00 dec. 07, 2005 page ix of xlii rules: register name: the following notatio n is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb (most significant bit) is on the left and the lsb (least significant bit) is on the right. number notation: binary is b'xxxx, hexadecimal is h'xxxx, decimal is xxxx. signal notation: an overbar is added to a low-active signal: xxxx related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/ sh7710 manuals: document title document no. sh7710 hardware manual this manual sh-3/sh-3e/sh3-dsp programming manual ade-602-096b user's manuals for development tools: document title document no. superh tm risc engine c/c++ compiler,assembler,optimizing linkage editor compiler package v.9.00 user's manual rej10b0152-0101 superh tm risc engine high-performance embedded workshop 3 users manual rej10b0025-0200 superh risc engine high-performance embed ded workshop 3 tutorial rej10b0023-0200 application note: document title document no. superh risc engine c/c++ compiler pack age application note rej05b0463-0100
rev. 2.00 dec. 07, 2005 page x of xlii abbreviations acia asynchronous commun ication interface adapter aud advanced user debugger bsc bus state controller cpg clock pulse generator dma direct memory access dmac direct memory access controller etu elementary time unit fifo first-in first-out h-udi user debugging interface intc interrupt controller ipsec security architecture acceler ator for internet protocol jtag joint test action group lsb least significant bit mmu memory management unit msb most significant bit pfc pin function controller risc reduced instruction set computer rtc realtime clock scif serial communicati on interface with fifo siof serial i/o with fifo tlb translation lookaside buffer tmu timer unit uart universal asynchronou s receiver/transmitter ubc user break controller wdt watchdog timer
rev. 2.00 dec. 07, 2005 page xi of xlii
rev. 2.00 dec. 07, 2005 page xii of xlii contents section 1 overview and pin function ................................................................... 1 1.1 features....................................................................................................................... ........... 1 1.2 block diagram.................................................................................................................. ..... 7 1.3 pin description ................................................................................................................ ...... 8 1.3.1 pin assign ment......................................................................................................... 8 1.3.2 pin functions .......................................................................................................... 19 section 2 cpu ..................................................................................................... 27 2.1 processing states and processing modes............................................................................. 27 2.1.1 processing states .................................................................................................... 27 2.1.2 processing modes ................................................................................................... 28 2.2 memory map ..................................................................................................................... .. 29 2.2.1 logical addr ess space............................................................................................ 29 2.2.2 external memory space.......................................................................................... 30 2.3 register de scriptions.......................................................................................................... .32 2.3.1 general registers.................................................................................................... 35 2.3.2 system regi sters..................................................................................................... 36 2.3.3 program counter..................................................................................................... 37 2.3.4 control registers .................................................................................................... 38 2.4 data formats................................................................................................................... ..... 42 2.4.1 register data format .............................................................................................. 42 2.4.2 memory data formats ............................................................................................ 42 2.5 features of cpu co re instructions ...................................................................................... 44 2.5.1 instruction exec ution method ................................................................................ 44 2.5.2 cpu instruction addr essing modes ....................................................................... 45 2.5.3 cpu instruction formats ........................................................................................ 48 2.6 instruction set ................................................................................................................ ...... 52 2.6.1 cpu instruction set based on fu nctions................................................................ 52 2.6.2 operation c ode map............................................................................................... 66 section 3 dsp operating unit............................................................................. 71 3.1 dsp extended functio ns ..................................................................................................... 71 3.2 dsp mode re sources .......................................................................................................... 73 3.2.1 processing modes ................................................................................................... 73 3.2.2 dsp mode memo ry map........................................................................................ 73 3.2.3 cpu register sets................................................................................................... 74
rev. 2.00 dec. 07, 2005 page xiii of xlii 3.2.4 dsp registers ......................................................................................................... 77 3.3 cpu extended instructions.................................................................................................. 78 3.3.1 repeat control instructions .................................................................................... 78 3.3.2 extended repeat cont rol instru ctions .................................................................... 88 3.4 dsp data transfer instructions ........................................................................................... 93 3.4.1 general registers.................................................................................................... 97 3.4.2 dsp data ad dressing ............................................................................................. 99 3.4.3 modulo addressing............................................................................................... 100 3.4.4 memory data formats .......................................................................................... 103 3.4.5 instruction formats of double and single transfer instructions .......................... 103 3.5 dsp data operation instructio ns ....................................................................................... 106 3.5.1 dsp regist ers ....................................................................................................... 106 3.5.2 dsp operation inst ruction se t.............................................................................. 111 3.5.3 dsp-type data formats ....................................................................................... 116 3.5.4 alu fixed-point operations................................................................................ 118 3.5.5 alu integer operations ....................................................................................... 123 3.5.6 alu logical op erations....................................................................................... 125 3.5.7 fixed-point multipl y operation............................................................................ 126 3.5.8 shift opera tions .................................................................................................... 128 3.5.9 most significant bit de tection oper ation............................................................. 132 3.5.10 rounding operation.............................................................................................. 135 3.5.11 overflow protection.............................................................................................. 137 3.5.12 local data move instruction ................................................................................ 138 3.5.13 operand conflict................................................................................................... 139 3.6 dsp extended function instruction set............................................................................. 140 3.6.1 cpu extended in structions................................................................................... 140 3.6.2 double-data transfer instructions........................................................................ 142 3.6.3 single-data transfer instruct ions ......................................................................... 143 3.6.4 dsp operation in structions .................................................................................. 145 3.6.5 operation code map in dsp mode ...................................................................... 151 section 4 exception handling ...........................................................................155 4.1 register desc riptions ......................................................................................................... 1 55 4.1.1 trapa exception regi ster (tra) ...................................................................... 156 4.1.2 exception event regi ster (expevt)................................................................... 157 4.1.3 interrupt event regi ster (intevt)...................................................................... 157 4.1.4 interrupt event regist er 2 (intevt2)................................................................. 158 4.1.5 exception address re gister ( tea)....................................................................... 158 4.2 exception handlin g function ............................................................................................ 159 4.2.1 exception hand ling flow ..................................................................................... 159
rev. 2.00 dec. 07, 2005 page xiv of xlii 4.2.2 exception vector addresses................................................................................. 160 4.2.3 exception c odes ................................................................................................... 160 4.2.4 exception request and bl bit (mu ltiple exception pr evention) ......................... 160 4.2.5 exception source acceptance timing and pr iority .............................................. 161 4.3 individual exceptio n operatio ns ....................................................................................... 165 4.3.1 resets .................................................................................................................... 165 4.3.2 general exceptions............................................................................................... 166 4.3.3 general exceptions ( mmu exceptions)............................................................... 169 4.4 exception processing while dsp ex tension function is valid ......................................... 172 4.4.1 illegal instruction exception and slot illegal instruction exception .................... 172 4.4.2 cpu address error ............................................................................................... 172 4.4.3 exception in repeat control pe riod ..................................................................... 172 4.5 usage notes .................................................................................................................... ... 179 section 5 memory management unit (mmu).................................................. 181 5.1 role of mmu .................................................................................................................... 181 5.1.1 mmu of this lsi................................................................................................. 183 5.2 register desc riptions......................................................................................................... 1 89 5.2.1 page table entry regist er high (pteh).............................................................. 190 5.2.2 page table entry regi ster low (ptel) ............................................................... 191 5.2.3 translation table base register (ttb) ................................................................ 191 5.2.4 mmu control regist er (mmucr) ...................................................................... 191 5.3 tlb functions .................................................................................................................. .193 5.3.1 configuration of the tlb ..................................................................................... 193 5.3.2 tlb indexing........................................................................................................ 195 5.3.3 tlb address co mparison .................................................................................... 196 5.3.4 page management information............................................................................. 198 5.4 mmu functions................................................................................................................. 2 00 5.4.1 mmu hardware management.............................................................................. 200 5.4.2 mmu software management ............................................................................... 200 5.4.3 mmu instruction (ldtlb).................................................................................. 201 5.4.4 avoiding synonym problems............................................................................... 202 5.5 mmu excepti ons............................................................................................................... 20 5 5.5.1 tlb miss exce ption............................................................................................. 205 5.5.2 tlb protection viola tion exceptio n .................................................................... 206 5.5.3 tlb invalid ex ception ......................................................................................... 207 5.5.4 initial page write exception................................................................................. 208 5.5.5 mmu exception in repeat lo op.......................................................................... 209 5.6 memory-mappe d tlb....................................................................................................... 211 5.6.1 address array....................................................................................................... 211
rev. 2.00 dec. 07, 2005 page xv of xlii 5.6.2 data array ............................................................................................................ 211 5.6.3 usage examples.................................................................................................... 213 5.7 usage note..................................................................................................................... .... 213 section 6 cache .................................................................................................215 6.1 features....................................................................................................................... ....... 215 6.1.1 cache struct ure..................................................................................................... 215 6.2 register desc riptions ......................................................................................................... 2 17 6.2.1 cache control regist er 1 (ccr1) ........................................................................ 217 6.2.2 cache control regist er 2 (ccr2) ........................................................................ 218 6.2.3 cache control regist er 3 (ccr3) ........................................................................ 221 6.3 operation ...................................................................................................................... ..... 222 6.3.1 searching the cache.............................................................................................. 222 6.3.2 read acces s.......................................................................................................... 223 6.3.3 prefetch operation ................................................................................................ 224 6.3.4 write acces s ......................................................................................................... 224 6.3.5 write-back buffer ................................................................................................ 224 6.3.6 coherency of cache and external memory .......................................................... 225 6.4 memory-mapped cache .................................................................................................... 226 6.4.1 address array ....................................................................................................... 226 6.4.2 data array ............................................................................................................ 227 6.4.3 usage examples.................................................................................................... 230 section 7 x/y memory......................................................................................231 7.1 features....................................................................................................................... ....... 231 7.2 operation ...................................................................................................................... ..... 232 7.2.1 access from cpu.................................................................................................. 232 7.2.2 access from dsp .................................................................................................. 232 7.2.3 access from dmac, e-dm ac, and ipsec ........................................................ 233 7.3 usage notes .................................................................................................................... ... 233 7.3.1 page conflict ........................................................................................................ 233 7.3.2 bus conflic t .......................................................................................................... 233 7.3.3 mmu and cache settings..................................................................................... 233 7.3.4 sleep mode ........................................................................................................... 234 7.3.5 address error........................................................................................................ 234 section 8 interrupt controller (intc) ...............................................................235 8.1 features....................................................................................................................... ....... 235 8.1.1 block diag ram...................................................................................................... 235 8.2 input/output pins .............................................................................................................. .237
rev. 2.00 dec. 07, 2005 page xvi of xlii 8.3 interrupt sources.............................................................................................................. .. 237 8.3.1 nmi interrupt........................................................................................................ 237 8.3.2 irq interr upts....................................................................................................... 238 8.3.3 irl interr upts ....................................................................................................... 238 8.3.4 on-chip peripheral mo dule interr upts ................................................................. 239 8.3.5 interrupt exception hand ling and prio rity............................................................ 240 8.4 register desc riptions......................................................................................................... 2 46 8.4.1 interrupt priority registers a to i (ipra to ipri)................................................ 246 8.4.2 interrupt control regi ster 0 (i cr0)...................................................................... 248 8.4.3 interrupt control regi ster 1 (i cr1)...................................................................... 249 8.4.4 interrupt request regi ster 0 (irr0) ..................................................................... 251 8.4.5 interrupt request regi ster 1 (irr1) ..................................................................... 251 8.4.6 interrupt request regi ster 2 (irr2) ..................................................................... 253 8.4.7 interrupt request regi ster 3 (irr3) ..................................................................... 254 8.4.8 interrupt request regi ster 4 (irr4) ..................................................................... 255 8.4.9 interrupt request regi ster 5 (irr5) ..................................................................... 256 8.4.10 interrupt request regi ster 7 (irr7) ..................................................................... 257 8.4.11 interrupt request regi ster 8 (irr8) ..................................................................... 258 8.5 operation ...................................................................................................................... ..... 260 8.5.1 interrupt sequence ................................................................................................ 260 8.5.2 multiple inte rrupts ................................................................................................ 262 section 9 user break controller........................................................................ 263 9.1 features....................................................................................................................... ....... 263 9.2 register desc riptions......................................................................................................... 2 66 9.2.1 break address regist er a (bara)...................................................................... 266 9.2.2 break address mask regi ster a (bamra)......................................................... 267 9.2.3 break bus cycle regi ster a ( bbra)................................................................... 267 9.2.4 break address regist er b (ba rb) ...................................................................... 269 9.2.5 break address mask re gister b (b amrb) ......................................................... 270 9.2.6 break data regist er b (bdrb)............................................................................ 270 9.2.7 break data mask regi ster b (b dmrb)............................................................... 271 9.2.8 break bus cycle regi ster b ( bbrb) ................................................................... 272 9.2.9 break control regi ster (brc r) ........................................................................... 274 9.2.10 execution times break register (betr)............................................................. 278 9.2.11 branch source regi ster (brs r)........................................................................... 279 9.2.12 branch destination re gister ( brdr)................................................................... 280 9.2.13 break asid register a (basra) ....................................................................... 280 9.2.14 break asid regist er b (bas rb)........................................................................ 281 9.3 operation ...................................................................................................................... ..... 281
rev. 2.00 dec. 07, 2005 page xvii of xlii 9.3.1 flow of the user br eak operation ........................................................................ 281 9.3.2 break on instructio n fetch cy cle.......................................................................... 283 9.3.3 break on data a ccess cycle................................................................................. 283 9.3.4 break on x/y-memory bus cycle........................................................................ 285 9.3.5 sequential break ................................................................................................... 285 9.3.6 value of saved prog ram counter ......................................................................... 286 9.3.7 pc trace ............................................................................................................... 287 9.3.8 usage examples.................................................................................................... 287 9.4 usage notes .................................................................................................................... ... 292 section 10 power-down modes ........................................................................295 10.1 overview....................................................................................................................... ..... 295 10.1.1 power-down modes ............................................................................................. 295 10.1.2 reset ..................................................................................................................... 296 10.1.3 input/output pins.................................................................................................. 298 10.2 register desc riptions ......................................................................................................... 2 98 10.2.1 standby control regi ster (st bcr)...................................................................... 298 10.2.2 standby control regist er 2 (st bcr2)................................................................. 300 10.2.3 standby control regist er 3 (st bcr3)................................................................. 301 10.3 operation ...................................................................................................................... ..... 302 10.3.1 sleep mode ........................................................................................................... 302 10.3.2 software sta ndby mode ........................................................................................ 303 10.3.3 module standby function..................................................................................... 305 10.3.4 status pin change timings.............................................................................. 306 section 11 on-chip oscillation circuits ...........................................................311 11.1 overview....................................................................................................................... ..... 311 11.1.1 features................................................................................................................. 311 11.2 overview of cpg............................................................................................................... 3 13 11.2.1 cpg block diagram ............................................................................................. 313 11.2.2 input/output pins.................................................................................................. 315 11.3 clock operatin g modes ..................................................................................................... 315 11.4 register de scription........................................................................................................... 320 11.4.1 frequency control re gister (f rqcr) ................................................................. 320 11.5 changing frequency .......................................................................................................... 322 11.5.1 changing multipli cation ra te............................................................................... 322 11.5.2 changing divisi on ratio....................................................................................... 322 11.6 overview of wdt ............................................................................................................. 323 11.6.1 block diagram of wdt........................................................................................ 323 11.7 register descripti ons of wdt........................................................................................... 324
rev. 2.00 dec. 07, 2005 page xviii of xlii 11.7.1 watchdog timer coun ter (wtcnt).................................................................... 324 11.7.2 watchdog timer control/statu s register (w tcsr)............................................ 324 11.7.3 notes on regist er access ..................................................................................... 326 11.8 using wdt...................................................................................................................... .. 327 11.8.1 canceling st andbys .............................................................................................. 327 11.8.2 changing frequency ............................................................................................. 328 11.8.3 using watchdog ti mer mode .............................................................................. 328 11.8.4 using interval timer mode .................................................................................. 328 11.9 notes on boar d design ...................................................................................................... 329 section 12 bus state controller (bsc) ............................................................. 331 12.1 features....................................................................................................................... ....... 331 12.2 input/output pins.............................................................................................................. .334 12.3 area overview.................................................................................................................. .336 12.3.1 area division........................................................................................................ 336 12.3.2 shadow area......................................................................................................... 336 12.3.3 address ma p......................................................................................................... 338 12.3.4 area 0 memory type and memory bus width .................................................... 340 12.3.5 data alignm ent..................................................................................................... 340 12.4 register desc riptions......................................................................................................... 3 41 12.4.1 common control regi ster (cmn cr) .................................................................. 342 12.4.2 csn space bus control register (csnbcr) (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) ..... 345 12.4.3 csn space wait control register (csnwcr) (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b)... 350 12.4.4 sdram control regi ster (sd cr)....................................................................... 377 12.4.5 refresh timer control/statu s register (r tcsr)................................................. 380 12.4.6 refresh timer coun ter (rtcnt)......................................................................... 381 12.4.7 refresh time constant register (rtcor) .......................................................... 382 12.5 operation ...................................................................................................................... ..... 383 12.5.1 endian/access size and da ta alignment.............................................................. 383 12.5.2 normal space interface ........................................................................................ 389 12.5.3 access wait control ............................................................................................. 395 12.5.4 csn assert period expansion ............................................................................... 397 12.5.5 sdram interface ................................................................................................. 398 12.5.6 burst rom (clock asynch ronous) interface ....................................................... 439 12.5.7 byte-selection sram interface ........................................................................... 441 12.5.8 pcmcia inte rface................................................................................................ 446 12.5.9 burst rom (clock sync hronous) interface.......................................................... 452 12.5.10 wait between acce ss cycles ................................................................................ 453 12.5.11 bus arbitrat ion ..................................................................................................... 453 12.5.12 others.................................................................................................................... 457
rev. 2.00 dec. 07, 2005 page xix of xlii section 13 direct memory access controller (dmac) ...................................459 13.1 features....................................................................................................................... ....... 459 13.2 input/output pins .............................................................................................................. .461 13.3 register desc riptions ......................................................................................................... 4 62 13.3.1 dma source address re gister (sar) ................................................................. 463 13.3.2 dma destination address register (d ar) ......................................................... 463 13.3.3 dma transfer count re gister (dma tcr) ......................................................... 464 13.3.4 dma channel control re gister (chcr) ............................................................. 464 13.3.5 dma operation regist er (dmaor) ................................................................... 469 13.3.6 dma extension resource selector 0 to 2 (dmars0 to dmars2) ................... 471 13.4 operation ...................................................................................................................... ..... 474 13.4.1 dma transfer flow ............................................................................................. 474 13.4.2 dma transfer requests ....................................................................................... 477 13.4.3 channel prio rity.................................................................................................... 479 13.4.4 dma transfer types............................................................................................ 482 13.4.5 number of bus cycle states and dreq pin sampli ng timing ........................... 489 13.5 usage note..................................................................................................................... .... 493 section 14 timer unit (tmu) ...........................................................................495 14.1 features....................................................................................................................... ....... 495 14.1.1 block diag ram...................................................................................................... 495 14.2 register desc riptions ......................................................................................................... 4 97 14.2.1 timer start regist er (tstr) ................................................................................ 497 14.2.2 timer control regi sters (tcr) ............................................................................ 498 14.2.3 timer constant regi sters (tco r) ....................................................................... 499 14.2.4 timer counters (tcnt) ....................................................................................... 499 14.3 tmu operation.................................................................................................................. 500 14.3.1 counter operation................................................................................................. 500 14.4 interrupts..................................................................................................................... ....... 503 14.4.1 status flag se t timing.......................................................................................... 503 14.4.2 status flag cl ear timi ng ...................................................................................... 503 14.4.3 interrupt sources an d prioriti es ............................................................................ 504 14.5 usage notes .................................................................................................................... ... 504 14.5.1 writing to regi sters .............................................................................................. 504 14.5.2 reading registers ................................................................................................. 504 section 15 realtime clock (rtc) .....................................................................505 15.1 feature ........................................................................................................................ ....... 505 15.2 input/output pins .............................................................................................................. .507 15.3 register desc riptions ......................................................................................................... 5 07
rev. 2.00 dec. 07, 2005 page xx of xlii 15.3.1 64-hz counter (r64cnt) .................................................................................... 508 15.3.2 second counter (rseccnt) ............................................................................... 508 15.3.3 minute counter (r mincnt)............................................................................... 509 15.3.4 hour counter (rhrcnt) .................................................................................... 509 15.3.5 day of week coun ter (rwkcnt) ...................................................................... 510 15.3.6 date counter (r daycnt) .................................................................................. 512 15.3.7 month counter (r moncnt) .............................................................................. 512 15.3.8 year counter (ryrcnt)..................................................................................... 513 15.3.9 second alarm regist er (rsecar) ...................................................................... 514 15.3.10 minute alarm regist er (rminar)...................................................................... 514 15.3.11 hour alarm regist er (rhrar) ........................................................................... 515 15.3.12 day of week alarm re gister (rwkar) ............................................................. 516 15.3.13 date alarm regist er (rdaya r)......................................................................... 517 15.3.14 month alarm regist er (rmonar) ..................................................................... 518 15.3.15 year alarm regist er (ryrar)............................................................................ 519 15.3.16 rtc control regist er 1 (rcr1)........................................................................... 520 15.3.17 rtc control regist er 2 (rcr2)........................................................................... 522 15.3.18 rtc control regist er 3 (rcr3)........................................................................... 524 15.4 operation ...................................................................................................................... ..... 525 15.4.1 initial settings of regist ers after po wer-on ......................................................... 525 15.4.2 setting ti me ......................................................................................................... 525 15.4.3 reading ti me........................................................................................................ 525 15.4.4 alarm func tion..................................................................................................... 527 15.4.5 crystal oscillato r circuit ...................................................................................... 528 15.5 usage notes .................................................................................................................... ... 529 15.5.1 register writing dur ing rtc count..................................................................... 529 15.5.2 use of realtime clock (rtc ) periodic inte rrupts................................................ 529 15.5.3 transition to standby mode after setting re gister............................................... 529 15.5.4 usage note about rtc power supply.................................................................. 530 section 16 serial communication interface with fifo (scif)........................ 531 16.1 features....................................................................................................................... ....... 531 16.2 input/output pins.............................................................................................................. .534 16.3 register desc riptions......................................................................................................... 5 35 16.3.1 receive shift regi ster (scrs r) .......................................................................... 536 16.3.2 receive fifo data re gister (scf rdr) .............................................................. 536 16.3.3 transmit shift regi ster (sct sr) ......................................................................... 537 16.3.4 transmit fifo data re gister (scftdr)............................................................. 537 16.3.5 serial mode regist er (scsmr)............................................................................ 537 16.3.6 serial control regi ster (scs cr).......................................................................... 541
rev. 2.00 dec. 07, 2005 page xxi of xlii 16.3.7 serial status regi ster (scfsr) ............................................................................ 545 16.3.8 bit rate regist er (scbrr) .................................................................................. 553 16.3.9 fifo control regi ster (scf cr) .......................................................................... 554 16.3.10 fifo data count regi ster (scfdr) .................................................................... 556 16.3.11 line status regist er (sclsr) .............................................................................. 558 16.4 operation ...................................................................................................................... ..... 559 16.4.1 overview............................................................................................................... 559 16.4.2 serial operation in as ynchronous mode.............................................................. 561 16.4.3 serial operation in cloc k synchronou s mode...................................................... 572 16.5 scif interrupt sour ces and dmac................................................................................... 582 16.6 usage notes .................................................................................................................... ... 583 section 17 serial i/o with fifo (siof)............................................................587 17.1 features....................................................................................................................... ....... 587 17.1.1 block diag ram...................................................................................................... 588 17.2 input/output pins .............................................................................................................. .589 17.3 register desc riptions ......................................................................................................... 5 90 17.3.1 siof mode register (simdr) ............................................................................. 591 17.3.2 serial clock select register (s iscr)................................................................... 593 17.3.3 serial transmit data assi gn register (sitdar) ................................................. 594 17.3.4 serial receive data assign register (sirdar) .................................................. 595 17.3.5 serial control data assign register (sicdar) ................................................... 596 17.3.6 siof control register (sictr) ........................................................................... 598 17.3.7 siof fifo control re gister (sifctr)................................................................ 601 17.3.8 siof status regist er (sistr) .............................................................................. 603 17.3.9 siof interrupt enable register (siier) ............................................................... 607 17.3.10 serial transmit data register (sitdr)................................................................ 609 17.3.11 serial receive data re gister (sir dr) ................................................................. 610 17.3.12 serial transmit control da ta register (sitcr) ................................................... 611 17.3.13 serial receive control data register (s ircr) .................................................... 612 17.4 operation ...................................................................................................................... ..... 613 17.4.1 serial cl ocks ......................................................................................................... 613 17.4.2 serial ti ming ........................................................................................................ 614 17.4.3 transfer data format............................................................................................ 616 17.4.4 register allocation of transfer data .................................................................... 617 17.4.5 control data interface .......................................................................................... 620 17.4.6 fifo...................................................................................................................... 621 17.4.7 transmission and recep tion procedures .............................................................. 623 17.4.8 interrupts............................................................................................................... 628 17.4.9 transmission and r eception timi ng .................................................................... 630
rev. 2.00 dec. 07, 2005 page xxii of xlii 17.5 usage notes .................................................................................................................... ... 635 section 18 ethernet controller (etherc) ........................................................... 637 18.1 features....................................................................................................................... ....... 637 18.2 input/output pins.............................................................................................................. .639 18.3 register desc riptions......................................................................................................... 6 41 18.3.1 software reset regi ster (arstr) ....................................................................... 644 18.3.2 etherc mode regi ster (ecmr)............................................................................ 645 18.3.3 etherc status regi ster (ecs r) ............................................................................ 648 18.3.4 etherc interrupt permission register (e csipr) .................................................. 649 18.3.5 phy interface regist er (pir) ............................................................................... 650 18.3.6 mac address high re gister (m ahr) ................................................................ 651 18.3.7 mac address low regi ster (malr) ................................................................. 651 18.3.8 receive frame length register (rflr) .............................................................. 652 18.3.9 phy status regist er (psr)................................................................................... 653 18.3.10 transmit retry over count er register (trocr) ................................................ 653 18.3.11 delayed collision detect coun ter register (cdcr)............................................ 654 18.3.12 lost carrier counter register (lccr)................................................................. 654 18.3.13 carrier not detect counte r register (cndcr) ................................................... 654 18.3.14 crc error frame receive count er register (cefcr)........................................ 655 18.3.15 frame receive error counte r register (frecr) ................................................. 655 18.3.16 too-short frame receive count er register (tsfrcr) ...................................... 655 18.3.17 too-long frame receive count er register (tlfrcr) ...................................... 656 18.3.18 residual-bit frame receive co unter register (rfcr) ....................................... 656 18.3.19 multicast address frame receive c ounter register (mafcr)........................... 657 18.3.20 ipg register (ipgr)............................................................................................. 657 18.3.21 tsu counter reset regist er (tsu_ctrst) ....................................................... 658 18.3.22 relay enable register (port 0 to 1) (tsu_fwen0) ............................................ 658 18.3.23 relay enable register (port 1 to 0) (tsu_fwen1) ............................................ 659 18.3.24 relay fifo size select re gister (tsu_fcm) ..................................................... 660 18.3.25 relay fifo overflow alert set regi ster (port 0) (tsu_bsysl0) ..................... 661 18.3.26 relay fifo overflow alert set regi ster (port 1) (tsu_bsysl1) ..................... 662 18.3.27 transmit/relay priority control mode register (port 0) (tsu_prisl0)............ 663 18.3.28 transmit/relay priority control mode register (port 1) (tsu_prisl1)............ 664 18.3.29 receive/relay function set register (port 0 to 1) (tsu_fwsl0)...................... 666 18.3.30 receive/relay function set register (port 1 to 0) (tsu_fwsl1)...................... 667 18.3.31 relay function set register (common) (tsu_fwslc)..................................... 669 18.3.32 qtag addition/deletion set register (port 0 to 1) (t su_qtagm 0) .................. 671 18.3.33 qtag addition/deletion set register (port 1 to 0) (t su_qtagm 1) .................. 672 18.3.34 relay status regist er (tsu_fwsr) .................................................................... 673
rev. 2.00 dec. 07, 2005 page xxiii of xlii 18.3.35 relay status interrupt mask register (tsu_fwinmk)...................................... 675 18.3.36 added qtag value set register (p ort 0 to 1) (t su_adqt0).............................. 679 18.3.37 added qtag value set register (p ort 1 to 0) (t su_adqt1).............................. 680 18.3.38 cam entry table busy regi ster (tsu_adsbsy) ............................................. 681 18.3.39 cam entry table enable re gister (tsu_ten) .................................................. 682 18.3.40 cam entry table post1 regi ster (tsu_post1).............................................. 686 18.3.41 cam entry table post2 regi ster (tsu_post2).............................................. 689 18.3.42 cam entry table post3 regi ster (tsu_post3).............................................. 692 18.3.43 cam entry table post4 regi ster (tsu_post4).............................................. 695 18.3.44 cam entry table 0 to 31 h register s (tsu_adrh0 to tsu_adrh31).......... 698 18.3.45 cam entry table 0 to 31 l registers (tsu_adrl0 to tsu_adrl31) ........... 699 18.3.46 transmit frame counter register (por t 0) (normal transmission only) (txnlcr0) ......................................................................................................... 699 18.3.47 transmit frame counter register (port 0) (normal and error transmission) (txalcr0) ......................................................................................................... 700 18.3.48 receive frame counter register (p ort 0) (normal reception only) (rxnlcr0 ) ......................................................................................................... 700 18.3.49 receive frame counter register (por t 0) (normal and error reception) (rxalcr0 ) ......................................................................................................... 701 18.3.50 relay frame counter register (port 1 to 0) (normal relay only) (fwnlcr0)......................................................................................................... 701 18.3.51 relay frame counter register (port 1 to 0) (normal and error relay) (fwalcr0)......................................................................................................... 702 18.3.52 transmit frame counter register (por t 1) (normal transmission only) (txnlcr1) ......................................................................................................... 702 18.3.53 transmit frame counter register (port 1) (normal and error transmission) (txalcr1) ......................................................................................................... 703 18.3.54 receive frame counter register (p ort 1) (normal reception only) (rxnlcr1 ) ......................................................................................................... 703 18.3.55 receive frame counter register (por t 1) (normal and error reception) (rxalcr1 ) ......................................................................................................... 704 18.3.56 relay frame counter register (port 0 to 1) (normal relay only) (fwnlcr1)......................................................................................................... 704 18.3.57 relay frame counter register (port 0 to 1) (normal and error relay) (fwalcr1)......................................................................................................... 705 18.4 operation ...................................................................................................................... ..... 706 18.4.1 transmissi on......................................................................................................... 707 18.4.2 reception .............................................................................................................. 709 18.4.3 relay ..................................................................................................................... 711 18.4.4 cam functio n ...................................................................................................... 711
rev. 2.00 dec. 07, 2005 page xxiv of xlii 18.4.5 mii frame timing ................................................................................................ 717 18.4.6 accessing mii re gisters....................................................................................... 719 18.4.7 magic packet de tection ........................................................................................ 722 18.4.8 operation by ip g setting...................................................................................... 723 18.4.9 direction for ieee 802.1q qt ag ........................................................................... 723 18.5 connection to lsi.............................................................................................................. 725 section 19 ethernet controller direct memory access controller (e-dmac)....................................................................................... 727 19.1 features....................................................................................................................... ....... 727 19.2 register desc riptions......................................................................................................... 7 28 19.2.1 e-dmac mode regi ster (edm r)....................................................................... 730 19.2.2 e-dmac transmit request register (e dtrr) .................................................. 731 19.2.3 e-dmac receive request register (edrrr).................................................... 732 19.2.4 transmit descriptor list a ddress register (tdlar).......................................... 733 19.2.5 receive descriptor list addr ess register (rdlar) ........................................... 734 19.2.6 etherc/e-dmac status register (e esr)............................................................ 734 19.2.7 etherc/e-dmac status interrupt pe rmission register (eesipr)....................... 740 19.2.8 transmit/receive status copy en able register (trscer)................................. 743 19.2.9 receive missed-frame counte r register (rmfcr) ............................................ 744 19.2.10 transmit fifo threshol d register (tftr).......................................................... 745 19.2.11 fifo depth regist er (fdr) ................................................................................. 747 19.2.12 receiving method contro l register (rmcr) ...................................................... 748 19.2.13 e-dmac operation contro l register (edocr) ................................................. 749 19.2.14 receive buffer write addres s register ( rbwar).............................................. 750 19.2.15 receive descriptor fetch addr ess register (rdfar)......................................... 750 19.2.16 transmit buffer read addres s register (tbrar) .............................................. 750 19.2.17 transmit descriptor fetch ad dress register (tdfar) ....................................... 751 19.2.18 overflow alert fifo thresh old register (fcftr) ............................................. 751 19.2.19 transmit interrupt re gister (trimd) .................................................................. 753 19.3 operation ...................................................................................................................... ..... 753 19.3.1 descriptors and desc riptor list ............................................................................ 754 19.3.2 transmissi on......................................................................................................... 767 19.3.3 reception .............................................................................................................. 769 19.3.4 transmit/receive processing of multi-buffer frame (single-frame/ multi- descriptor) ........................................................................ 771 19.3.5 receive fifo overfl ow alert signal ( arbusy )................................................ 773 19.4 usage notes .................................................................................................................... ... 776 19.4.1 using of edtrr and edrrr ............................................................................. 776 19.4.2 endian support in e-dmac................................................................................. 777
rev. 2.00 dec. 07, 2005 page xxv of xlii section 20 ip security accelerator (ipsec) .....................................................779 section 21 pin functio n controller (pfc).........................................................781 21.1 overview....................................................................................................................... ..... 781 21.2 register conf iguratio n....................................................................................................... 78 2 21.3 register desc riptions ......................................................................................................... 7 83 21.3.1 port a control regi ster (pacr) .......................................................................... 783 21.3.2 port b control re gister (p bcr)........................................................................... 784 21.3.3 port c control re gister (p ccr)........................................................................... 785 21.3.4 ethernet controller pin cont rol register (petcr).............................................. 786 section 22 i/o ports ...........................................................................................789 22.1 overview....................................................................................................................... ..... 789 22.2 register desc riptions ......................................................................................................... 7 89 22.2.1 port a data regi ster (padr)............................................................................... 789 22.2.2 port b data regi ster (pbdr) ............................................................................... 790 22.2.3 port c data regi ster (pcdr) ............................................................................... 792 section 23 user debuggi ng interface (h-udi) .................................................793 23.1 features....................................................................................................................... ....... 793 23.2 input/output pins .............................................................................................................. .794 23.3 register desc riptions ......................................................................................................... 7 95 23.3.1 bypass register (sdbpr) .................................................................................... 795 23.3.2 instruction regist er (sdir) .................................................................................. 795 23.3.3 boundary scan regist er (sdbsr) ....................................................................... 796 23.3.4 id register (sdid)............................................................................................... 803 23.4 operation ...................................................................................................................... ..... 804 23.4.1 tap contro ller ..................................................................................................... 804 23.4.2 reset configur ation .............................................................................................. 805 23.4.3 tdo output timing ............................................................................................. 805 23.4.4 h-udi reset ......................................................................................................... 806 23.4.5 h-udi interrupt .................................................................................................... 806 23.5 boundary scan .................................................................................................................. .807 23.5.1 supported inst ructions .......................................................................................... 807 23.5.2 points for a ttention............................................................................................... 808 23.6 usage notes .................................................................................................................... ... 808 23.7 advanced user de bugger (aud)...................................................................................... 808
rev. 2.00 dec. 07, 2005 page xxvi of xlii section 24 list of registers............................................................................... 809 24.1 register addresses (by functional module, in order of th e corresponding sec tion numbers) ........................... 810 24.2 register bits.................................................................................................................. ..... 823 24.3 register states in ea ch operating mode ........................................................................... 846 section 25 electrical characteristics ................................................................. 855 25.1 absolute maximum ratings .............................................................................................. 855 25.2 dc charact eristics ............................................................................................................. 857 25.3 ac charact eristics ............................................................................................................. 859 25.3.1 clock timing ........................................................................................................ 860 25.3.2 control signal timing .......................................................................................... 865 25.3.3 ac bus ti ming..................................................................................................... 868 25.3.4 basic timi ng......................................................................................................... 870 25.3.5 burst rom ti ming............................................................................................... 874 25.3.6 synchronous dram timing ................................................................................ 875 25.3.7 dmac signal timing .......................................................................................... 901 25.3.8 rtc signal timing............................................................................................... 902 25.3.9 scif module signa l timing ................................................................................. 903 25.3.10 siof module si gnal timi ng ................................................................................ 904 25.3.11 ethernet controll er timi ng................................................................................... 908 25.3.12 port input/output timing ..................................................................................... 912 25.3.13 h-udi related pi n timing................................................................................... 913 25.3.14 ac characteristics meas urement cond itions ....................................................... 915 25.4 delay time variation due to load capacitance ............................................................... 916 appendix ......................................................................................................... 917 a. pin states and states of unused pins ................................................................................. 917 b. package dime nsions .......................................................................................................... 925 main revisions and additions in this edition..................................................... 929 index ......................................................................................................... 947
rev. 2.00 dec. 07, 2005 page xxvii of xlii figures section 1 overview figure 1.1 block di agram ..................................................................................................... ......... 7 figure 1.2 pin assignment (hqfp2828-256 (fp-256g/gv)) ....................................................... 8 figure 1.3 pin assignment (p-lfbga1717-256 (bp-256h/h v))................................................. 9 section 2 cpu figure 2.1 processi ng state tr ansitions...................................................................................... .. 28 figure 2.2 logical address to external memory space mapping................................................ 31 figure 2.3 register configura tion in each pro cessing mode....................................................... 34 figure 2.4 ge neral registers ................................................................................................. ....... 36 figure 2.5 system regist ers and progra m counter ...................................................................... 37 figure 2.6 control re gister config uration ................................................................................... 4 1 figure 2.7 data format on memory (big endian mode) ............................................................. 43 figure 2.8 data format on memory (little en dian mode) .......................................................... 43 section 3 dsp operating unit figure 3.1 dsp instruction format............................................................................................ ... 72 figure 3.2 cpu regi sters in dsp mode....................................................................................... 74 figure 3.3 dsp regi ster config uration ........................................................................................ 77 figure 3.4 dsp regist ers and bus connections ........................................................................... 94 figure 3.5 general registers (dsp mode) ................................................................................... 97 figure 3.6 sample para llel instructio n program ......................................................................... 113 figure 3.7 examples of conditional operations and data transfer instructions ....................... 115 figure 3.8 data formats ...................................................................................................... ....... 117 figure 3.9 alu fixed-point arithmetic opera tion flow ........................................................... 118 figure 3.10 operatio n sequence example.................................................................................. 120 figure 3.11 dc bit generation exam ples in carry or borrow mode ........................................ 121 figure 3.12 dc bit generation ex amples in negative value mode .......................................... 121 figure 3.13 dc bit generation examples in overflow mode.................................................... 122 figure 3.14 alu integer arithmetic operat ion flow ................................................................ 123 figure 3.15 alu logi cal operatio n flow ................................................................................. 125 figure 3.16 fixed-point multiply opera tion flow ..................................................................... 127 figure 3.17 arithmetic shift operatio n flow............................................................................. 129 figure 3.18 logical shift operatio n flow .................................................................................. 131 figure 3.19 pdms b operation flow ......................................................................................... 133 figure 3.20 roundin g operation flow ....................................................................................... 136 figure 3.21 definition of rounding op eration........................................................................... 136 figure 3.22 local data move instruc tion flow.......................................................................... 138
rev. 2.00 dec. 07, 2005 page xxviii of xlii section 4 exception handling figure 4.1 register bit config uration ........................................................................................ 156 section 5 memory management unit (mmu) figure 5.1 mmu functions ..................................................................................................... ... 183 figure 5.2 virtual addr ess space (mmucr .at = 1)................................................................ 185 figure 5.3 virtual addr ess space (mmucr .at = 0)................................................................ 186 figure 5.4 p4 area........................................................................................................... ........... 187 figure 5.5 extern al memory space ............................................................................................ 1 88 figure 5.6 overall conf iguration of the tlb............................................................................. 193 figure 5.7 virtual addr ess and tlb st ructure........................................................................... 194 figure 5.8 tlb indexing (ix = 1) ............................................................................................. .195 figure 5.9 tlb indexing (ix = 0) ............................................................................................. .196 figure 5.10 objects of address comp arison.............................................................................. 197 figure 5.11 operation of ldtlb inst ruction............................................................................. 202 figure 5.12 synonym pr oblem (32-kbyte cache) ...................................................................... 204 figure 5.13 mmu exceptio n generation flowchart .................................................................. 210 figure 5.14 specifying address and data for memo ry-mapped tlb access ........................... 212 section 6 cache figure 6.1 cache structure ................................................................................................... ...... 215 figure 6.2 cache search scheme ............................................................................................... 223 figure 6.3 write-back buffer configur ation .............................................................................. 225 figure 6.4 specifying address and data for memory-mapped cache access (16 kbytes mode) ....................................................................................................... 228 figure 6.5 specifying address and data for memory-mapped cache access (32 kbytes mode) ....................................................................................................... 229 section 8 interrupt controller (intc) figure 8.1 block diagram of intc............................................................................................ 2 36 figure 8.2 example of ir l interrupt c onnection....................................................................... 239 figure 8.3 interrupt operation flowchart................................................................................... 26 1 section 9 user break controller figure 9.1 block diagram of user break controller.................................................................. 265 section 10 power-down modes figure 10.1 canceling stan dby mode with stbcr.stby........................................................ 305 figure 10.2 status out put at power-on reset....................................................................... 306 figure 10.3 status ou tput at manua l reset ........................................................................... 307 figure 10.4 status output when software standby mode is canceled by interrupt ............. 307 figure 10.5 status output when software standby mode is canceled by power-on reset .. 308 figure 10.6 status output when software standby mode is canceled by manual reset ..... 308
rev. 2.00 dec. 07, 2005 page xxix of xlii figure 10.7 status output when sl eep mode is canceled by interrupt................................. 309 figure 10.8 status output when sleep mode is canceled by power-on reset...................... 309 figure 10.9 status output when sleep mode is canceled by manual reset......................... 310 section 11 on-chip oscillation circuits figure 11.1 bloc k diagram of cpg ........................................................................................... 31 3 figure 11.2 block diagram of wdt .......................................................................................... 323 figure 11.3 writing to wtcnt and wtcsr............................................................................ 327 figure 11.4 points for attenti on when using crysta l resonator................................................ 329 figure 11.5 points for attention when using pll osc illator circ uit ........................................ 330 section 12 bus state controller (bsc) figure 12.1 bloc k diagram of bsc............................................................................................ 3 33 figure 12.2 address space .................................................................................................... ..... 337 figure 12.3 normal space basi c access timing (a ccess wait 0)............................................. 389 figure 12.4 continuous access for normal space 1, bus width = 16 bits, longword access, csnwcr.wm bit = 0 (access wa it = 0, cycle wait = 0)..................................... 391 figure 12.5 continuous access for normal space 2, bus width = 16 bits, longword access, csnwcr.wm bit = 1 (access wa it = 0, cycle wait = 0)..................................... 392 figure 12.6 example of 32-bit data-width sram connectio n ................................................ 393 figure 12.7 example of 16-bit data-width sram connectio n ................................................ 394 figure 12.8 example of 8-bit data-width sram connection .................................................. 394 figure 12.9 wait timing for normal space access (softwar e wait only ) ............................... 395 figure 12.10 wait state ti ming for normal space access (wait state insertion by wait signal)................................................................. 396 figure 12.11 csn assert period expansion................................................................................ 397 figure 12.12 example of 32-bit data-width sdram connectio n ........................................... 399 figure 12.13 example of 16-bit data-width sdram connectio n ........................................... 400 figure 12.14 burst read ba sic timing (auto precharge) .......................................................... 415 figure 12.15 burst read wait speci fication timing (auto precharge) ..................................... 416 figure 12.16 basic timing for si ngle read (auto precharge)................................................... 417 figure 12.17 basic timing for burst write (auto precharge).................................................... 419 figure 12.18 basic timing for si ngle write (auto-precharge).................................................. 420 figure 12.19 burst read ti ming (no auto precharge) .............................................................. 422 figure 12.20 burst read timing (b ank active, same row address) ....................................... 423 figure 12.21 burst read timing (ban k active, different row addresses) .............................. 424 figure 12.22 single write ti ming (no auto precharge)............................................................ 425 figure 12.23 single write timing (b ank active, same row address) ..................................... 426 figure 12.24 single write timing (ban k active, different row addresses) ............................ 427 figure 12.25 auto-refresh timing ............................................................................................ 4 29 figure 12.26 se lf-refresh timing ............................................................................................. .431
rev. 2.00 dec. 07, 2005 page xxx of xlii figure 12.27 access timing in low-frequency mode .............................................................. 432 figure 12.28 access timing in power-down mode .................................................................. 433 figure 12.29 write timing for sdram mode register (based on jedec)............................. 436 figure 12.30 emrs co mmand issue timing............................................................................. 438 figure 12.31 transition timing in deep power-down mode.................................................... 439 figure 12.32 burst rom (clock asynchronous) access (bus width = 32 bits, 16-byte transfer (number of bursts = 4), access wait for first time = 2, access wait for 2nd time and after = 1).............................................................. 441 figure 12.33 basic access timing fo r byte-selection sram (bas = 0) ................................. 442 figure 12.34 basic access timing fo r byte-selection sram (bas = 1) ................................. 443 figure 12.35 wait timing for byte-selection sram (bas = 1) (software wait only)........... 444 figure 12.36 example of connection with 32-bit data-width byte -selection sram ............. 445 figure 12.37 example of connection with 16-bit data-width byte -selection sram ............. 445 figure 12.38 example of pc mcia interface connectio n.......................................................... 447 figure 12.39 basic access timing fo r pcmcia memory card interface................................. 448 figure 12.40 wait timing for pcmcia memory card interface (ted[3:0] = b 0010, teh[3:0] = b 0001, software wait = 1, hardware wait = 1) .............................. 448 figure 12.41 example of pcmcia space assignment (cs5bwcr.sa[1:0] = b 10, cs6bwcr.sa[1:0] = b 10)................................................................................. 449 figure 12.42 basic timing for pcmcia i/o card interface ..................................................... 450 figure 12.43 wait timing for pcmcia i/o card interface (ted[3:0] = b 0010, teh[3:0] = b 0001, software wait = 1, hardware wait = 1) .............................. 451 figure 12.44 timing for dynamic bus sizing of pcmcia i/o card interface (ted[3:0] = b 0010, teh[3:0] = b 0001, software waits = 3) .......................... 451 figure 12.45 burst rom (clock synchr onous) access timing (burst length = 8, wait cycles inserted in first access = 2, wait cycles inserted in second and subsequent acce sses = 1)..................................................................................... 452 figure 12.46 bus arbitration timing ......................................................................................... 4 56 section 13 direct memory access controller (dmac) figure 13.1 block diagram of dmac ....................................................................................... 460 figure 13.2 dma transfer flowchart........................................................................................ 476 figure 13.3 round-robin mode................................................................................................. 480 figure 13.4 changes in channel priority in roun d-robin mode............................................... 481 figure 13.5 data flow in dual address mode ........................................................................... 483 figure 13.6 example of dma transfer timing in dual address mode (source: ordinary memory, destin ation: ordinary memory) ................................. 484 figure 13.7 data flow in single addr ess mode......................................................................... 485 figure 13.8 example of dma transf er timing in single address mode ................................. 486 figure 13.9 dma transfer ex ample in cycle-steal mode (dual address, dreq lo w level det ection)......................................................... 487
rev. 2.00 dec. 07, 2005 page xxxi of xlii figure 13.10 dma transfer example in burst mode (dual address, dreq lo w level det ection)....................................................... 487 figure 13.11 bus state when mu ltiple channels ar e operating ................................................. 489 figure 13.12 example of dreq input detec tion in cycle steal mode edge detection............ 490 figure 13.13 example of dreq input detec tion in cycle steal mode level detection........... 490 figure 13.14 example of dreq input det ection in burst mode edge detection ..................... 491 figure 13.15 example of dreq input det ection in burst mode level detection .................... 491 figure 13.16 example of dma transfer en d timing (cycle steal level detection) ............... 491 figure 13.17 example of bsc ordinary memory access (no wait, idle cycle = 1, longword access to 16-bit devi ce)...................................................................... 492 section 14 timer unit (tmu) figure 14.1 tmu block diagram............................................................................................... 4 96 figure 14.2 setti ng count op eration .......................................................................................... 501 figure 14.3 auto-rel oad count oper ation................................................................................. 501 figure 14.4 count timing when internal clock is operating .................................................... 502 figure 14.5 unf set timing ................................................................................................... ... 503 figure 14.6 status flag clear timing......................................................................................... 503 section 15 realtime clock (rtc) figure 15.1 rt c block di agram................................................................................................ 506 figure 15.2 setting time ..................................................................................................... ....... 525 figure 15.3 readin g time ..................................................................................................... ..... 526 figure 15.4 us ing alarm function ............................................................................................. 527 figure 15.5 example of crysta l oscillator circu it connectio n .................................................. 528 figure 15.6 using peri odic interrupt function ........................................................................... 529 section 16 serial communicati on interface with fifo (scif) figure 16.1 bloc k diagram of scif........................................................................................... 5 33 figure 16.2 data format in asynchronous communication (example of 8-bit data with parity and 2 st op bits) .............................................. 561 figure 16.3 sample the sc if initialization flowchart ............................................................... 564 figure 16.4 sample serial transmission flowchart ................................................................... 565 figure 16.5 example of transmit operation (example of 8-bit data with parity and 1 st op bit)................................................ 567 figure 16.6 sample serial reception flowch art (1)................................................................... 568 figure 16.7 sample serial reception flowch art (2)................................................................... 569 figure 16.8 example of scif receive opera tion (example of 8-bit data with parity and 1 stop b it) ............................................................................................................... 571 figure 16.9 cts control oper ation ........................................................................................... 571 figure 16.10 rts control oper ation ......................................................................................... 572 figure 16.11 data format in cl ock synchronous co mmunication ............................................ 572
rev. 2.00 dec. 07, 2005 page xxxii of xlii figure 16.12 sample the sc if initialization flowchart ............................................................. 574 figure 16.13 sample serial transmission flowchart ................................................................. 575 figure 16.14 example of the scif transmit operation............................................................. 576 figure 16.15 sample seri al reception fl owchart ...................................................................... 577 figure 16.16 sample seri al reception fl owchart ...................................................................... 578 figure 16.17 example of th e scif receive operation .............................................................. 579 figure 16.18 sample serial data transmission/reception flowchart ....................................... 581 figure 16.19 receive data sampli ng timing in asynchronous mode ...................................... 584 figure 16.20 sample transfer of synchronous cl ock by dmac .............................................. 585 section 17 serial i/o with fifo (siof) figure 17.1 bloc k diagram of siof .......................................................................................... 58 8 figure 17.2 se rial cloc k supply.............................................................................................. ... 613 figure 17.3 serial data synchronizati on timing ....................................................................... 615 figure 17.4 siof tr ansmit/receive timing .............................................................................. 616 figure 17.5 transmit/receiv e data bit a lignment .................................................................... 618 figure 17.6 control data bit alig nment .................................................................................... 619 figure 17.7 control data interface (slot position) ..................................................................... 620 figure 17.8 control data interface (seconda ry fs) ................................................................... 621 figure 17.9 example of transmi ssion operation in master mode............................................. 624 figure 17.10 example of receptio n operation in ma ster mode ................................................ 625 figure 17.11 example of transm ission operation in slave mode............................................. 626 figure 17.12 example of recep tion operation in slave mode .................................................. 627 figure 17.13 transmission and reception timings (8-bit monaur al data (1)) ......................... 631 figure 17.14 transmission and reception timings (8-bit monaur al data (2)) ......................... 631 figure 17.15 transmission and reception timings (16-bit monaur al data (1)) ....................... 632 figure 17.16 transmission and reception timings (16-bit ster eo data (1)) ............................ 632 figure 17.17 transmission and reception timings (16-bit ster eo data (2)) ............................ 633 figure 17.18 transmission and reception timings (16-bit ster eo data (3)) ............................ 633 figure 17.19 transmission and reception timings (16-bit monaur al data (2)) ....................... 634 section 18 ethernet controller (etherc) figure 18.1 conf iguration of etherc.......................................................................................... 638 figure 18.2 etherc data path and variou s settings................................................................... 707 figure 18.3 etherc tran smitter state tr ansitions ...................................................................... 708 figure 18.4 etherc recei ver state tran smissions ..................................................................... 710 figure 18.5 example of external cam c onnection .................................................................. 714 figure 18.6 external cam signal timing ................................................................................. 716 figure 18.7 (1) mii frame tran smit timing (normal transmission)........................................ 717 figure 18.7 (2) mii frame transmit timing (c ollision) ............................................................ 717 figure 18.7 (3) mii frame tr ansmit timing (transmit error) .................................................. 718
rev. 2.00 dec. 07, 2005 page xxxiii of xlii figure 18.7 (4) mii frame r eceive timing (norma l reception)............................................... 718 figure 18.7 (5) mii frame recei ve timing (reception error (1 ))............................................. 718 figure 18.7 (6) mii fame recei ve timing (reception error (2)) .............................................. 718 figure 18.8 mii mana gement frame format ............................................................................. 719 figure 18.9 (1) 1-bit data write fl owchart ............................................................................... 720 figure 18.9 (2) bus release flowchar t (ta in read in figure 18.8) ......................................... 721 figure 18.9 (3) 1-bit data read flowchart ................................................................................ 721 figure 18.9 (4) independent bus release fl owchart (idle in write in figure 18.8)................ 722 figure 18.10 changing ipg an d transmission efficiency ......................................................... 723 figure 18.11 diagram of qtag additional functions ................................................................. 724 figure 18.12 comparison of normal ethernet frame and ieee802.1q frame (with qtag)...... 724 figure 18.13 example of connection to dp83847 ..................................................................... 725 section 19 ethernet controller di rect memory access controller (e-dmac) figure 19.1 configuration of e-dm ac, and descriptors and buffers....................................... 728 figure 19.2 relationship between transm it descriptor and transmit buffer ............................ 755 figure 19.3 relationship between recei ve descriptor and receive bu ffer ............................... 761 figure 19.4 sample transmission flowchart (single-frame/two-descriptor) ................................ 768 figure 19.5 sample reception flowch art (single-frame/tw o-descriptor) ............................... 770 figure 19.6 e-dmac opera tion after transm it error ............................................................... 771 figure 19.7 e-dmac opera tion after receive error................................................................. 772 figure 19.8 configuration of arbusy ..................................................................................... 773 figure 19.9 summary of receive fifo overflow alert signal ................................................. 774 figure 19.10 arbusy signal change and minimum pulse width depending on increase and decrease of fifo ............................................................................. 775 section 23 user debugging interface (h-udi) figure 23.1 block diagram of h-udi........................................................................................ 793 figure 23.2 tap contro ller state tran sitions ............................................................................ 804 figure 23.3 h-udi da ta transfer timing.................................................................................. 806 figure 23.4 h-udi reset...................................................................................................... ...... 806 section 25 electrical characteristics figure 25.1 power on/off sequence .......................................................................................... 85 6 figure 25.2 extal clock input timing ................................................................................... 861 figure 25.3 ckio clock input timing....................................................................................... 861 figure 25.4 ckio cl ock output timing.................................................................................... 862 figure 25.5 power-on oscillation settlin g time ....................................................................... 862 figure 25.6 oscillation settling time at standby return (ret urn by reset).............................. 862 figure 25.7 oscillation settling time at standby return (r eturn by nmi)............................... 863 figure 25.8 oscillation settling time at standby return (return by irq5 to irq0 and irl3 to irl0 ) ......................................................................................................... 863
rev. 2.00 dec. 07, 2005 page xxxiv of xlii figure 25.9 pll synchronization settling time by re set or nmi ............................................ 863 figure 25.10 pll synchronization se ttling time by irq/ir l interrup ts ................................. 864 figure 25.11 pll synchronization settling time when frequency multiplication ratio modi fied...................................................................................................... 864 figure 25.12 re set input timing.............................................................................................. .. 866 figure 25.13 interrupt signal input timing................................................................................ 866 figure 25.14 bu s release timing .............................................................................................. 866 figure 25.15 pin drive timing at st andby................................................................................. 867 figure 25.16 irqout output dela y time................................................................................ 867 figure 25.17 basic bus cycle (n o wait) ................................................................................... 870 figure 25.18 basic bus cy cle (one software wait) .................................................................. 871 figure 25.19 basic bus cy cle (one extern al wait) ................................................................... 872 figure 25.20 basic bus cycle (one software wait, external wait enabled (wm bit = 0), no idle cycl e setting) .......................................................................................... 873 figure 25.21 burst rom read cycle (one access wait, one external wait, one burst wait, tw o bursts)................................................................................ 874 figure 25.22 synchronous dram single read bus cycle (auto precharge, cas latency = 2, trcd = 1 cycle, trp = 1 cycle)........................................... 875 figure 25.23 synchronous dram single read bus cycle (auto precharge, cas latency = 2, trcd = 2 cycle, trp = 2 cycle)........................................... 876 figure 25.24 synchronous dram burst read bus cycle (single read 4), (auto precharge, cas latency = 2, trcd = 1 cycle, trp = 2 cycle)............... 877 figure 25.25 synchronous dram burst read bus cycle (single read 4), (auto precharge, cas latency = 2, trcd = 2 cycle, trp = 1 cycle)............... 878 figure 25.26 synchronous dram single write bus cycle (auto precharge, trwl = 2 cy cle) ................................................................................................. 879 figure 25.27 synchronous dram single write bus cycle (auto precharge, trcd = 3 cycle, trwl = 2 cycl e) .................................................................... 880 figure 25.28 synchronous dram burst write bus cycle (single write 4), (auto precharge, trcd = 1 cycle, trwl = 2 cycle) ........................................ 881 figure 25.29 synchronous dram burst write bus cycle (single write 4), (auto precharge, trcd = 2 cycle, trwl = 2 cycle) ........................................ 882 figure 25.30 synchronous dram burst read bus cycle (single read 4) (bank active mode, actv + read commands, cas latency = 2, trcd = 1 cycle) .................................................................................................. 883 figure 25.31 synchronous dram burst read bus cycle (single read 4) (bank active mode, read command, same row address, cas latency = 2, trcd = 1 cycle) .................................................................................................. 884
rev. 2.00 dec. 07, 2005 page xxxv of xlii figure 25.32 synchronous dram burst read bus cycle (single read 4) (bank active mode, pre + actv + read commands, different row address, cas late ncy = 2, trcd = 1 cycle) ............................. 885 figure 25.33 synchronous dram burst write bus cycle (single write 4) (bank active mode, actv + write commands, trcd = 1 cycle, trwl = 1 cy cle) ................................................................................................. 886 figure 25.34 synchronous dram burst write bus cycle (single write 4) (bank active mode, write command, same row address, trcd = 1 cycle, trwl = 1 cy cle) ................................................................................................. 887 figure 25.35 synchronous dram burst write bus cycle (single write 4) (bank active mode, pre + actv + write commands, different row address, trcd = 1 cycle, trwl = 1 cycle) ............................. 888 figure 25.36 synchronous dram auto -refresh timing (trp = 2 cycl e) .............................. 889 figure 25.37 synchronous dram sel f-refresh timing (trp = 2 cycle) ................................ 890 figure 25.38 synchronous dram mode re gister write timing (trp = 2 cycle)................... 891 figure 25.39 pcmcia memory card interface bus timing ..................................................... 892 figure 25.40 pcmcia memory card in terface bus timing (ted[3:0] = b'0010, teh[3:0] = b'0001, one software wait, one hardware wait)............................ 893 figure 25.41 pcmcia i/o ca rd interface bus timing.............................................................. 894 figure 25.42 pcmcia i/o card interface bus timing (ted[3:0] = b'0010, teh[3:0] = b'0001, one software wait, one hardware wait)............................ 895 figure 25.43 refout delay time ........................................................................................... 895 figure 25.44 access timing in low- frequency mode (auto precharge).................................. 897 figure 25.45 synchronous dram auto-refresh timing (trp = 2 cycle, low- frequency mode) .............................................................. 898 figure 25.46 synchronous dram self-refresh timing (trp = 2 cycle, low- frequency mode) .............................................................. 899 figure 25.47 synchronous dram mode register write timing (trp = 2 cycle, low- frequency mode) .............................................................. 900 figure 25.48 dreqn input timing ............................................................................................ 90 1 figure 25.49 tendn, dac kn output timing .......................................................................... 901 figure 25.50 oscillation settling time when rtc crystal oscillato r is turned on ................. 902 figure 25.51 scifnck input clock timing .............................................................................. 903 figure 25.52 scif input/output ti ming in clock synchronous mode...................................... 904 figure 25.53 siom clk input ti ming....................................................................................... 905 figure 25.54 siof transmit/receive timing (master mode 1: fa ll sampling time)............... 905 figure 25.55 siof transmit/receive timing (master mode 1: rise sampling time).............. 906 figure 25.56 siof transmit/receive timing (master mode 2: fa ll sampling time)............... 906 figure 25.57 siof transmit/receive timing (master mode 2: rise sampling time).............. 907 figure 25.58 siof transmit/receive timi ng (slave mode 1 and slave mode 2)..................... 907
rev. 2.00 dec. 07, 2005 page xxxvi of xlii figure 25.59 mii transmit timing (normal operation)............................................................ 909 figure 25.60 mii transmit timing (case of conflict)............................................................... 909 figure 25.61 mii receive timing (normal operation) ............................................................. 910 figure 25.62 mii receive timing (case of error) ..................................................................... 910 figure 25.63 mdio input timing .............................................................................................. 9 10 figure 25.64 mdio output timing ........................................................................................... 910 figure 25.65 wol output timing ............................................................................................. 91 1 figure 25.66 exou t output timing......................................................................................... 911 figure 25.67 cams en input timing ........................................................................................ 911 figure 25.68 arbuby output timing ..................................................................................... 911 figure 25.69 i/o port timing ................................................................................................. .... 912 figure 25.70 tck input timing................................................................................................ .913 figure 25.71 trst input timing (res et hold).......................................................................... 914 figure 25.72 h-udi da ta transfer timing................................................................................ 914 figure 25.73 asemd0 input timing......................................................................................... 914 figure 25.74 asebrkak delay ti me ..................................................................................... 914 figure 25.75 output load circuit ............................................................................................. .915 figure 25.76 load cap acitance vs. de lay time......................................................................... 916 appendix figure b.1 package dimensions (hqfp2828-256 (fp-256g/gv))........................................... 926 figure b.2 package dimensions (p-lfbga1717-256 (b p-256h/hv)) .................................... 927
rev. 2.00 dec. 07, 2005 page xxxvii of xlii tables section 1 overview table 1.1 pin assigument ....................................................................................................... 10 table 1.2 pin functions .......................................................................................................... 19 section 2 cpu table 2.1 logical addr ess space............................................................................................ 30 table 2.2 register initia l values............................................................................................. 33 table 2.3 addressing modes and effective ad dresses for cpu instructions......................... 45 table 2.4 cpu instruction formats ........................................................................................ 49 table 2.5 cpu instruction types............................................................................................ 52 table 2.6 data transfer instructions....................................................................................... 56 table 2.7 arithmetic operatio n instructions .......................................................................... 58 table 2.8 logic operation instructions .................................................................................. 60 table 2.9 shift instru ctions..................................................................................................... 61 table 2.10 branch instructions ................................................................................................. 62 table 2.11 system control instructions.................................................................................... 63 table 2.12 operation code map............................................................................................... 66 section 3 dsp operating unit table 3.1 logical addr ess space............................................................................................ 73 table 3.2 operation of sr bits in each processing mode ..................................................... 76 table 3.3 rs and re setting rule.......................................................................................... 82 table 3.4 repeat control instructions .................................................................................... 82 table 3.5 repeat contro l macros ........................................................................................... 83 table 3.6 dsp mode extended system control instructions ................................................. 84 table 3.7 pc value during repeat control (when rc[11:0] 2) ......................................... 87 table 3.8 extended repeat cont rol instru ctions .................................................................... 91 table 3.9 extended system control in structions in dsp mode ............................................. 96 table 3.10 overview of data transfer instructions.................................................................. 99 table 3.11 modulo addressing cont rol instruc tions.............................................................. 101 table 3.12 double data transfer in struction formats ........................................................... 104 table 3.13 single data transfer in struction formats ............................................................. 105 table 3.14 destination register in dsp instru ctions.............................................................. 107 table 3.15 source register in dsp operations ...................................................................... 108 table 3.16 dsr register bits................................................................................................. 109 table 3.17 dsp operation instru ction form ats ...................................................................... 112 table 3.18 correspondence between dsp instruc tion operands and registers ..................... 112 table 3.19 dc bit update definitions.................................................................................... 114
rev. 2.00 dec. 07, 2005 page xxxviii of xlii table 3.20 examples of nopx and nopy instruction codes............................................... 116 table 3.21 variation of alu fixed- point opera tions............................................................ 119 table 3.22 correspondence between oper ands and registers ............................................... 119 table 3.23 variation of alu inte ger operations ................................................................... 124 table 3.24 variation of alu logi cal operations .................................................................. 125 table 3.25 variation of fixed-point multiply oper ation ....................................................... 127 table 3.26 correspondence between oper ands and registers ............................................... 127 table 3.27 variation of shif t operations................................................................................ 128 table 3.28 operation definition of pdmsb .......................................................................... 134 table 3.29 variation of pdms b operation............................................................................ 135 table 3.30 variation of roundin g operation ......................................................................... 136 table 3.31 definition of overflow protection for fixed-point arithmetic operations .......... 137 table 3.32 definition of overflow protection fo r integer arithmetic operations.................. 137 table 3.33 variation of local data move oper ations............................................................ 138 table 3.34 correspondence between oper ands and registers ............................................... 139 table 3.35 dsp mode extended system control instructions ............................................... 140 table 3.36 double data transfer instruction ......................................................................... 142 table 3.37 single data transfer instructions ......................................................................... 143 table 3.38 correspondence between dsp data tran sfer operands and registers ................ 144 table 3.39 dsp operation in structions .................................................................................. 145 table 3.40 operation code map............................................................................................. 151 section 4 exception handling table 4.1 exception event vectors ...................................................................................... 163 table 4.2 instruction positions and restriction types.......................................................... 173 table 4.3 spc value when re-execution type exce ption occurs in repeat control (rc[11:0] 2) ...................................................................................................... 176 table 4.4 exception acceptance in repeat loop ................................................................. 177 table 4.5 instruction where a specific exce ption occurs when memory access exception occurs in repeat control (sr.rc[11:0] 1).......................... 178 section 5 memory management unit (mmu) table 5.1 access states designated by d, c, and pr bits ................................................... 199 section 6 cache table 6.1 lru and way replacement (when cache locking mechanism is disabled)...... 216 table 6.2 way replacement when a pref inst ruction misses th e cache ........................... 220 table 6.3 way replacement when instructions ot her than the pref instruction miss the c ache...................................................................................................... 220 table 6.4 lru and way replacement (when w2lo ck = 1 and w3lock =0)................ 220 table 6.5 lru and way replacement (when w2lo ck = 0 and w3lock =1)................ 221 table 6.6 lru and way replacement (when w2lo ck = 1 and w3lock =1)................ 221
rev. 2.00 dec. 07, 2005 page xxxix of xlii section 7 x/y memory table 7.1 x/y memory logical addresses .......................................................................... 231 table 7.2 mmu and cache settings..................................................................................... 234 section 8 interrupt controller (intc) table 8.1 pin configuration.................................................................................................. 237 table 8.2 interrupt exception handling sources and priority (irq mode) ......................... 240 table 8.3 interrupt exception handling sources and priority (irl mode).......................... 243 table 8.4 interrupt level and intevt code....................................................................... 245 table 8.5 interrupt sources and ipra to ipri ..................................................................... 247 section 9 user break controller table 9.1 specifying break addr ess regist er ...................................................................... 269 table 9.2 specifying break da ta regist er............................................................................ 271 table 9.3 data access cycle addresses and oper and size comparison conditions ........... 284 section 10 power-down modes table 10.1 states of power- down modes .............................................................................. 296 table 10.2 pin configuration.................................................................................................. 298 table 10.3 register states in soft ware standby mode........................................................... 303 section 11 on-chip oscillation circuits table 11.1 pin configuration.................................................................................................. 315 table 11.2 clock operatin g modes ........................................................................................ 315 table 11.3 possible combination of clock mode and frqcr values.................................. 317 section 12 bus state controller (bsc) table 12.1 pin configuration.................................................................................................. 334 table 12.2 address space map 1 (cmncr.map = 0).......................................................... 338 table 12.3 address space map 2 (cmncr.map = 1).......................................................... 339 table 12.4 correspondence between external pins (md3 and md4), memory type of cs0, an d memory bus width................................................... 340 table 12.5 correspondence between external pin (md5) and endians ................................. 340 table 12.6 32-bit external device/big endian access and data alignment ......................... 383 table 12.7 16-bit external device/big endian access and data alignment ......................... 384 table 12.8 8-bit external device/big endian access and data alignment........................... 385 table 12.9 32-bit external device/little endian access and data alignment ...................... 386 table 12.10 16-bit external device/little endian access and data alignment ...................... 387 table 12.11 8-bit external device/little endian access and data alignment ........................ 388 table 12.12 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex ou tput (1)- 1............................................................................ 401 table 12.12 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex ou tput (1)- 2............................................................................ 403
rev. 2.00 dec. 07, 2005 page xl of xlii table 12.13 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex ou tput (2)- 1 ........................................................................... 404 table 12.13 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex ou tput (2)- 2 ........................................................................... 405 table 12.14 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex ou tput (3 )............................................................................... 407 table 12.15 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex ou tput (4)- 1 ........................................................................... 408 table 12.15 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex ou tput (4)- 2 ........................................................................... 409 table 12.16 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex ou tput (5)- 1 ........................................................................... 410 table 12.16 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex ou tput (5)- 2 ........................................................................... 411 table 12.17 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex ou tput (6)- 1 ........................................................................... 412 table 12.17 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex ou tput (6)- 2 ........................................................................... 413 table 12.18 relationship between access size and number of bursts.................................... 414 table 12.19 access address in sdram m ode register write ............................................... 434 table 12.20 output addresses when emrs command is issued ............................................ 437 table 12.21 relationship between bus width, acce ss size, and number of bursts................ 440 section 13 direct memo ry access controller (dmac) table 13.1 pin configuration.................................................................................................. 461 table 13.2 dmars settin g.................................................................................................... 474 table 13.3 selecting external request modes with rs bits .................................................. 477 table 13.4 selecting external request det ection with dl, ds bits ...................................... 478 table 13.5 selecting external request de tection with do bit .............................................. 478 table 13.6 selecting on-chip peripheral module re quest modes with rs3 to rs0 bits ..... 479 table 13.7 supported dma transfers.................................................................................... 482 table 13.8 relationship of request modes and bus modes by dma transfer category ..... 488 section 14 timer unit (tmu) table 14.1 tmu interrupt sources......................................................................................... 504 section 15 realtime clock (rtc) table 15.1 pin configuration.................................................................................................. 507 table 15.2 recommended oscillator circuit cons tants (recommended values).................. 528 section 16 serial communicati on interface with fifo (scif) table 16.1 pin configuration.................................................................................................. 534
rev. 2.00 dec. 07, 2005 page xli of xlii table 16.2 relationship between n and clock........................................................................ 553 table 16.3 scsmr settings for serial tran sfer format se lection......................................... 560 table 16.4 scsmr and scscr settings for the sc if clock source selection .................... 560 table 16.5 serial transfer formats......................................................................................... 562 table 16.6 the scif interr upt sources .................................................................................. 583 section 17 serial i/o with fifo (siof) table 17.1 pin configuration.................................................................................................. 589 table 17.2 siof serial cloc k frequency ............................................................................... 614 table 17.3 serial transfer modes........................................................................................... 616 table 17.4 frame length........................................................................................................ 617 table 17.5 audio mode specification for transmit data....................................................... 619 table 17.6 audio mode specification for receive data ........................................................ 619 table 17.7 setting for number of cont rol data ch annels...................................................... 620 table 17.8 conditions to issue transmit request .................................................................. 622 table 17.9 conditions to issue receive request .................................................................... 622 table 17.10 transmission and r eception rese t ....................................................................... 628 table 17.11 siof interrupt sources ......................................................................................... 629 table 17.12 setting condition of transmit/r eceive interrupt flag.......................................... 630 section 18 ethernet controller (etherc) table 18.1 pin configuration.................................................................................................. 639 table 18.2 transfer frame processi ng (without cam)......................................................... 711 table 18.3 reception frame process...................................................................................... 713 table 18.4 relay frame proces s (with ca m) ....................................................................... 713 table 18.5 receive frame process (when exte rnal cam logic is used)............................. 715 table 18.6 relay frame process (when extern al cam logic is used) ................................ 716 section 21 pin function controller (pfc) table 21.1 list of multiplexe d pins (1 ).................................................................................. 781 table 21.2 list of multiplexe d pins (2 ).................................................................................. 782 section 22 i/o ports table 22.1 port a data register (padr) read/write operations ......................................... 790 table 22.2 port b data register (pbdr) r ead/write operations (1) .................................... 791 table 22.3 port b data register (pbdr) r ead/write operations (2) .................................... 791 table 22.4 port c data register (pcdr) read/write operations.......................................... 792 section 23 user debugging interface (h-udi) table 23.1 pin configuration.................................................................................................. 794 table 23.2 h-udi commands................................................................................................ 796 table 23.3 this lsi?s pins and boundar y scan regist er bits................................................ 797 table 23.4 reset configur ation .............................................................................................. 805
rev. 2.00 dec. 07, 2005 page xlii of xlii section 25 electrical characteristics table 25.1 absolute maximum ratings ................................................................................. 855 table 25.2 dc characteris tics (1) .......................................................................................... 857 table 25.2 dc characteris tics (2) .......................................................................................... 858 table 25.3 permitted output cu rrent values.......................................................................... 859 table 25.4 maximum operating frequencies......................................................................... 859 table 25.5 clock timing ........................................................................................................ 860 table 25.6 control signal timing .......................................................................................... 865 table 25.7 bus timing (1)...................................................................................................... 868 table 25.8 bus timing (2)...................................................................................................... 896 table 25.9 dmac signal timing .......................................................................................... 901 table 25.10 rtc signal timing............................................................................................... 902 table 25.11 scif module signa l timing................................................................................. 903 table 25.12 siof module si gnal timing ................................................................................ 904 table 25.13 ethernet contro ller timing................................................................................... 908 table 25.14 port input/output timing ..................................................................................... 912 table 25.15 h-udi related pi n timing................................................................................... 913
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 1 of 950 rej09b0079-0200 section 1 overview and pin function this lsi is a 32-bit reduced instruction set computer (risc) microprocessor that is built on the superh architecture. its core is a risc-type cpu with a digital signa l processor (dsp) as a f unctional extension. a single chip microprocessor integrates peripheral functions required for building an ethernet system. the lsi comprises two channels of ethernet c ontrollers. they include a media access controller (mac) and a media independent interface (mii) standard unit that conforms to the iee802.3u standard and provide 10/100 m bps lan connection. th e on-chip ip security accelerator enables efficient security management of network data. the lsi has a large capacity (32-kbyte) cache memory, 16-kbyte on-chip x/y memory, and an interrupt controller for system configuration to en able flexible system design. it supports high- speed data transfer using an on-chip direct memory access controller (dmac). its external memory access support provides direct co nnection to various types of memory. the strong on-chip power saving function reduces power consumption even during high-speed operation. 1.1 features the features of this lsi are shown below. cpu: ? ? ? ? ? ?
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 2 of 950 rej09b0079-0200 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 3 of 950 rej09b0079-0200 cache memory: ? ? ? ? ? ? ? ? irl3 to irl0 ) ? irqout ) ? ? ? ? ? ? ? ?
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 4 of 950 rej09b0079-0200 ? ? ? ? ? cs0 , cs2 to cs4 , cs5a/b , and cs6a/b ) for corresponding area (the cs assert/negate timing can be selected by software.) direct memory access controller (dmac): ? ? ? ? ? ?
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 5 of 950 rej09b0079-0200 serial communication int erface with fifo (scif): ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 6 of 950 rej09b0079-0200 ? ? ? ? ? ? ? ? ? ? ? HD6417710bp/bpv 256-pin csp (bp-256h/hv) sh7710 3.3 v 0.3 v 1.5 v 0.1 v 200 mhz HD6417710f/fv 256-pin hqfp (fp-256g/gv)
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 7 of 950 rej09b0079-0200 1.2 block diagram superh cpu core x/y memory instructions/data for cpu/dsp 16 kbytes user break controller (ubc) dsp core cache access controller (ccn) direct memory access controller (dmac) memory management unit (mmu) cache memory 32 kbytes bus state controller (bsc) ip security accelerator (ipsec) peripheral bus controller ethernet controller direct memory access controller (e-dmac) cpu bus (i clock) internal bus (b clock) external bus note: * scif and siof have two channels respectively. 128-byte sram serial i/o with fifo (siof) * user debugging interface (h-udi) interrupt controller (intc) realtime clock (rtc) timer unit (tmu) on-chip oscillation circuits (cpg) (wdt) serial communication interface with fifo (scif) * transmit fifo (2 kbytes) ethernet controller 0 (etherc0) ethernet controller 1 (etherc1) transfer fifo (3 kbytes) transfer fifo (3 kbytes) receive fifo (2 kbytes) transmit fifo (2 kbytes) receive fifo (2 kbytes) x bus y bus ethernet 0 ethernet 1 peripheral bus (p clock) advanced user debugger (aud) l bus figure 1.1 block diagram
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 8 of 950 rej09b0079-0200 1.3 pin description 1.3.1 pin assignment hqfp2828-256 (fp-256g/gv) top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 refout / irqout / arbusy breq vccq(3.3v) vssq(0v) back cs0 cs4 cs5a cs6a wait rd bs vccq(3.3v) vssq(0v) vcc(1.5v) vss(0v) d0 d1 d2 d3 d4 d5 d6 d7 vccq(3.3v) vssq(0v) d8 d9 d10 d11 d12 d13 d14 d15 vcc(1.5v) vss(0v) we0 ( be0 )/dqmll we1 ( be1 )/dqmlu/ we rd/ wr ckio cas cke vccq(3.3v) vssq(0v) ras cs2 cs3 a0 vcc(1.5v) vss(0v) a1 a2 a3 a4 a5 a6 vccq(3.3v) vssq(0v) a7 a8 a9 a10 a11 a12 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 vccq(3.3v) vssq(0v) vccq(3.3v) md5 md4 vssq(0v) vssq(0v) vccq(3.3v) camsen0/irq4 exout0/tend0 lnksta0 wol0 mdio0 mdc0 erxd03 vss(0v) vcc(1.5v) erxd02 erxd01 erxd00 rx-dv0 rx-clk0 rx-er0 tx-er0 vssq(0v) vccq(3.3v) tx-clk0 tx-en0 etxd00 etxd01 etxd02 etxd03 col0 vss(0v) vcc(1.5v) crs0 camsen1/irq5 exout1/tend1 lnksta1 wol1 mdio1 mdc1 erxd13 vssq(0v) vccq(3.3v) vss(0v) vcc(1.5v) erxd12 erxd11 erxd10 rx-dv1 rx-clk1 rx-er1 tx-er1 tx-clk1 vssq(0v) vccq(3.3v) tx-en1 etxd10 etxd11 etxd12 etxd13 col1 crs1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 vccq(3.3v) pta7/siofsync0 pta6/txd_sio0 pta5/rxd_sio0 pta4/siomclk0 pta3/sck_sio0 vssq(0v) vccq(3.3v) pta2/scif0ck pta1/txd0 pta0/rxd0 ptb7/ rts0 ptb6/ cts0 ptb5/scif1ck vss(0v) vcc(1.5v) ptb4/txd1 ptb3/rxd1 ptb2/ rts1 ptb1/ cts1 vssq(0v) vccq(3.3v) ptb0 a25 a24 a23 a22 a21 vss(0v) vcc(1.5v) a20 a19 a18 d31 d30 vssq(0v) vccq(3.3v) d29 d28 d27 d26 d25 d24 d23 vss(0v) vcc(1.5v) vssq(0v) vccq(3.3v) d22 d21 d20 d19 d18 d17 d16 vssq(0v) vccq(3.3v) we3 ( be3 )/dqmuu/ iciow r we2 ( be2 )/dqmul/ iciord a17 a16 a15 a14 a13 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 vccq-rtc(3.3v) xtal2 extal2 vssq-rtc(0v) asemd0 tdi tms tdo trst tck asebrkak audsync audck vcc(1.5v) vss(0v) vccq(3.3v) vssq(0v) audata3 audata2 audata1 audata0 resetm resetp nmi irq0/ irl0 irq1/ irl1 irq2/ irl2 irq3/ irl3 vcc(1.5v) vss(0v) status0 status1 ckio2 dack0 vccq(3.3v) vssq(0v) dack1 dreq0 dreq1 ptc0/sck_sio1 ptc1/siomclk1 ptc2/rxd_sio1 vcc(1.5v) vss(0v) ptc3/txd_sio1 ptc4/siofsync1 ptc5/ ce2a ptc6/ ce2b vccq(3.3v) vssq(0v) ptc7/ iois16 cs5b / ce1a cs6b / ce1b vssq(0v) md0 md1 md2 md3 vcc-pll1(1.5v) vss-pll1(0v) vcc-pll2(1.5v) vss-pll2(0v) xtal extal figure 1.2 pin assignment (hqfp2828-256 (fp-256g/gv))
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 9 of 950 rej09b0079-0200 a b c d e f g h j k l m n p r t u v w y 1234567891011121314151617181920 extal md3 md1 cs5b / ce1a cs6b / ce1b ptc6/ ce2b ptc4/ siofsync1 ptc1/ siomclk1 ptc2/ rxd_sio1 dreq0 dack0 dack1 status 1 status 0 irq2/ irl2 resetp au data 0 au data 2 au data 1 au data 3 vssq audck trst tms vssq- rtc vccq- rtc vccq vccq vccq vssq vssq vccq vssq vccq vssq vssq refout / irqout / arbusy xtal md2 md0 vss-pll1 vssq vssq vss ptc0/ sck_sio1 ptc3/ txd_sio1 vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vcc vcc vcc vcc vcc irq0/ irl0 nmi vss asebrkak audsync asemd0 extal2 xtal2 cs4 cs6a cs5a breq vcc-pll1vss-pll2 vcc-pll2 ptc7/ iois16 ptc5/ ce2a vcc vccq vccq vccq vccq vccq vccq vccq vccq vccq vccq vccq vccq dreq1 vccq vcc vccq irq3/ irl3 irq1/ irl1 tdi vssq vssq tdo camsen0 / /irq4 ckio2 vss vss resetm tck exout0/ tend0 mdio0 back cs0 wait wol0 md5 md4 vcc vcc vcc vccq vcc vss vss vss d0 d4 d6 d8 d12 d10 d9 d11 d7 d2 d3 d5 d1 rd bs mdc0 lnksta0 lnksta1 erxd01 erxd00 etxd03 etxd01 etxd00 erxd02 erxd03 rx-er0 tx-er0 tx-en0 rx-clk0 rx-dv0 tx-clk0 etxd02 col0 d13 d15 d14 vss vss vss vss vss camsen1/ irq5 crs0 ckio rd/ wr we0 ( be0 )/ dqmll we1 ( be1 )/ dqmlu/ we we2 ( be2 )/ dqmul/ iciord we3 ( be3 )/ dqmuu/ iciowr mdio1 wol1 exout1/ tend1 cas erxd13 erxd12 erxd11 erxd10 mdc1 cke cs3 ras cs2 a4 a1 vcc rx-dv1 rx-er1 tx-er1 a0 a8 a9 a3 tx-clk1 etxd10 etxd11 rx-clk1 a2 a10 a5 d16 d20 d24 d28 d30 a19 a21 a25 ptb1/ cts1 ptb6/ cts0 ptb7/ rts0 ptb2/ rts1 pta1/ txd0 ptb4/ txd1 pta0/ rxd0 ptb3/ rxd1 etxd13 a6 a11 a7 d18 d22 d26 a23 a24 ptb5/ scif1ck pta4/ siomclk0 pta5/ rxd-sio0 pta6/ txd-sio0 pta3/ sck-sio0 pta7/ siofsync0 pta2/ scif0clk col1 tx-en1 a13 a14 a15 a17 d17 d21 d27 crs1 etxd12 a12 a16 d19 d23 d25 d29 d31 a18 a20 a22 ptb0 p-lfbga1717-256 (bp-256h/hv) top view index figure 1.3 pin assignment (p-lfbga1717-256 (bp-256h/hv))
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 10 of 950 rej09b0079-0200 table 1.1 pin assigument pin no. ( fp-256g/gv) pin no. (bp-256h/hv ) pin name i/o description 1 b2 refout / irqout/ arbusy o/o/o bus release request output 2 c2 breq i bus request 3 d2 vccq i/o power supply (3.3 v) 4 b1 vssq i/o power supply (0 v) 5 e2 back o bus acknowledge 6 e3 cs0 o chip select 0 7 c1 cs4 o chip select 4 8 d3 cs5a o chip select 5 a 9 d1 cs6a o chip select 6 a 10 e4 wait i hardware wait request 11 f2 rd o read strobe 12 f3 bs o bus cycle start signal 13 e1 vccq i/o power supply (3.3 v) 14 f4 vssq i/o power supply (0 v) 15 g2 vcc internal power supply (1.5 v) 16 g3 vss internal power supply (0 v) 17 f1 d0 io data bus 18 g4 d1 io data bus 19 h2 d2 io data bus 20 h3 d3 io data bus 21 g1 d4 io data bus 22 h4 d5 io data bus 23 h1 d6 io data bus 24 j3 d7 io data bus 25 j2 vccq i/o power supply (3.3 v) 26 j4 vssq i/o power supply (0 v) 27 j1 d8 io data bus 28 k3 d9 io data bus 29 k2 d10 io data bus
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 11 of 950 rej09b0079-0200 pin no. ( fp-256g/gv) pin no. (bp-256h/hv ) pin name i/o description 30 k4 d11 io data bus 31 k1 d12 io data bus 32 l1 d13 io data bus 33 l4 d14 io data bus 34 m1 d15 io data bus 35 l3 vcc internal power supply (1.5 v) 36 l2 vss internal power supply (0 v) 37 m4 we0 ( be0 )/dqmll o/o d7 to d0-select signal/dqm (sdram) 38 n1 we1 ( be1 )/dqmlu/ we o/o/o d15 to d8-select signal/dqm (sdram)/pcmcia write cycle strobe 39 m3 rd/ wr o read/write 40 m2 ckio io system clock i/o 41 n4 cas o cas (sdram) 42 p1 cke o ck enable (sdram) 43 n3 vccq i/o power supply (3.3 v) 44 n2 vssq i/o power supply (0 v) 45 p4 ras o ras (sdram) 46 r1 cs2 o chip select 2 47 p3 cs3 o chip select 3 48 t1 a0 o address bus 49 r4 vcc internal power supply (1.5 v) 50 p2 vss internal power supply (0 v) 51 r3 a1 o address bus 52 u1 a2 o address bus 53 t4 a3 o address bus 54 r2 a4 o address bus 55 u4 a5 o address bus 56 v1 a6 o address bus 57 u2 vccq i/o power supply (3.3 v) 58 w1 vssq i/o power supply (0 v) 59 v3 a7 o address bus
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 12 of 950 rej09b0079-0200 pin no. ( fp-256g/gv) pin no. (bp-256h/hv ) pin name i/o description 60 t2 a8 o address bus 61 t3 a9 o address bus 62 u3 a10 o address bus 63 v2 a11 o address bus 64 y1 a12 o address bus 65 w2 a13 o address bus 66 w3 a14 o address bus 67 w4 a15 o address bus 68 y2 a16 o address bus 69 w5 a17 o address bus 70 v5 we2 ( be2 )/dqmul/ iciord o/o/o d23 to d16-select signal/dqm (sdram)/pcmcia i/o read 71 y3 we3 ( be3 )/dqmuu/ iciowr o/o/o d31 to d24-select signal/dqm (sdram)/pcmcia i/o write 72 v4 vccq i/o power supply (3.3 v) 73 y4 vssq i/o power supply (0 v) 74 u5 d16 io data bus 75 w6 d17 io data bus 76 v6 d18 io data bus 77 y5 d19 io data bus 78 u6 d20 io data bus 79 w7 d21 io data bus 80 v7 d22 io data bus 81 y6 vccq i/o power supply (3.3 v) 82 u7 vssq i/o power supply (0 v) 83 w8 vcc internal power supply (1.5 v) 84 v8 vss internal power supply (0 v) 85 y7 d23 io data bus 86 u8 d24 io data bus 87 y8 d25 io data bus 88 v9 d26 io data bus
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 13 of 950 rej09b0079-0200 pin no. ( fp-256g/gv) pin no. (bp-256h/hv ) pin name i/o description 89 w9 d27 io data bus 90 u9 d28 io data bus 91 y9 d29 io data bus 92 v10 vccq i/o power supply (3.3 v) 93 w10 vssq i/o power supply (0 v) 94 u10 d30 io data bus 95 y10 d31 io data bus 96 y11 a18 o address bus 97 u11 a19 o address bus 98 y12 a20 o address bus 99 v11 vcc internal power supply (1.5 v) 100 w11 vss internal power supply (0 v) 101 u12 a21 o address bus 102 y13 a22 o address bus 103 v12 a23 o address bus 104 w12 a24 o address bus 105 u13 a25 o address bus 106 y14 ptb0 io i/o port b 107 v13 vccq i/o power supply (3.3 v) 108 w13 vssq i/o power supply (0 v) 109 u14 ptb1/ cts1 io/i i/o port b/scif1 transmit clear 110 y15 ptb2/ rts1 io/o i/o port b/scif1 transmit request 111 v14 ptb3/rxd1 io/i i/o port b/scif1 receive data 112 y16 ptb4/txd1 io/o i/o port b/scif1 transmit data 113 u15 vcc internal power supply (1.5 v) 114 w14 vss internal power supply (0 v) 115 v15 ptb5/scif1ck io/io i/o port b/scif1 serial clock 116 y17 ptb6/ cts0 io/i i/o port b/scif0 transmit clear 117 u16 ptb7/ rts0 io/o i/o port b/scif0 transmit request 118 w15 pta0/rxd0 io/i i/o port a/scif0 receive data 119 u17 pta1/txd0 io/o i/o port a/scif0 transmit data
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 14 of 950 rej09b0079-0200 pin no. ( fp-256g/gv) pin no. (bp-256h/hv ) pin name i/o description 120 y18 pta2/scif0ck io/io i/o port a/scif0 serial clock 121 w17 vccq i/o power supply (3.3 v) 122 y19 vssq i/o power supply (0 v) 123 v18 pta3/sck_sio0 io/io i/o port a/siof0 communication clock 124 w16 pta4/siomclk0 io/i i/o port a/siof0 clock input 125 v16 pta5/rxd_sio0 io/i i/o port a/siof0 receive data 126 v17 pta6/txd_sio0 io/o i/o port a/siof0 transmit data 127 w18 pta7/siofsync0 io/io i/o port a/siof0 frame sync 128 y20 vccq i/o power supply (3.3 v) 129 w19 crs1 i mac1 carrier detection 130 v19 col1 i mac1 collision detection 131 u19 etxd13 o mac1 transmit data 3 132 w20 etxd12 o mac1 transmit data 2 133 t19 etxd11 o mac1 transmit data 1 134 t18 etxd10 o mac1 transmit data 0 135 v20 tx-en1 o mac1 transmit enable 136 u18 vccq i/o power supply (3.3 v) 137 u20 vssq i/o power supply (0 v) 138 t17 tx-clk1 i mac1 transmit clock 139 r19 tx-er1 o mac1 transmit error 140 r18 rx-er1 i mac1 receive error 141 t20 rx-clk1 i mac1 receive clock 142 r17 rx-dv1 i mac1 receive data valid 143 p19 erxd10 i mac1 receive data 0 144 p18 erxd11 i mac1 receive data 1 145 r20 erxd12 i mac1 receive data 2 146 p17 vcc internal power supply (1.5 v) 147 n19 vss internal power supply (0 v) 148 n18 vccq i/o power supply (3.3 v) 149 p20 vssq i/o power supply (0 v)
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 15 of 950 rej09b0079-0200 pin no. ( fp-256g/gv) pin no. (bp-256h/hv ) pin name i/o description 150 n17 erxd13 i mac1 receive data 3 151 n20 mdc1 o mac1 management data clock 152 m18 mdio1 io mac1 management data i/o 153 m19 wol1 o mac1 wake-on-lan 154 m17 lnksta1 i mac1 link status 155 m20 exout1/tend1 o/o mac1 general-purpose external output/dma transfer end notification 1 156 l18 camsen1/irq5 i/i mac1 cam input/external interrupt request 157 l19 crs0 i mac0 carrier detection 158 l17 vcc internal power supply (1.5 v) 159 l20 vss internal power supply (0 v) 160 k20 col0 i mac0 collision detection 161 k17 etxd03 o mac0 transmit data 3 162 j20 etxd02 o mac0 transmit data 2 163 k18 etxd01 o mac0 transmit data 1 164 k19 etxd00 o mac0 transmit data 0 165 j17 tx-en0 o mac0 transmit enable 166 h20 tx-clk0 i mac0 transmit clock 167 j18 vccq i/o power supply (3.3 v) 168 j19 vssq i/o power supply (0 v) 169 h17 tx-er0 o mac0 transmit error 170 g20 rx-er0 i mac0 receive error 171 h18 rx-clk0 i mac0 receive clock 172 h19 rx-dv0 i mac0 receive data valid 173 g17 erxd00 i mac0 receive data 0 174 f20 erxd01 i mac0 receive data 1 175 g18 erxd02 i mac0 receive data 2 176 e20 vcc internal power supply (1.5 v) 177 f17 vss internal power supply (0 v) 178 g19 erxd03 i mac0 receive data 3
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 16 of 950 rej09b0079-0200 pin no. ( fp-256g/gv) pin no. (bp-256h/hv ) pin name i/o description 179 f18 mdc0 o mac0 management data clock 180 d20 mdio0 io mac0 management data i/o 181 e17 wol0 o mac0 wake-on-lan 182 f19 lnksta0 i mac0 link status 183 d17 exout0/tend0 o/o mac0 general-purpose external output/dma transfer end notification 0 184 c20 camsen0/irq4 i/i mac0 cam input/external interrupt request 185 d19 vccq i/o power supply (3.3 v) 186 b20 vssq i/o power supply (0 v) 187 c18 vssq i/o power supply (0 v) 188 e19 md4 i specifies area 0 bus width 189 e18 md5 i endian select 190 d18 vccq i/o power supply (3.3 v) 191 c19 vssq i/o power supply (0 v) 192 a20 vccq i/o power supply (3.3 v) 193 b19 vccq-rtc rtc oscillator power supply (3.3 v) 194 b18 xtal2 o on-chip rtc crystal oscillator pin 195 b17 extal2 i on-chip rtc crystal oscillator pin 196 a19 vssq-rtc rtc oscillator power supply (0 v) 197 b16 asemd0 i ase mode 198 c16 tdi i test data input 199 a18 tms i test mode select 200 c17 tdo o test data output 201 a17 trst i test reset 202 d16 tck i test clock 203 b15 asebrkak o ase break acknowledge 204 c15 audsync o aud synchronous 205 a16 audck o aud clock 206 d15 vcc internal power supply (1.5 v) 207 b14 vss internal power supply (0 v)
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 17 of 950 rej09b0079-0200 pin no. ( fp-256g/gv) pin no. (bp-256h/hv ) pin name i/o description 208 c14 vccq i/o power supply (3.3 v) 209 a15 vssq i/o power supply (0 v) 210 d14 audata3 o aud data 211 b13 audata2 o aud data 212 c13 audata1 o aud data 213 a14 audata0 o aud data 214 d13 resetm i manual reset request 215 a13 resetp i power-on reset request 216 c12 nmi i non-maskable interrupt request 217 b12 irq0/ irl0 i external interrupt request 218 d12 irq1/ irl1 i external interrupt request 219 a12 irq2/ irl2 i external interrupt request 220 c11 irq3/ irl3 i external interrupt request 221 b11 vcc internal power supply (1.5 v) 222 d11 vss internal power supply (0 v) 223 a11 status0 o processor status 224 a10 status1 o processor status 225 d10 ckio2 o system clock output 226 a9 dack0 o dma acknowledge 0 227 c10 vccq i/o power supply (3.3 v) 228 b10 vssq i/o power supply (0 v) 229 d9 dack1 o dma acknowledge 1 230 a8 dreq0 i dma request 0 231 c9 dreq1 i dma request 1 232 b9 ptc0/sck_sio1 io/io i/o port c/siof1 communication clock 233 d8 ptc1/siomclk1 io/i i/o port c/siof1 clock input 234 a7 ptc2/rxd_sio1 io/i i/o port c/siof1 receive data 235 c8 vcc internal power supply (1.5 v) 236 b8 vss internal power supply (0 v) 237 d7 ptc3/txd_sio1 io/o i/o port c/siof1 transmit data 238 a6 ptc4/siofsync1 io/io i/o port c/siof1 frame sync
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 18 of 950 rej09b0079-0200 pin no. ( fp-256g/gv) pin no. (bp-256h/hv ) pin name i/o description 239 c7 ptc5/ ce2a io/o i/o port c/area 5 pcmcia card enable 240 a5 ptc6/ ce2b io/o i/o port c/area 6 pcmcia card enable 241 d6 vccq i/o power supply (3.3 v) 242 b7 vssq i/o power supply (0 v) 243 c6 ptc7/ iois16 io/i i/o port c/pcmcia 16-bit i/o select 244 a4 cs5b / ce1a o/o chip select 5b/area 5 pcmcia card enable 245 d5 cs6b / ce1b o/o chip select 6b/area 6 pcmcia card enable 246 b6 vssq i/o power supply (0 v) 247 d4 md0 i clock mode select 248 a3 md1 i clock mode select 249 b4 md2 i clock mode select 250 a2 md3 i area 0 bus width 251 c3 vcc-pll1 pll1 power supply (1.5 v) 252 b5 vss-pll1 pll1 power supply (0 v) 253 c5 vcc-pll2 pll2 power supply (1.5 v) 254 c4 vss-pll2 pll2 power supply (0 v) 255 b3 xtal o clock oscillator pin 256 a1 extal i external clock/crystal oscillator pin notes: 1. vccq-rtc must be supplied even if the realtime clock (rtc) is not used. 2. rtc in this lsi does not operate even if vccq-rtc is turned on. the crystal oscillator circuit for rtc operates with vccq-rtc. the control circuit and the rtc counter operate with vcc (common to the internal circ uit). therefore, all power supplies other than vccq-rtc should always be tur ned on even if only rtc operates. 3. vcc-pll1/vcc-pll2 must be supplied even if the on-chip cpg is not used. 4. vccq (3.3 v), vcc (1.5 v), vssq, and vss must be connected to the system power supply (for uninterrupted supply).
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 19 of 950 rej09b0079-0200 1.3.2 pin functions table 1.2 lists the pin functions. table 1.2 pin functions classification symbol i/o name function vcc ? power supply power supply for the internal lsi and ports for the system. connect all vcc pins to the system power supply. there will be no operation if any pins are open. vss ? ground ground pin. connect all vss pins to the system power supply (0 v). there will be no operation if any pins are open. vccq ? power supply power supply for i/o pins. connect all vccq pins to the system power supply. there will be no operation if any pins are open. power supply vssq ? ground ground pin. connect all vssq pins to the system power supply (0 v). there will be no operation if any pins are open. clock vcc-pll1 i pll1 power supply power supply for the on-chip pll1 oscillator. vss-pll1 i pll1 ground ground pin for the on-chip pll1 oscillator. vcc-pll2 i pll2 power supply power supply for the on-chip pll2 oscillator. vss-pll2 i pll2 ground ground pin for the on-chip pll2 oscillator. extal i external clock for connection to a crystal resonator. this pin can be also used for external clock input. for examples of crystal resonator connection and external clock input, see section 11, on-chip oscillation circuits.
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 20 of 950 rej09b0079-0200 classification symbol i/o name function xtal o crystal for connection to a crystal resonator. for examples of crystal resonator connection and external clock input, see section 11, on- chip oscillation circuits. ckio i/o system clock supplies the system clock to external devices. this pin can be also used for external clock input. clock ckio2 o system clock supplies the system clock to external devices. operating mode control md5 to md0 i mode set these pins set the operating mode. do not change values on these pins during operation. md2 to md0 set the clock mode, md4 and md3 set the bus-width mode of area 0, and md5 sets the endian. resetp i power-on reset when lo w, the system enters the power-on reset state. resetm i manual reset when low, the system enters the manual reset state. status1 status0 o status output indicates that this lsi is in software standby mode, reset, or sleep. breq i bus request low when an external device requests the release of the bus mastership. system control back o bus request acknowledge indicates that the bus mastership has been released to an external device. reception of the back signal informs the device which has output the breq signal that it has acquired the bus mastership.
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 21 of 950 rej09b0079-0200 classification symbol i/o name function nmi i non-maskable interrupt non-maskable interrupt request pin. fix to high when not in use. irq5 to irq0 i interrupt requests 5 to 0 maskable interrupt request pins. selectable as level input or edge input. the rising edge, falling edge, and both edges are selectable as edges. irl3 to irl0 i interrupt request 15-level interrupt request pins. interrupts irqout o interrupt request output indicates that the interrupt request is occurred. address bus a25 to a0 o address bus outputs addresses. data bus d31 to d0 i/o data bus 32-bit bidirectional bus. cs0 , cs2 to cs4 , cs5a , cs6a , cs5b / ce1a , cs6b / ce1b , ce2a , ce2b o chip select 0, 2 to 4, 5a, 5b, 6a, 6b pcmcia card select chip-select signals for external memory or devices. pcmcia card select signal when pcmcia is used. rd o read indicates reading of data from external devices. rd/ wr o read/write read/write signal bs o bus start bus-cycle start signal we3 ( be3 )/ iciowr o byte write indicates that bits 31 to 24 of the data in the external memory or device are being written. i/o write strobe signal when pcmcia is used. we2 ( be2 )/ iciord o byte write indicates that bits 23 to 16 of the data in the external memory or device are being written. i/o read strobe signal when pcmcia is used. bus control we1 ( be1 )/ we o byte write indicates that bits 15 to 8 of the data in the external memory or device are being written. memory write strobe signal when pcmcia is used.
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 22 of 950 rej09b0079-0200 classification symbol i/o name function we0 ( be0 ) o byte write indicates that bits 7 to 0 of the data in the external memory or device are being written. ras o ras connects ras pin during access to the sdram. cas o cas connects cas pin during access to the sdram. cke o ck enable connects cke pin during access to the sdram. iois16 i 16-bit i/o selection indicates 16-bit i/o for pcmcia. dqmuu o dqm selects d31 to d24 during access to the sdram. dqmul o dqm selects d23 to d16 during access to the sdram. dqmlu o dqm selects d15 to d8 during access to the sdram. dqmll o dqm selects d7 to d0 during access to the sdram. refout o refresh request output outputs the refresh request in master mode or bus release. bus control wait i wait inserts a wait cycle into the bus cycles during access to the external space. dreq0, dreq1 i dma-transfer request input pin for external requests for dma transfer. dack0, dack1 o dma-transfer request accept output pin for request acceptance, in response to external requests for dma transfer. direct memory access controller (dmac) tend0, tend1 o dma-transfer end output output pin for dma transfer end signal.
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 23 of 950 rej09b0079-0200 classification symbol i/o name function tck i test clock test-clock input pin. tms i test mode select inputs the test-mode select signal. tdi i test data input serial input pin for instructions and data. tdo o test data output serial output pin for instructions and data. user debugging interface (h-udi) trst i test reset initializing signal input pin. audata3 to audata0 o aud data data output pin in aud trace mode. audck o aud clock synchronous-clock output pin in aud trace mode. advanced user debugger (aud) audsync o aud synchronous signal data start-position acknowledge- signal output pin in aud trace mode. asebrkak o break mode acknowledge indicates that the e10a emulator has entered its break mode. for the connection with the e10a, see the sh7710 e10a emulator user?s manual (tentative title). e10a interface asemd0 i ase mode sets the ase mode. vccq-rtc i rtc oscillator power supply power supply pin for the on-chip rtc vssq-rtc i rtc oscillator ground ground pin for the on-chip rtc extal2 i rtc external clock clock input pin for the on-chip rtc clock (32.768 mhz). for a connection example, refer to section 15, realtime clock (rtc). realtime clock (rtc) xtal2 o rtc crystal clock output pin for the on-chip rtc clock (32.768 mhz). for a connection example, refer to section 15, realtime clock (rtc).
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 24 of 950 rej09b0079-0200 classification symbol i/o name function crs1, crs0 i mac1/0 carrier detection carrier detection pin. for a connection example, refer to section 18, ethernet controller (etherc). col1, col0 i mac1/0 collision detection collision detection pin. for a connection example, refer to section 18, ethernet controller (etherc). etxd13 to etxd10 o mac1 transmit data 4-bit transmit data pins. for a connection example, refer to section 18, ethernet controller (etherc). etxd03 to etxd00 o mac0 transmit data 4-bit transmit data pins. for a connection example, refer to section 18, ethernet controller (etherc). tx-en1, tx-en0 o mac1/0 transmit enable these pins indicate that transmit data is ready on etxd13 to etxd10 and etxd03 to etxd00. for a connection example, refer to section 18, ethernet controller (etherc). tx-clk1, tx-clk0 i mac1/0 transmit clock timing reference pins (clock) for tx-en1/0, tx-er1 /0, etxd13 to etxd10 and etxd03 to etxd00. for a connection example, refer to section 18, ethernet controller (etherc). tx-er1, tx-er0 o mac1/0 transmit error these pins notify an error during transmission to the phy-lsi. for a connection example, refer to section 18, ethernet controller (etherc). ethernet controller (etherc1/0) rx-er1, rx-er0 i mac1/0 receive error these pins notify an error during data reception. for a connection example, refer to section 18, ethernet controller (etherc).
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 25 of 950 rej09b0079-0200 classification symbol i/o name function rx-clk1, rx-clk0 i mac1/0 receive clock timing reference pins (clock) for rx-dv1/0, rx-er1 /0, erxd13 to erxd10 and erxd03 to erxd00. for a connection example, refer to section 18, ethernet controller (etherc). rx-dv1, rx-dv0 i mac1/0 receive data valid these pins indicate that valid receive data is on erxd13 to erxd10 and erxd03 to erxd00. for a connection example, refer to section 18, ethernet controller (etherc). erxd13 to erxd10 i mac1 receive data 4-bit receive data pins. for a connection example, refer to section 18, ethernet controller (etherc). erxd03 to erxd00 i mac0 receive data 4-bit receive data pins. for a connection example, refer to section 18, ethernet controller (etherc). mdc1, mdc0 o mac1/0 management data clock reference clock pins for information transf er via mdio. for a connection example, refer to section 18, ethernet controller (etherc). mdio1, mdio0 i/o mac1/0 management data i/o bidirectional pins for exchanging management information. for a connection example, refer to section 18, ethernet controller (etherc). wol1, wol0 o mac1/0 wake- on-lan these pins indicate that a magic packet has been received. lnksta1, lnksta0 i mac1/0 link status link state input pins from the phy-lsi exout1, exout0 o mac1/0 general-purpose external output external output pins ethernet controller (etherc1/0) camsen1, camsen0 i mac1/0 cam input cam interface pins input
section 1 overview and pin function rev. 2.00 dec. 07, 2005 page 26 of 950 rej09b0079-0200 classification symbol i/o name function ethernet controller (etherc1/0) arbusy o bus release request this pin outputs a bus release request when the amount of data in the receive fifo reaches the threshold. cts1 , cts0 i scif1/0 transmission clear modem control pins rts1 , rts0 o scif1/0 transmit request modem control pins rxd1, rxd0 i scif1/0 receive data receive data pins txd1, txd0 o scif1/0 transmit data transmit data pins serial communication interface with fifo (scif1/0) scif1ck, scif0ck i/o scif1/0 serial clock clock i/o pins sck_sio1, sck_sio0 i/o siof1/0 communication clock transmit/receive communication clock i/o pins siomclk1, siomclk 0 i siof1/0 clock input master-clock input pins rxd_sio1, rxd_sio0 i siof1/0 receive data receive data pins txd_sio1, txd_sio0 o siof1/0 transmit data transmit data pins serial i/o with fifo (siof1/0) siofsync1, siofsync0 i/o siof1/0 frame synchronous signal transmit/receive frame- synchronous-signal i/o pins pta7 to pta0 i/o general purpose i/o port a 8-bit general-purpose i/o port pins ptb7 to ptb0 i/o general purpose i/o port b 8-bit general-purpose i/o port pins i/o port ptc7 to ptc0 i/o general purpose i/o port c 8-bit general-purpose i/o port pins
section 2 cpu cpus3d0s_000020020300 rev. 2.00 dec. 07, 2005 page 27 of 950 rej09b0079-0200 section 2 cpu 2.1 processing states and processing modes 2.1.1 processing states this lsi supports four types of processing states: a reset state, an exception handling state, a program execution state, and a low-power consum ption state, according to the cpu processing states. reset state: in the reset state, the cpu is reset. the lsi supports two types of resets: power-on reset and manual reset. for details on resets, refer to section 4, exception handling. in power-on reset, the registers an d internal statuses of all lsi on -chip modules are initialized. in manual reset, the register conten ts of a part of the lsi on-chip modules, such as the bus state controller (bsc), are retained. for details, refer to section 24, list of regi sters. the cpu internal statuses and registers are initialized both in power- on reset and manual reset. after initialization, the program branches to address h'a0000000 to pass control to the reset processing program to be executed. exception handling state: in the exception handling state, the cpu processing flow is changed temporarily by a general exception or interrupt exception processing. the program counter (pc) and status register (sr) are saved in the save program counter (spc) and save status register (ssr), respectively. the program branches to an ad dress obtained by adding a vector offset to the vector base register (vbr) and passes control to the exception processing program defined by the user to be executed. for details on reset, refer to section 4, exception handling. program execution state: the cpu executes programs sequentially. low-power consumption state: the cpu stops operation to reduce power consumption. the low-power consumption state can be entered by executing the sleep inst ruction. for details on the low-power consumption state, refer to section 10, power-down modes. figure 2.1 shows a status transition diagram.
section 2 cpu rev. 2.00 dec. 07, 2005 page 28 of 950 rej09b0079-0200 2.1.2 processing modes this lsi supports two processing modes: user mode and privileged mode. these processing modes can be determined by the processing mode bit (md) of the status register (sr). if the md bit is cleared to 0, the user mode is selected. if the md bit is set to 1, the privileged mode is selected. the cpu enters the privileged mode by a transition to reset state or exception handling state. in the privileged mode , any registers and resources in address spaces can be accessed. clearing the md bit of the sr to 0 puts the cpu in the user mode. in the user mode, some of the registers, including sr, and so me of the address spaces cannot be accessed by the user program and system control instru ctions cannot be executed. this func tion effectively protects the system resources from the user program. to change the processing mode from user to privileged mode, a transition to exception handling state is required*. note: * to call a service routine used in privileged mode from user mode, the lsi supports an unconditional trap instruction (trapa). when a transition from user mode to privileged mode occurs, the contents of the sr and pc are saved. a program execution in user mode can be resumed by restoring the contents of the sr and pc. to return from an exception processing program, the lsi supports an rte instruction. (from any states) power-on reset manual reset reset state program execution state low-power consumption state exception handling state an exception is accepted exception handling routine starts reset processing routine starts an exception is accepted multiple exceptions sleep instruction figure 2.1 processing state transitions
section 2 cpu rev. 2.00 dec. 07, 2005 page 29 of 950 rej09b0079-0200 2.2 memory map 2.2.1 logical address space the lsi supports 32-bit logical addresses and accesses system reso urces using the 4-gbytes of logical address space. user prog rams and data are accessed from the logical address space. the logical address space is divided into several areas as shown in table 2.1. p0/u0 area: this area is called the p0 area when the cpu is in privileged mode and the u0 area when in user mode. for the p0 and u0 areas, access using the cach e is enabled. the p0 and u0 areas are handled as address translatable areas. if the cache is enabled, access to the p0 or u0 ar ea is cached. if a p0 or u0 address is specified while the address translation unit is enabled, the p0 or u0 address is tran slated into a physical address based on translation information defined by the user. if the cpu is in user mode, only the u0 area can be accessed. if p1, p2, p3, or p4 is accessed in user mode, a transition to an address error exception occurs. p1 area: the p1 area is defined as a cacheable but non-address translatab le area. normally, programs executed at high speed in privileged mode, such as exception processing handlers, which are at the core of the operating syst em (s), are assigned to the p1 area. p2 area: the p2 area is defined as a non-cacheable bu t non-address translatable area. a reset processing program to be called from the reset st ate is described at the start address (h'a0000000) of the p2 area. normally, programs such as system initialization routines and os initiation programs are assigned to the p2 area. to access a part of an on-chip i/o, its corresponding program should be assigned to the p2 area. p3 area: the p3 area is defined as a cacheable and addre ss translatable area. this area is used if an address translation is requir ed for a privileged program. p4 area: the p4 area is defined as a control ar ea which is non-cachea ble and non-address translatable. this area can be acce ssed only in privileged mode. a pa rt of the lsi's on-chip i/o is assigned to this area.
section 2 cpu rev. 2.00 dec. 07, 2005 page 30 of 950 rej09b0079-0200 table 2.1 logical address space address range name mode description h'00000000 to h'7fffffff p0/u0 privileged/user mode 2-gbyte physical space, cacheable, address translatable in user mode, only this address space can be accessed. h'80000000 to h'9fffffff p1 privileged mode 0.5-gbyte physical space, cacheable h'a0000000 to h'bfffffff p2 privileged mode 0.5-gbyte physical space, non-cacheable h'c0000000 to h'dfffffff p3 privileged mode 0.5-gbyte physi cal space, cacheable, address translatable h'e0000000 to h'ffffffff p4 privileged mode 0.5-gbyte control space, non-cacheable 2.2.2 external memory space the lsi uses 29 bits of the 32-bit logical address to access ex ternal memory. in this case, 0.5- gbyte of external memory space can be accessed. the external memory space is managed in area units. different types of memory can be connected to each area, as shown in figure 2.2. for details, please refer to section 12, bus state controller (bsc). in addition, area 1 in the exte rnal memory space is used as an on-chip i/o space where most of this lsi?s on-chip i/os are mapped.* 1 normally, the upper three bits of the 32-bit logical address are masked and the lower 29 bits are used for external memory addresses.* 2 for example, address h'00000100 in the p0 area, address h'80000100 in the p1 area, address h'a0000100 in the p2 area, and address h'c0000100 in the p3 area of the logical address space are mapped into address h?00000100 of area 0 in the external memory space. the p4 area in th e logical address space is not ma pped into the external memory address. if an address in th e p4 area is accessed, an external memory cannot be accessed. notes: 1. to access an on-chip i/o mapped into area 1 in the external memory space, access the address from the p2 area which is not cached in th e logical address space. 2. if the address translation unit is enabled, arbitrary mapping in page units can be specified. for details, refer to section 5, memory management unit (mmu).
section 2 cpu rev. 2.00 dec. 07, 2005 page 31 of 950 rej09b0079-0200 p0 area privileged mode user mode external memory space area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 h'0000 0000 h'0000 0000 h'8000 0000 h'ffff ffff h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 h'ffff ffff u0 area address error p1 area p2 area p3 area p4 area figure 2.2 logical address to external memory space mapping
section 2 cpu rev. 2.00 dec. 07, 2005 page 32 of 950 rej09b0079-0200 2.3 register descriptions this lsi provides thirty-three 32-bit registers: 24 general registers, five control registers, three system registers, and one program counter. general registers: this lsi incorporates 24 general registers: r0_bank0 to r7_bank0, r0_bank1 to r7_bank1 and r8 to r15. r0 to r7 are banked. the process mode and the register bank (rb) bit in the status register (sr) define which set of banked registers (r0_bank0 to r7_bank0 or r0_bank1 to r7_bank1) are accessed as general registers. system registers: this lsi incorporates the multiply and accumulate registers (mach/macl) and procedure register (pr) as sy stem registers. these registers can be accessed regardless of the processing mode. program counter: the program counter stores the value obtained by adding 4 to the current instruction address. control registers: this lsi incorporates the status register (sr), global base register (gbr), save status register (ssr), save program counte r (spc), and vector base register as control register. only the gbr can be accessed in user mo de. control registers other than the gbr can be accessed only in privileged mode. table 2.2 shows the register values after reset. figure 2.3 shows the register configurations in each process mode.
section 2 cpu rev. 2.00 dec. 07, 2005 page 33 of 950 rej09b0079-0200 table 2.2 register initial values register type registers initial values * general registers r0_bank0 to r7_bank0, r0_bank1 to r7_bank1, r8 to r15 undefined system registers mach, macl, pr undefined program counter pc h'a0000000 sr md bit = 1, rb bit = 1, bl bit = 1, i3 to i0 bits = h'f (1111), reserved bits = all 0, other bits = undefined gbr, ssr, spc undefined control registers vbr h'00000000 note: * initialized by a power-on or manual reset.
section 2 cpu rev. 2.00 dec. 07, 2005 page 34 of 950 rej09b0079-0200 31 r0_bank0 * 1, * 2 r1_bank0 * 2 r2_bank0 * 2 r3_bank0 * 2 r4_bank0 * 2 r5_bank0 * 2 r6_bank0 * 2 r7_bank0 * 2 r8 r9 r10 r11 r12 r13 r14 r15 sr gbr mach macl pr pc 031 r0_bank1 * 1, * 3 r1_bank1 * 3 r2_bank1 * 3 r3_bank1 * 3 r4_bank1 * 3 r5_bank1 * 3 r6_bank1 * 3 r7_bank1 * 3 r0_bank0 * 1, * 4 r1_bank0 * 4 r2_bank0 * 4 r3_bank0 * 4 r4_bank0 * 4 r5_bank0 * 4 r6_bank0 * 4 r7_bank0 * 4 r8 r9 r10 r11 r12 r13 r14 r15 sr ssr gbr mach macl vbr pr pc spc 031 r0_bank0 * 1, * 4 r1_bank0 * 4 r2_bank0 * 4 r3_bank0 * 4 r4_bank0 * 4 r5_bank0 * 4 r6_bank0 * 4 r7_bank0 * 4 r0_bank1 * 1, * 3 r1_bank1 * 3 r2_bank1 * 3 r3_bank1 * 3 r4_bank1 * 3 r5_bank1 * 3 r6_bank1 * 3 r7_bank1 * 3 r8 r9 r10 r11 r12 r13 r14 r15 sr ssr gbr mach macl vbr pr pc spc 0 (a) user mode register configuration (b) privileged mode register configuration (rb = 1) (c) privileged mode register configuration (rb = 0) notes: * 1 the r0 register is used as an index register in indexed register indirect addressing mode and indexed gbr indirect addressing mode. * 2 bank register * 3 bank register accessed as a general register when the rb bit is set to 1 in the sr register. accessed only by ldc/stc instructions when the rb bit is cleared to 0. * 4 bank register accessed as a general register when the rb bit is cleared to 0 in the sr register. accessed only by ldc/stc instructions when the rb bit is set to 1. figure 2.3 register configuration in each processing mode
section 2 cpu rev. 2.00 dec. 07, 2005 page 35 of 950 rej09b0079-0200 2.3.1 general registers there are twenty-four 32-bit general registers: r0_bank0 to r7_bank0, r0_bank1 to r7_bank1, and r8 to r15. r0 to r7 are banked. the process mode and the register bank (rb) bit in the status register (sr) define which set of banked registers (r0_bank0 to r7_bank0 or r0_bank1 to r7_bank1) are accessed as general registers. r0 to r7 registers in the selected bank are accessed as r0 to r7. r0 to r7 in the non-selected bank is accessed as r0_bank to r7_bank by the control register load instruction (ldc) and control register store instruction (stc). in user mode, bank 0 is selected regardless of he rb bit value. sixteen registers: r0_bank0 to r7_bank0 and r8 to r15 are accessed as gene ral registers r0 to r15. the r0_bank1 to r7_bank1 registers in bank 1 cannot be accessed. in privileged mode that is entered by a transition to exception handling state, the rb bit is set to 1 to select bank 1. in privileged mode, sixteen registers: r0_bank1 to r7_bank1 and r8 to r15 are accessed as general registers r0 to r15. a bank is switched automatically when an exception handling state is entered, registers r0 to r7 need not be saved by the exception handling routine. the r0_bank0 to r7_bank0 registers in bank 0 can be accessed as r0_bank to r7_bank by the ldc and stc instructions. in privileged mode, bank 0 can also be used as general registers by clearing the rb bit to 0. in this case, sixteen registers: r0_bank0 to r7_bank0 and r8 to r15 are accessed as general registers r0 to r15. the r0 _bank1 to r7_bank1 registers in bank 1 can be accessed as r0_bank to r7_bank by the ldc and stc instructions. the general registers r0 to r15 are used as equivalent registers for almost all instructions. in some instructions, the r0 register is automatically used or only the r0 register can be used as source or destination registers.
section 2 cpu rev. 2.00 dec. 07, 2005 page 36 of 950 rej09b0079-0200 31 r0 * 1, * 2 r1 * 2 r2 * 2 r3 * 2 r4 * 2 r5 * 2 r6 * 2 r7 * 2 r8 r9 r10 r11 r12 r13 r14 r15 0 general registers: undefined after reset notes: * 1 r0 functions as an index register in the indexed register-indirect addressing mode and indexed gbr-indirect addressing mode. in some instructions, only r0 can be used as the source or destination register. * 2 r0?r7 are banked registers. in user mode, bank0 is used. in privileged mode, either r0_bank0 to r7_bank0 or r0_bank1 to r7_bank1 is selected by the rb bit of the sr register. figure 2.4 general registers 2.3.2 system registers the system registers: multiply and accumulate registers (mach/ macl) and procedure register (pr) as system registers can be acce ssed by the lds and sts instructions. multiply and accumulate registers (mach/macl): the multiply and accumulate registers (mach/macl) store the results of multiplication and accumulation instructions or multiplication instructions. the mach/macl registers also store addition values for the multiplication and accumulations. after reset, these registers are u ndefined. the mach and macl registers store upper 32 bits and lower 32 bits, respectively. procedure register (pr): the procedure register (pr) stores the return addres s for a subroutine call using the bsr, bsrf, or jsr instruction. the return address stored in the pr register is restored to the program counter (pc) by the rts (return from the subroutine) instruction. after reset, this register is undefined.
section 2 cpu rev. 2.00 dec. 07, 2005 page 37 of 950 rej09b0079-0200 2.3.3 program counter the program counter (pc) stores the value obtained by adding 4 to the curr ent instruction address. there is no instruction to read the pc directly. before an exception handlin g state is entered, the pc is saved in the save program counter (spc). before a subroutine call is executed, the pc is saved in the procedure register (pr). in addition, the pc can be used for pc relative addressing mode. figure 2.5 shows the system register and program counter configurations. mach macl 31 0 pr 31 0 pc 31 0 multiply and accumulate high and low registers (mach/macl) procedure register (pr) program counter (pc) figure 2.5 system registers and program counter
section 2 cpu rev. 2.00 dec. 07, 2005 page 38 of 950 rej09b0079-0200 2.3.4 control registers the control registers (sr, gbr, ssr, spc, an d vbr) can be accessed by the ldc or stc instruction in privileged mode. the gbr regi ster can be accessed in the user mode. the control registers are described below. status register (sr): the status register (sr) indicates th e system status as shown below. the sr register can be accessed only in privileged mode. bit bit name initial value r/w description 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30 md 1 r/w processing mode indicates the cpu processing mode. 0: user mode 1: privileged mode the md bit is set to 1 in reset or exception handling state. 29 rb 1 r/w register bank the general registers r0 to r7 are banked registers. the rb bit selects a bank used in the privileged mode. 0: selects bank 0 registers. in this case, r0_bank0 to r7_bank0 and r8 to r15 are used as general registers. r0_bank1 to r7_bank1 can be accessed by the ldc or str instruction. 1: selects bank 1 registers. in this case, r0_bank1 to r7_bank1 and r8 to r15 are used as general registers. r0_bank0 to r7_bank0 can be accessed by the ldc or str instruction. the rb bit is set to 1 in reset or exception handling state.
section 2 cpu rev. 2.00 dec. 07, 2005 page 39 of 950 rej09b0079-0200 bit bit name initial value r/w description 28 bl 1 r/w block specifies whether an exception, interrupt, or user break is enabled or not. 0: enables an exception, interrupt, or user break. 1: disables an exception, interrupt, or user break. the bl bit is set to 1 in reset or exception handling state. 27 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 m q ? ? r/w r/w m bit q bit these bits are used by t he div0s, div0u, and div1 instructions. these bits can be changed even in user mode by using the div0s, di v0u, and div1 instructions. these bits are undefined at reset. these bits do not change in an exception handling state. 7 to 4 i3 to i0 all 1 r/w interrupt mask indicates the interrupt mask level. these bits do not change even if an interrupt occurs. at reset, these bits are initialized to b'1111. these bits are not affected in an exception handling state. 3, 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 s ? r/w saturation mode specifies the saturation mode for multiply instructions or multiply and accumulate instructions. this bit can be specified by the sets and clrs instructions in user mode. at reset, this bit is undefined. this bit is not affected in an exception handling state.
section 2 cpu rev. 2.00 dec. 07, 2005 page 40 of 950 rej09b0079-0200 bit bit name initial value r/w description 0 t ? r/w t bit indicates true or false for compare instructions or carry or borrow occurrence for an operation instruction with carry or borrow. this bit can be specified by the sett and clrt instructions in user mode. at reset, this bit is undefined. this bit is not affected in an exception handling state. note: the m, q, s, and t bits can be set/cleared by the user mode specific instructions. other bits can be read or written in privileged mode. save status register (ssr): the save status register (ssr) can be accessed only in privileged mode. before entering the exception, the contents of the sr register is stor ed in the ssr register. at reset, the ssr initial value is undefined. save program counter (spc): the save program counter (spc) can be accessed only in privileged mode. before entering the exception, the contents of the pc is stored in the spc. at reset, the spc initial value is undefined. global base register (gbr): the global base register (gbr) is referenced as a base register in gbr indirect addressing mode. at reset, the gbr initial value is undefined. vector base register (vbr): the global base register (gbr) can be accessed only in privileged mode. if a transition from reset state to exception ha ndling state occurs, this register is referenced as a base address. for details, refer to section 4, exception handling. at reset, the vbr is initialized as h'00000000. figure 2.6 shows the control register configuration.
section 2 cpu rev. 2.00 dec. 07, 2005 page 41 of 950 rej09b0079-0200 31 0 31 spc ssr 0 save status register (ssr) save program counter (spc) 31 0 31 vbr gbr 0 global base register (gbr) vector base register (vbr) 31 0 0 md rb bl 0 status register (sr) t s 0 0 i0 i1 i2 i3 q m 0 figure 2.6 control register configuration
section 2 cpu rev. 2.00 dec. 07, 2005 page 42 of 950 rej09b0079-0200 2.4 data formats 2.4.1 register data format register operands are always longwords (32 bits). when the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 0 longword 2.4.2 memory data formats memory data formats are classi fied into byte, word, and long word. memory can be accessed in byte, word, and longword. when the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. an address error will occur if word data starting from an address other than 2n or longword data starting from an address other th an 4n is accessed. in such cases, the data accessed cannot be guaranteed. when a word or longword operand is accessed, th e byte positions on the me mory corres ponding to the word or longword data on the register is determined to the specified endian mode (big endian or little endian). figure 2.7 shows a byte correspondence in big endian mode. in big endian mode, the msb byte in the register corresponds to the lowest address in the memory, and the lsb the in the register corresponds to the highest address. for example, if the contents of th e general register r0 is stored at an address indicated by the general register r1 in longword, the msb byte of the r0 is stored at the address indicated by the r1 and the lsb byte of the r1 regist er is stored at the address indicated by the (r1 +3). the on-chip device registers assigne d to memory are accessed in big endian mode. note that the available access size (byte, word, or l ong word) differs in each register. note: the cpu instruction codes of this lsi must be stored in word units. in big endian mode, the instruction code must be stored from upper byte to lower byte in this order from the word boundary of the memory.
section 2 cpu rev. 2.00 dec. 07, 2005 page 43 of 950 rej09b0079-0200 31 @(r1+0) @(r1+1) @(r1+2) @(r1+3) @(r1+0) @(r1+1) @(r1+2) @(r1+3) @(r1+0) @(r1+1) @(r1+2) @(r1+3) [7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [15:8] [7:0] [7:0] (a) byte access example: mov.b r0, @r1 (r1 = address 4n) (b) word access example: mov.w r0, @r1 (r1 = address 4n) (c) longword access example: mov.l r0, @r1 (r1 = address 4n) byte position in r0 byte position in memory 23 15 7 0 figure 2.7 data format on memory (big endian mode) the little endian mode can also be specified as da ta format. either big-endian or little-endian mode can be selected according to the external pin (md5) at a po wer-on reset. when md5 is low at reset, the processor operates in big-endian mode. when md 5 is high at reset, the processor operates in little-endian mode. the endian mode cannot be modified dynamically. in little endian mode, the msb byte in the regi ster corresponds to the highest address in the memory, and the lsb the in the register corres ponds to the lowest address (figure 2.8). for example, if the contents of the general register r0 is stored at an address indicated by the general register r1 in longword, the msb byte of the r0 is stored at the address indicated by the (r1+3) and the lsb byte of the r1 register is st ored at the address indicated by the r1. if the little endian mode is selected, the on- chip memory are accessed in little endian mode. however, the on-chip device regi sters assigned to memory are acce ssed in big endian mode. note that the available access size (byte, word, or long word ) differs in each register. note: the cpu instruction codes of this lsi must be stored in word units. in little endian mode, the instruction code must be stored from lower byte to upper byte in this order from the word boundary of the memory. 31 @(r1+3) @(r1+2) @(r1+1) @(r1+0) @(r1+3) @(r1+2) @(r1+1) @(r1+0) @(r1+3) @(r1+2) @(r1+1) @(r1+0) [7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [15:8] [7:0] [7:0] (a) byte access example: mov.b r0, @r1 (r1 = address 4n) (b) word access example: mov.w r0, @r1 (r1 = address 4n) (c) longword access example: mov.l r0, @r1 (r1 = address 4n) byte position in r0 byte position in memory 23 15 7 0 figure 2.8 data format on memory (little endian mode)
section 2 cpu rev. 2.00 dec. 07, 2005 page 44 of 950 rej09b0079-0200 note: when the external memory is accessed through the e-dmac or ipsec module, big endian is supported, but little endian is not supported. therefore, if the external memory is accessed through the e-dmac or ipsec module in little endian mode , data format should be converted from big endian mode to little endian mode through software. 2.5 features of cpu core instructions 2.5.1 instruction execution method instruction length: all instructions have a fixed length of 16 bits and are executed in the sequential pipeline. in the sequential pipeline, almo st all instructions can be executed in one cycle. all data items are handles in longword (32 bits ). memory can be accessed in byte, word, or longword. in this case, memory byte or word data is sign-extended and operated on as longword data. immediate data is sign-extended to longword size for arithmetic operations (mov, add, and cmp/eq instructions) or zero-extended to lo ngword size for logical operations (tst, and, or, and xor instructions). load/store architecture: basic operations are executed be tween registers. in operations involving memory, data is first loaded into a register (load/store architecture). however, bit manipulation instructions such as and are executed dir ectly on memory. delayed branching: unconditional branch instructions are executed as delayed branches. with a delayed branch instruction, the branch is made after execution of the instruction (called the slot instruction) immediately following the delayed branch instruction. this minimizes disruption of the pipeline when a branch is made. this lsi supports two types of conditional branch instructions: delayed branch instruction or normal branch instruction. example: bra target add r1, r0 ; add is executed before branching to the target t bit: the result of a comparison is indicated by th e t bit in the status register (sr), and a conditional branch is performed according to whether the result is true or false. processing speed has been improved by keeping the number of instructions that modify the t bit to a minimum. example: add #1, r0 ; the t bit cannot be modified by the add instruction cmp/eq #0, r0 ; the t bit is set to 1 if r0 is 0. bt target ; branch to target if the t bit is set to 1 (r0=0).
section 2 cpu rev. 2.00 dec. 07, 2005 page 45 of 950 rej09b0079-0200 literal constant: byte literal constant is placed inside th e instruction code as immediate data. since the instruction length is fixed to 16 bits, word and longword literal constant is not placed inside the instruction code, but in a table in me mory. the table in memory is referenced with a mov instruction using pc -relative addressing mode with displacement. example: mov.w @(disp, pc) absolute addresses: when data is referenced by absolute address, the absolute address value is placed in a table in memory beforehand as well as word or longword literal constant. using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is refere nced using register indirect addressing mode. 16-bit/32-bit displacement: when data is referenced with a 16- or 32-bit di splacement, the displacement value is placed in a table in memory beforehand. using the method whereby word or longword immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is referenced using indexed register indirect addressing mode. 2.5.2 cpu instruction addressing modes the following table shows addressing modes and effective address calculation methods for instructions executed by the cpu core. table 2.3 addressing modes and effect ive addresses for cpu instructions addressing mode instruction format effective address calculation method calculation formula register direct rn effective address is register rn. (operand is register rn contents.) ? register indirect @rn effective address is register rn contents. rn rn rn register indirect with post-increment @rn+ effective address is register rn contents. a constant is added to rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn rn 1/2/4 + rn + 1/2/4 rn after instruction execution byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn
section 2 cpu rev. 2.00 dec. 07, 2005 page 46 of 950 rej09b0079-0200 addressing mode instruction format effective address calculation method calculation formula register indirect with pre-decrement @?rn effective address is register rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn rn - 1/2/4 1/2/4 - rn - 1/2/4 byte: rn ? 1 rn word: rn ? 2 rn longword: rn ? 4 rn (instruction executed with rn after calculation) register indirect with displacement @(disp:4, rn) effective address is register rn contents with 4-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. rn rn + disp 1/2/4 1/2/4 + disp (zero-extended) byte: rn + disp word: rn + disp 2 longword: rn + disp 4 indexed register indirect @(r0, rn) effective address is sum of register rn and r0 contents. + rn r0 rn + r0 rn + r0 gbr indirect with displacement @(disp:8, gbr) effective address is register gbr contents with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. gbr gbr + disp 1/2/4 1/2/4 + disp (zero-extended) byte: gbr + disp word: gbr + disp 2 longword: gbr + disp 4
section 2 cpu rev. 2.00 dec. 07, 2005 page 47 of 950 rej09b0079-0200 addressing mode instruction format effective address calculation method calculation formula indexed gbr indirect @(r0, gbr) effective address is sum of register gbr and r0 contents. gbr gbr + r0 r0 + gbr + r0 pc-relative with displacement @(disp:8, pc) effective address is pc with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. with a longword operand, the lower 2 bits of pc are masked. pc pc + disp 2 or pc & h'fffffffc + disp 4 h'fffffffc + & 2/4 disp (zero-extended) * *: with longword operand word: pc + disp 2 longword: pc&h'fffffffc + disp 4 pc-relative disp:8 effective address is pc with 8-bit displacement disp added after being sign- extended and multiplied by 2. pc 2 disp (sign-extended) + pc + disp 2 pc + disp 2 disp:12 effective address is pc with 12-bit displacement disp added after being sign- extended and multiplied by 2 pc 2 disp (sign-extended) + pc + disp 2 pc + disp 2
section 2 cpu rev. 2.00 dec. 07, 2005 page 48 of 950 rej09b0079-0200 addressing mode instruction format effective address calculation method calculation formula pc-relative rn effective address is sum of pc and rn. pc pc + rn rn + pc + rn #imm:8 8-bit immediate data imm of tst, and, or, or xor instruction is zero-extended. ? #imm:8 8-bit immediate data imm of mov, add, or cmp/eq instruction is sign-extended. ? immediate #imm:8 8-bit immediate data imm of trapa instruction is zero-extended and multiplied by 4. ? note: for addressing modes with displacement (dis p) as shown below, the assembler description in this manual indicates the value before it is scaled (x 1, x2, or x4) according to the operand size to clarify the lsi operation. for det ails on assembler description, refer to the description rules in each assembler. @ (disp:4, rn); register indirect with displacement @ (disp:8, gbr); gbr indirect with displacement @ (disp:8, pc); pc relative with displacement disp:8, disp; pc relative 2.5.3 cpu instruction formats table 2.4 shows the instruction formats, and the meaning of the source and destination operands, for instructions executed by the cpu core. the meaning of the operands depends on the instruction code. the following symbols are used in the table. xxxx: instruction code mmmm: source register nnnn: destination register iiii: immediate data dddd: displacement
section 2 cpu rev. 2.00 dec. 07, 2005 page 49 of 950 rej09b0079-0200 table 2.4 cpu instruction formats instruction format source operand destination operand sample instruction 0 type xxxx xxxx xxxx xxxx 15 0 ? ? nop n type xxxx nnnn xxxx xxxx 15 0 ? nnnn: register direct movt rn control register or system register nnnn: register direct sts mach,rn control register or system register nnnn: pre- decrement register indirect stc.l sr,@-rn m type xxxx mmmm xxxx xxxx 15 0 mmmm: register direct control register or system register ldc rm,sr mmmm: post- increment register indirect control register or system register ldc.l @rm+,sr mmmm: register indirect ? jmp @rm pc-relative using rm ? braf rm nm type xxxx nnnn mmmm xxxx 15 0 mmmm: register direct nnnn: register direct add rm,rn mmmm: register indirect nnnn: register indirect mov.l rm,@rn mmmm: post- increment register indirect (multiply- and-accumulate operation) nnnn: * post- increment register indirect (multiply- and-accumulate operation) mach, macl mac.w @rm+,@rn+
section 2 cpu rev. 2.00 dec. 07, 2005 page 50 of 950 rej09b0079-0200 instruction format source operand destination operand sample instruction nm type mmmm: post- increment register indirect nnnn: register direct mov.l @rm+,rn mmmm: register direct nnnn: pre- decrement register indirect mov.l rm,@-rn mmmm: register direct nnnn: indexed register indirect mov.l rm,@(r0,rn) md type xxxx xxxx mmmm dddd 15 0 mmmmdddd: register indirect with displacement r0 (register direct) mov.b @(disp,rm),r0 nd4 type xxxx xxxx nnnn dddd 15 0 r0 (register direct) nnnndddd: register indirect with displacement mov.b r0,@(disp,rn) nmd type xxxx nnnn mmmm dddd 15 0 mmmm: register direct nnnndddd: register indirect with displacement mov.l rm,@(disp,rn) mmmmdddd: register indirect with displacement nnnn: register direct mov.l @(disp,rm),rn d type xxxx xxxx dddd dddd 15 0 dddddddd: gbr indirect with displacement r0 (register direct) mov.l @(disp,gbr),r0 r0 (register direct) dddddddd: gbr indirect with displacement mov.l r0,@(disp,gbr) dddddddd: pc-relative with displacement r0 (register direct) mova @(disp,pc),r0 dddddddd: pc-relative ? bf label d12 type xxxx dddd dddd dddd 15 0 dddddddddddd: pc-relative ? bra label (label=disp+pc) nd8 type xxxx nnnn dddd dddd 15 0 dddddddd: pc- relative with displacement nnnn: register direct mov.l @(disp,pc),rn
section 2 cpu rev. 2.00 dec. 07, 2005 page 51 of 950 rej09b0079-0200 instruction format source operand destination operand sample instruction i type xxxx xxxx i i i i i i i i 15 0 iiiiiiii: immediate indexed gbr indirect and.b #imm,@(r0,gbr) iiiiiiii: immediate r0 (register direct) and #imm,r0 iiiiiiii: immediate ? trapa #imm ni type xxxx nnnn i i i i i i i i 15 0 iiiiiiii: immediate nnnn: register direct add #imm,rn note: * in multiply-and-accumula te instructions, nnnn is the source register.
section 2 cpu rev. 2.00 dec. 07, 2005 page 52 of 950 rej09b0079-0200 2.6 instruction set 2.6.1 cpu instruction set based on functions the cpu instruction set consists of 68 basic instruction types divided into six functional groups, as shown in table 2.5. tables 2.6 to 2.11 show the instru ction notation, machine code, execution time, and function. table 2.5 cpu instruction types type kinds of instruction op code function number of instructions mov data transfer immediate data transfer peripheral module data transfer structure data transfer 39 mova effective address transfer movt t bit transfer swap upper/lower swap data transfer instructions 5 xtrct extraction of middl e of linked registers 21 add binary addition 33 addc binary addition with carry addv binary addition with overflow check cmp/cond comparison div1 division div0s signed division initialization div0u unsigned division initialization dmuls signed double-precision multiplication dmulu unsigned double-precision multiplication dt decrement and test exts sign extension arithmetic operation instructions extu zero extension
section 2 cpu rev. 2.00 dec. 07, 2005 page 53 of 950 rej09b0079-0200 type kinds of instruction op code function number of instructions 21 mac multiply-and-accumulate, double- precision multiply-and-accumulate 33 mul double-precision multiplication (32 32 bits) muls signed multiplication (16 16 bits) mulu unsigned multiplication (16 16 bits) neg sign inversion negc sign inversion with borrow sub binary subtraction subc binary subtraction with carry arithmetic operation instructions subv binary subtraction with underflow 6 and logical and 14 not bit inversion or logical or tas memory test and bit setting tst logical and and t bit setting logic operation instructions xor exclusive logical or 12 rotl 1-bit left shift 16 rotr 1-bit right shift rotcl 1-bit left shift with t bit rotcr 1-bit right shift with t bit shal arithmetic 1-bit left shift shar arithmetic 1-bit right shift shll logical 1-bit left shift shlln logical n-bit left shift shlr logical 1-bit right shift shlrn logical n-bit right shift shad arithmetic dynamic shift shift instructions shld logical dynamic shift
section 2 cpu rev. 2.00 dec. 07, 2005 page 54 of 950 rej09b0079-0200 type kinds of instruction op code function number of instructions 9 bf conditional branch, delayed conditional branch (t = 0) 11 bt conditional branch, delayed conditional branch (t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure branch instructions rts return from subroutine procedure 15 clrt t bit clear 75 clrmac mac register clear clrs s bit clear ldc load into control register lds load into system register ldtlb pteh/ptel load into tlb nop no operation pref data prefetch to cache rte return from exception handling sets s bit setting sett t bit setting sleep transition to power-down mode stc store from control register sts store from system register system control instructions trapa trap exception handling total: 68 188 the instruction code, operation, and number of ex ecution states of the cp u instructions are shown in the following tables, classified by instruction type, using the format shown below.
section 2 cpu rev. 2.00 dec. 07, 2005 page 55 of 950 rej09b0079-0200 instruction instruction code operation privilege execution states t bit indicated by mnemonic. explanation of symbols op.sz src, dest op: operation code sz: size src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement indicated in msb ? lsb order. explanation of symbols mmmm: source register nnnn: destination register 0000: r0 0001: r1 ......... 1111: r15 iiii: immediate data dddd: displacement * 2 indicates summary of operation. explanation of symbols , : transfer direction (xx): memory operand m/q/t: flag bits in sr &: logical and of each bit |: logical or of each bit ^: exclusive logical or of each bit ~: logical not of each bit <>n: n-bit right shift indicates a privileged instruction. value when no wait states are inserted * 1 value of t bit after instruction is executed explanatio n of symbols ?: no change notes: 1. the table shows the minimum number of execution states. in practice, the number of instruction execution states will be incr eased in cases such as the following: a. when there is a conflict between an instruction fetch and a data access b. when the destination register of a load instruction (memory register) is also used by the following instruction 2. scaled (x1, x2, or x4) according to the instruction operand size, etc.
section 2 cpu rev. 2.00 dec. 07, 2005 page 56 of 950 rej09b0079-0200 table 2.6 data transfer instructions instruction instruction code operation privileged mode cycles t bit mov #imm,rn 1110nnnniiiiiiii imm sign extension rn ? 1 ? mov.w @(disp,pc),rn 1001nnnndddddddd (disp x 2+pc) sign extension rn ? 1 ? mov.l @(disp,pc),rn 1101nnnndddddddd (disp x 4+pc) rn ? 1 ? mov rm,rn 0110nnnnmmmm0011 rm rn ? 1 ? mov.b rm,@rn 0010nnnnmmmm0000 rm (rn) ? 1 ? mov.w rm,@rn 0010nnnnmmmm0001 rm (rn) ? 1 ? mov.l rm,@rn 0010nnnnmmmm0010 rm (rn) ? 1 ? mov.b @rm,rn 0110nnnnmmmm0000 (rm) sign extension rn ? 1 ? mov.w @rm,rn 0110nnnnmmmm0001 (rm) sign extension rn ? 1 ? mov.l @rm,rn 0110nnnnmmmm0010 (rm) rn ? 1 ? mov.b rm,@?rn 0010nnnnmmmm0100 rn?1 rn, rm (rn) ? 1 ? mov.w rm,@?rn 0010nnnnmmmm0101 rn?2 rn, rm (rn) ? 1 ? mov.l rm,@?rn 0010nnnnmmmm0110 rn?4 rn, rm (rn) ? 1 ? mov.b @rm+,rn 0110nnnnmmmm0100 (rm) sign extension rn, rm+1 rm ? 1 ? mov.w @rm+,rn 0110nnnnmmmm0101 (rm) sign extension rn, rm+2 rm ? 1 ? mov.l @rm+,rn 0110nnnnmmmm0110 (rm) rn, rm+4 rm ? 1 ? mov.b r0,@(disp,rn) 10000000nnnndddd r0 (disp+rn) ? 1 ? mov.w r0,@(disp,rn) 10000001nnnndddd r0 (disp x 2+rn) ? 1 ? mov.l rm,@(disp,rn) 0001nnnnmmmmdddd rm (disp x 4+rn) ? 1 ? mov.b @(disp,rm),r0 10000100mmmmdddd (disp+rm) sign extension r0 ? 1 ? mov.w @(disp,rm),r0 10000101mmmmdddd (disp x 2+rm) sign extension r0 ? 1 ? mov.l @(disp,rm),rn 0101nnnnmmmmdddd (disp x 4+rm) rn ? 1 ? mov.b rm,@(r0,rn) 0000nnnnmmmm0100 rm (r0+rn) ? 1 ? mov.w rm,@(r0,rn) 0000nnnnmmmm0101 rm (r0+rn) ? 1 ? mov.l rm,@(r0,rn) 0000nnnnmmmm0110 rm (r0+rn) ? 1 ?
section 2 cpu rev. 2.00 dec. 07, 2005 page 57 of 950 rej09b0079-0200 instruction instruction code operation privileged mode cycles t bit mov.b @(r0,rm),rn 0000nnnnmmmm1100 (r0+rm) sign extension rn ? 1 ? mov.w @(r0,rm),rn 0000nnnnmmmm1101 (r0+rm) sign extension rn ? 1 ? mov.l @(r0,rm),rn 0000nnnnmmmm1110 (r0+rm) rn ? 1 ? mov.b r0,@(disp,gbr) 11000000dddddddd r0 (disp+gbr) ? 1 ? mov.w r0,@(disp,gbr) 11000001dddddddd r0 (disp x 2+gbr) ? 1 ? mov.l r0,@(disp,gbr) 11000010dddddddd r0 (disp x 4+gbr) ? 1 ? mov.b @(disp,gbr),r0 11000100dddddddd (disp+gbr) sign extension r0 ? 1 ? mov.w @(disp,gbr),r0 11000101dddddddd (disp x 2+gbr) sign extension r0 ? 1 ? mov.l @(disp,gbr),r0 11000110dddddddd (disp x 4+gbr) r0 ? 1 ? mova @(disp,pc),r0 11000111dddddddd disp x 4+pc r0 ? 1 ? movt rn 0000nnnn00101001 t rn ? 1 ? swap.b rm,rn 0110nnnnmmmm1000 rm swap lowest two bytes rn ? 1 ? swap.w rm,rn 0110nnnnmmmm1001 rm swap two consecutive words rn ? 1 ? xtrct rm,rn 0010nnnnmmmm1101 rm: middle 32 bits of rn rn ? 1 ?
section 2 cpu rev. 2.00 dec. 07, 2005 page 58 of 950 rej09b0079-0200 table 2.7 arithmetic operation instructions instruction instruction code operation privileged mode cycles t bit add rm,rn 0011nnnnmmmm1100 rn+rm rn ? 1 ? add #imm,rn 0111nnnniiiiiiii rn+imm rn ? 1 ? addc rm,rn 0011nnnnmmmm1110 rn+rm+t rn, carry t ? 1 carry addv rm,rn 0011nnnnmmmm1111 rn+rm rn, overflow t ? 1 overflow cmp/eq #imm,r0 10001000iiiiiiii if r0 = imm, 1 t ? 1 compariso n result cmp/eq rm,rn 0011nnnnmmmm0000 if rn = rm, 1 t ? 1 compariso n result cmp/hs rm,rn 0011nnnnmmmm0010 if rn rm with unsigned data, 1 t ? 1 compariso n result cmp/ge rm,rn 0011nnnnmmmm0011 if rn rm with signed data, 1 t ? 1 compariso n result cmp/hi rm,rn 0011nnnnmmmm0110 if rn > rm with unsigned data, 1 t ? 1 compariso n result cmp/gt rm,rn 0011nnnnmmmm0111 if rn > rm with signed data, 1 t ? 1 compariso n result cmp/pl rn 0100nnnn00010101 if rn 0, 1 t ? 1 compariso n result cmp/pz rn 0100nnnn00010001 if rn > 0, 1 t ? 1 compariso n result cmp/str rm,rn 0010nnnnmmmm1100 if rn and rm have an equivalent byte, 1 t ? 1 compariso n result div1 rm,rn 0011nnnnmmmm0100 single-step division (rn/rm) ? 1 calculation result div0s rm,rn 0010nnnnmmmm0111 msb of rn q, msb of rm m, m ^ q t ? 1 calculation result div0u 0000000000011001 0 m/q/t ? 1 0 dmuls.l rm,rn 0011nnnnmmmm1101 signed operation of rn rm mach, macl 32 32 64 bits ? 2 (to 5) * ? dmulu.l rm,rn 0011nnnnmmmm0101 unsigned operation of rn rm mach, macl 32 32 64 bits ? 2 (to 5) * ?
section 2 cpu rev. 2.00 dec. 07, 2005 page 59 of 950 rej09b0079-0200 instruction instruction code operation privileged mode cycles t bit dt rn 0100nnnn00010000 rn ? 1 rn, if rn = 0, 1 t, else 0 t ? 1 comparison result exts.b rm,rn 0110nnnnmmmm1110 a byte in rm is sign-extended rn ? 1 ? exts.w rm,rn 0110nnnnmmmm1111 a word in rm is sign-extended rn ? 1 ? extu.b rm,rn 0110nnnnmmmm1100 a byte in rm is zero-extended rn ? 1 ? extu.w rm,rn 0110nnnnmmmm1101 a word in rm is zero-extended rn ? 1 ? mac.l @rm+, @rn+ 0000nnnnmmmm1111 signed operation of (rn) (rm) + mac mac,rn + 4 rn, rm + 4 rm, 32 32 + 64 64 bits ? 2 (to 5) * ? mac.w @rm+, @rn+ 0100nnnnmmmm1111 signed operation of (rn) (rm) + mac mac,rn + 2 rn, rm + 2 rm, 16 16 + 64 64 bits ? 2 (to 5) * ? mul.l rm,rn 0000nnnnmmmm0111 rn rm macl, 32 32 32 bits ? 2 (to 5) * ? muls.w rm,rn 0010nnnnmmmm1111 signed operation of rn rm macl, 16 16 32 bits ? 1( to 3) * ? mulu.w rm,rn 0010nnnnmmmm1110 unsigned operation of rn rm macl, 16 16 32 bits ? 1(to 3) * ? neg rm,rn 0110nnnnmmmm1011 0?rm rn ? 1 ? negc rm,rn 0110nnnnmmmm1010 0?rm?t rn, borrow t ? 1 borrow sub rm,rn 0011nnnnmmmm1000 rn?rm rn ? 1 ? subc rm,rn 0011nnnnmmmm1010 rn?rm?t rn, borrow t ? 1 borrow subv rm,rn 0011nnnnmmmm1011 rn?rm rn, underflow t ? 1 underflow note: * the number of execut ion cycles indicated within the parentheses ( ) are required when the operation result is read from the ma ch/macl register immediately after the instruction.
section 2 cpu rev. 2.00 dec. 07, 2005 page 60 of 950 rej09b0079-0200 table 2.8 logic operation instructions instruction instruction code operation privileged mode cycles t bit and rm,rn 0010nnnnmmmm1001 rn & rm rn ? 1 ? and #imm,r0 11001001iiiiiiii r0 & imm r0 ? 1 ? and.b #imm,@(r0, gbr) 11001101iiiiiiii (r0+gbr) & imm (r0+gbr) ? 3 ? not rm,rn 0110nnnnmmmm0111 rm rn ? 1 ? or rm,rn 0010nnnnmmmm1011 rn ? rm rn ? 1 ? or #imm,r0 11001011iiiiiiii r0 ? imm r0 ? 1 ? or.b #imm,@(r0, gbr) 11001111iiiiiiii (r0+gbr) ? imm (r0+gbr) ? 3 ? tas.b @rn 0100nnnn00011011 if (rn) is 0, 1 t; 1 msb of (rn) ? 4 test result tst rm,rn 0010nnnnmmmm1000 rn & rm; if the result is 0, 1 t ? 1 test result tst #imm,r0 11001000iiiiiiii r0 & imm; if the result is 0, 1 t ? 1 test result tst.b #imm,@(r0, gbr) 11001100iiiiiiii (r0 + gbr) & imm; if the result is 0, 1 t ? 3 test result xor rm,rn 0010nnnnmmmm1010 rn ^ rm rn ? 1 ? xor #imm,r0 11001010iiiiiiii r0 ^ imm r0 ? 1 ? xor.b #imm,@(r0, gbr) 11001110iiiiiiii (r0+gbr) ^ imm (r0+gbr) ? 3 ?
section 2 cpu rev. 2.00 dec. 07, 2005 page 61 of 950 rej09b0079-0200 table 2.9 shift instructions instruction instruction code operation privileged mode cycles t bit rotl rn 0100nnnn00000100 t rn msb ? 1 msb rotr rn 0100nnnn00000101 lsb rn t ? 1 lsb rotcl rn 0100nnnn00100100 t rn t ? 1 msb rotcr rn 0100nnnn00100101 t rn t ? 1 lsb shad rm, rn 0100nnnnmmmm1100 rm 0: rn << rm rn rm < 0: rn >> rm [msb rn] ? 1 ? shal rn 0100nnnn00100000 t rn 0 ? 1 msb shar rn 0100nnnn00100001 msb rn t ? 1 lsb shld rm, rn 0100nnnnmmmm1101 rm 0: rn << rm rn rm < 0: rn >> rm [0 rn] ? 1 ? shll rn 0100nnnn00000000 t rn 0 ? 1 msb shlr rn 0100nnnn00000001 0 rn t ? 1 lsb shll2 rn 0100nnnn00001000 rn<<2 rn ? 1 ? shlr2 rn 0100nnnn00001001 rn>>2 rn ? 1 ? shll8 rn 0100nnnn00011000 rn<<8 rn ? 1 ? shlr8 rn 0100nnnn00011001 rn>>8 rn ? 1 ? shll16 rn 0100nnnn00101000 rn<<16 rn ? 1 ? shlr16 rn 0100nnnn00101001 rn>>16 rn ? 1 ?
section 2 cpu rev. 2.00 dec. 07, 2005 page 62 of 950 rej09b0079-0200 table 2.10 branch instructions instruction instruction code operation privileged mode cycles t bit bf label 10001011dddddddd if t = 0, disp 2 + pc pc; if t = 1, nop ? 3/1 * ? bf/s label 10001111dddddddd delayed branch, if t = 0, disp 2 + pc pc; if t = 1, nop ? 2/1 * ? bt label 10001001dddddddd if t = 1, disp 2 + pc pc; if t = 0, nop ? 3/1 * ? bt/s label 10001101dddddddd delayed branch, if t = 1, disp 2 + pc pc; if t = 0, nop ? 2/1 * ? bra label 1010dddddddddddd delayed branch, disp 2 + pc pc ? 2 ? braf rm 0000mmmm00100011 delayed branch,rm + pc pc ? 2 ? bsr label 1011dddddddddddd delayed branch, pc pr, disp 2 + pc pc ? 2 ? bsrf rm 0000mmmm00000011 delayed branch, pc pr, rm + pc pc ? 2 ? jmp @rm 0100mmmm00101011 delayed branch, rm pc ? 2 ? jsr @rm 0100mmmm00001011 delayed branch, pc pr, rm pc ? 2 ? rts 0000000000001011 delayed branch, pr pc ? 2 ? note: * one state when the br anch is not executed.
section 2 cpu rev. 2.00 dec. 07, 2005 page 63 of 950 rej09b0079-0200 table 2.11 system control instructions instruction instruction code operation privileged mode cycles t bit clrmac 0000000000101000 0 mach,macl ? 1 ? clrs 0000000001001000 0 s ? 1 ? clrt 0000000000001000 0 t ? 1 0 ldc rm,sr 0100mmmm00001110 rm sr 6 lsb ldc rm,gbr 0100mmmm00011110 rm gbr ? 4 ? ldc rm,vbr 0100mmmm00101110 rm vbr 4 ? ldc rm,ssr 0100mmmm00111110 rm ssr 4 ? ldc rm,spc 0100mmmm01001110 rm spc 4 ? ldc rm,r0_bank 0100mmmm10001110 rm r0_bank 4 ? ldc rm,r1_bank 0100mmmm10011110 rm r1_bank 4 ? ldc rm,r2_bank 0100mmmm10101110 rm r2_bank 4 ? ldc rm,r3_bank 0100mmmm10111110 rm r3_bank 4 ? ldc rm,r4_bank 0100mmmm11001110 rm r4_bank 4 ? ldc rm,r5_bank 0100mmmm11011110 rm r5_bank 4 ? ldc rm,r6_bank 0100mmmm11101110 rm r6_bank 4 ? ldc rm,r7_bank 0100mmmm11111110 rm r7_bank 4 ? ldc.l @rm+,sr 0100mmmm00000111 (rm) sr, rm+4 rm 8 lsb ldc.l @rm+,gbr 0100mmmm00010111 (rm) gbr, rm+4 rm ? 4 ? ldc.l @rm+,vbr 0100mmmm00100111 (rm) vbr, rm+4 rm 4 ? ldc.l @rm+,ssr 0100mmmm00110111 (rm) ssr,rm+4 rm 4 ? ldc.l @rm+,spc 0100mmmm01000111 (rm) spc,rm+4 rm 4 ? ldc.l @rm+, r0_bank 0100mmmm10000111 (rm) r0_bank,rm+4 rm 4 ? ldc.l @rm+, r1_bank 0100mmmm10010111 (rm) r1_bank,rm+4 rm 4 ? ldc.l @rm+, r2_bank 0100mmmm10100111 (rm) r2_bank,rm+4 rm 4 ? ldc.l @rm+, r3_bank 0100mmmm10110111 (rm) r3_bank, rm+4 rm 4 ?
section 2 cpu rev. 2.00 dec. 07, 2005 page 64 of 950 rej09b0079-0200 instruction instruction code operation privileged mode cycles t bit ldc.l @rm+, r4_bank 0100mmmm11000111 (rm) r4_bank, rm+4 rm 4 ? ldc.l @rm+, r5_bank 0100mmmm11010111 (rm) r5_bank, rm+4 rm 4 ? ldc.l @rm+, r6_bank 0100mmmm11100111 (rm) r6_bank, rm+4 rm 4 ? ldc.l @rm+, r7_bank 0100mmmm11110111 (rm) r7_bank, rm+4 rm 4 ? lds rm,mach 0100mmmm00001010 rm mach ? 1 ? lds rm,macl 0100mmmm00011010 rm macl ? 1 ? lds rm,pr 0100mmmm00101010 rm pr ? 1 ? lds.l @rm+,mach 0100mmmm00000110 (rm) mach, rm+4 rm ? 1 ? lds.l @rm+,macl 0100mmmm00010110 (rm) macl, rm+4 rm ? 1 ? lds.l @rm+,pr 0100mmmm00100110 (rm) pr, rm+4 rm ? 1 ? ldtlb 0000000000111000 pteh/ptel tlb 1 ? nop 0000000000001001 no operation ? 1 ? pref @rm 0000mmmm10000011 (rm) cache ? 1 ? rte 0000000000101011 delayed branch, ssr sr, spc pc 5 ? sets 0000000001011000 1 s ? 1 ? sett 0000000000011000 1 t ? 1 1 sleep 0000000000011011 sleep 4 * 1 ? stc sr,rn 0000nnnn00000010 sr rn 1 ? stc gbr,rn 0000nnnn00010010 gbr rn ? 1 ? stc vbr,rn 0000nnnn00100010 vbr rn 1 ? stc ssr, rn 0000nnnn00110010 ssr rn 1 ? stc spc,rn 0000nnnn01000010 spc rn 1 ? stc r0_bank,rn 0000nnnn10000010 r0_bank rn 1 ? stc r1_bank,rn 0000nnnn10010010 r1_bank rn 1 ? stc r2_bank,rn 0000nnnn10100010 r2_bank rn 1 ? stc r3_bank,rn 0000nnnn10110010 r3_bank rn 1 ? stc r4_bank,rn 0000nnnn11000010 r4_bank rn 1 ?
section 2 cpu rev. 2.00 dec. 07, 2005 page 65 of 950 rej09b0079-0200 instruction instruction code operation privileged mode cycles t bit stc r5_bank,rn 0000nnnn11010010 r5_bank rn 1 ? stc r6_bank,rn 0000nnnn11100010 r6_bank rn 1 ? stc r7_bank,rn 0000nnnn11110010 r7_bank rn 1 ? stc.l sr,@?rn 0100nnnn00000011 rn?4 rn, sr (rn) 1 ? stc.l gbr,@?rn 0100nnnn00010011 rn?4 rn, gbr (rn) ? 1 ? stc.l vbr,@?rn 0100nnnn00100011 rn?4 rn, vbr (rn) 1 ? stc.l ssr,@?rn 0100nnnn00110011 rn?4 rn, ssr (rn) 1 ? stc.l spc,@?rn 0100nnnn01000011 rn?4 rn, spc (rn) 1 ? stc.l r0_bank,@? rn 0100nnnn10000011 rn?4 rn, r0_bank (rn) 1 ? stc.l r1_bank,@? rn 0100nnnn10010011 rn?4 rn, r1_bank (rn) 1 ? stc.l r2_bank,@? rn 0100nnnn10100011 rn?4 rn, r2_bank (rn) 1 ? stc.l r3_bank,@? rn 0100nnnn10110011 rn?4 rn, r3_bank (rn) 1 ? stc.l r4_bank,@? rn 0100nnnn11000011 rn?4 rn, r4_bank (rn) 1 ? stc.l r5_bank,@? rn 0100nnnn11010011 rn?4 rn, r5_bank (rn) 1 ? stc.l r6_bank,@? rn 0100nnnn11100011 rn?4 rn, r6_bank (rn) 1 ? stc.l r7_bank,@? rn 0100nnnn11110011 rn?4 rn, r7_bank (rn) 1 ? sts mach,rn 0000nnnn00001010 mach rn ? 1 ? sts macl,rn 0000nnnn00011010 macl rn ? 1 ? sts pr,rn 0000nnnn00101010 pr rn ? 1 ? sts.l mach,@?rn 0100nnnn00000010 rn?4 rn, mach (rn) ? 1 ? sts.l macl,@?rn 0100nnnn00010010 rn?4 rn, macl (rn) ? 1 ? sts.l pr,@?rn 0100nnnn00100010 rn?4 rn, pr (rn) ? 1 ? trapa #imm 11000011iiiiiiii unconditional trap exception occurs * 2 ? 8 ? notes: 1. number of states before the chip enters the sleep state. 2. for details, refer to section 4, exception handling.
section 2 cpu rev. 2.00 dec. 07, 2005 page 66 of 950 rej09b0079-0200 2.6.2 operation code map table 2.12 shows the operation code map. table 2.12 operation code map instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0000 rn fx 0000 0000 rn fx 0001 0000 rn 00md 0010 stc sr, rn stc gbr, rn stc vbr, rn stc ssr, rn 0000 rn 01md 0010 stc spc, rn 0000 rn 10md 0010 stc r0_bank, rn stc r1_bank, rn stc r2_bank, rn stc r3_bank, rn 0000 rn 11md 0010 stc r4_bank, rn stc r5_bank, rn stc r6_bank, rn stc r7_bank, rn 0000 rm 00md 0011 bsrf rm braf rm 0000 rm 10md 0011 pref @rm 0000 rn rm 01md mov.b rm, @(r0, rn) mov.w rm, @(r0, rn) mov.l rm, @(r0, rn) mul.l rm, rn 0000 0000 00md 1000 clrt sett clrmac ldtlb 0000 0000 01md 1000 clrs sets 0000 0000 fx 1001 nop div0u 0000 0000 fx 1010 0000 0000 fx 1011 rts sleep rte 0000 rn fx 1000 0000 rn fx 1001 movt rn 0000 rn fx 1010 sts mach, rn sts macl, rn sts pr, rn 0000 rn fx 1011 0000 rn rm 11md mov. b @(r0, rm), rn mov.w @(r0, rm), rn mov.l @(r0, rm), rn mac.l @rm+,@rn+ 0001 rn rm disp mov.l rm, @(disp:4, rn) 0010 rn rm 00md mov.b rm, @rn mov.w rm, @rn mov.l rm, @rn
section 2 cpu rev. 2.00 dec. 07, 2005 page 67 of 950 rej09b0079-0200 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0010 rn rm 01md mov.b rm, @? rn 0010 rn rm 10md tst rm, rn 0010 rn rm 11md cmp/strrm, rn 0011 rn rm 00md cmp/eq rm, rn cmp/hs rm, rn cmp/ge rm, rn 0011 rn rm 01md div1 rm, rn dmulu.l rm,rn cmp/hi rm, rn cmp/gt rm, rn 0011 rn rm 10md sub rm, rn subc rm, rn subv rm, rn 0011 rn rm 11md add rm, rn dmuls.l rm,rn addc rm, rn addv rm, rn 0100 rn fx 0000 shll rn dt rn shal rn 0100 rn fx 0001 shlr rn cmp/pz rn shar rn 0100 rn fx 0010 sts.l mach, @? rn sts.l macl, @? rn sts.l pr, @?rn 0100 rn 00md 0011 stc.l sr, @?rn stc.l gbr, @?rn stc.l vbr, @? rn stc.l ssr, @? rn 0100 rn 01md 0011 stc.l spc, @?rn 0100 rn 10md 0011 stc.l r0_bank, @?rn stc.l r1_bank, @?rn stc.l r2_bank, @?rn stc.l r3_bank, @?rn 0100 rn 11md 0011 stc.l r4_bank, @?rn stc.l r5_bank, @?rn stc.l r6_bank, @?rn stc.l r7_bank, @?rn 0100 rn fx 0100 rotl rn rotcl rn 0100 rn fx 0101 rotr rn cmp/pl rn rotcr rn 0100 rm fx 0110 lds.l @rm+, mach lds.l @rm+, macl lds.l @rm+, pr 0100 rm 00md 0111 ldc.l @rm+, sr ldc.l @rm+, gbr ldc.l @rm+, vbr ldc.l @rm+, ssr 0100 rm 01md 0111 ldc.l @rm+, spc 0100 rm 10md 0111 ldc.l @rm+, r0_bank ldc.l @rm+, r1_bank ldc.l @rm+, r2_bank ldc.l @rm+, r3_bank 0100 rm 11md 0111 ldc.l @rm+, r4_bank ldc.l @rm+, r5_bank ldc.l @rm+, r6_bank ldc.l @rm+, r7_bank 0100 rn fx 1000 shll2 rn shll8 rn shll16 rn
section 2 cpu rev. 2.00 dec. 07, 2005 page 68 of 950 rej09b0079-0200 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0100 rn fx 1001 shlr2 rn 0100 rm fx 1010 lds rm, mach 0100 rm/rn fx 1011 jsr @rm 0100 rn rm 1100 shad rm, rn 0100 rn rm 1101 shld rm, rn 0100 rm 00md 1110 ldc rm, sr ldc rm, gbr ldc rm, vbr ldc rm, ssr 0100 rm 01md 1110 ldc rm, spc 0100 rm 10md 1110 ldc rm, r0_bank ldc rm, r1_bank ldc rm, r2_bank ldc rm, r3_bank 0100 rm 11md 1110 ldc rm, r4_bank ldc rm, r5_bank ldc rm, r6_bank ldc rm, r7_bank 0100 rn rm 1111 mac.w @rm+, @rn+ 0101 rn rm disp mov.l @ (disp:4, rm), rn 0110 rn rm 00md mov.b @rm, rn mov.w @rm, rn mov.l @rm, rn mov rm, rn 0110 rn rm 01md mov.b @rm+, rn mov.w @rm+, rn mov.l @rm+, rn not rm, rn 0110 rn rm 10md swap.b rm, rn swap.wrm, rn negc rm, rn neg rm, rn 0110 rn rm 11md extu.b rm, rn extu.w rm, rn exts.b rm, rn exts.w rm, rn 0111 rn imm add # imm : 8, rn 1000 00md rn disp mov. b r0, @(disp: 4, rn) mov. w r0, @(disp: 4, rn) 1000 01md rm disp mov.b @(disp:4, rm), r0 mov.w @(disp: 4, rm), r0 1000 10md imm/disp cmp/eq #imm:8, r0 bt disp: 8 bf disp: 8 1000 11md imm/disp bt/s disp: 8 bf/s disp: 8 1001 rn disp mov.w @ (disp : 8, pc), rn 1010 disp bra disp: 12 1011 disp bsr disp: 12
section 2 cpu rev. 2.00 dec. 07, 2005 page 69 of 950 rej09b0079-0200 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 1100 00md imm/disp mov.b r0, @(disp: 8, gbr) mov.w r0, @(disp: 8, gbr) mov.l r0, @(disp: 8, gbr) trapa #imm: 8 1100 01md disp mov.b @(disp: 8, gbr), r0 mov.w @(disp: 8, gbr), r0 mov.l @(disp: 8, gbr), r0 mova @(disp: 8, pc), r0 1100 10md imm tst #imm: 8, r0 and #imm: 8, r0 xor #imm: 8, r0 or #imm: 8, r0 1100 11md imm tst.b #imm: 8, @(r0, gbr) and.b #imm: 8, @(r0, gbr) xor.b #imm: 8, @(r0, gbr) or.b #imm: 8, @(r0, gbr) 1101 rn disp mov.l @(disp: 8, pc), rn 1110 rn imm mov #imm:8, rn 1111 ************ note: for details, refer to the sh -3/sh-3e/sh3-dsp programming manual.
section 2 cpu rev. 2.00 dec. 07, 2005 page 70 of 950 rej09b0079-0200
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 71 of 950 rej09b0079-0200 section 3 dsp operating unit 3.1 dsp extended functions this lsi incorporates a dsp unit and x/y memory directly connected to the dsp unit. this lsi supports the dsp extended function instruction sets needed to control the dsp unit and x/y memory. the dsp extended function instructions are divided into four groups. extended system control in structions for the cpu: if the dsp extended function is enabled, the following extended system control instructions can be used for the cpu. ? repeat loop control instructions and repeat loop control regist er access instructions are added. looped programs can be executed efficiently by using the zero-overhead repeat control unit. for details, refer to section 3.3, cpu extended instructions. ? modulo addressing control inst ructions and control register access instructions are added. function allows access to data with a circular st ructure. for details, refer to section 3.4, dsp data transfer instructions. ? dsp unit register access instructions are added. so me of the dsp unit registers can be used in the same way as the cpu system registers. for de tails, refer to section 3.4, dsp data transfer instructions. data transfer instructions for data transfers between ds p unit registers and on-chip x/y memory: data transfer instructions for data transf ers between the dsp unit registers and on- chip x/y memory are called double -data transfer instructions. inst ruction codes for these double- transfer instructions are 16 bit codes as well as cpu instruction codes. these data transfer instructions perform data transfers between the dsp unit and on-chip x/y memory that is directly connected to the dsp unit. these da ta transfer instructions can be described in combination with other dsp unit operation instructions. for details , refer to section 3.4, dsp data transfer instructions. data transfer instructions fo r data transfers between dsp un it registers and all logical address spaces: data transfer instructions for data tran sfers between dsp unit registers and all logical address spaces are called single-data transfer instructions. instructio n codes for the double- transfer instructions are 16 bit codes as well as cpu instruction codes. these data transfer instructions performs data transfers between the dsp unit registers and all logical address spaces. for details, refer to section 3.4, dsp data transfer instructions. dsp unit operation instructions: dsp unit operation instructions are called dsp data operation instructions. these instructions are provided to execute digital signal processing operations at high speed using the dsp. instruction codes for these instructions are 32 bits. the dsp data operation
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 72 of 950 rej09b0079-0200 instruction fields consist of two fields: field a and field b. in field a, a function for double data transfer instructions can be descried. in fi eld b, alu operation instructions and multiply instructions can be described. the instructions described in fields a and b can be executed in parallel. a maximum of four instructions (alu operation, multiply, and two data transfers) can be executed in parallel. for details, refer to s ection 3.5, dsp data operation instructions. notes: 1. 32-bit instruction codes are handled as two consecutive 16-bit instruction codes. accordingly, 32-bit instruction codes can be assigned to a word boundary. 32-bit instruction codes must be stored in memory, upper word and lower word, in this order, in word units. 2. in little endian, the upper and lower words must be stored in memory as data to be accessed in word units. cpu core instruction 15 0000 1110 111100 111101 111110 a field a field a field b field 0 15 0 15 10 10 9 12 11 90 31 16 26 25 0 15 double-data transfer instruction single-data transfer instruction dsp data operation instruction - * figure 3.1 dsp instruction format
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 73 of 950 rej09b0079-0200 3.2 dsp mode resources 3.2.1 processing modes the cpu processing modes can be extended using the mode bit (md) and dsp bit (dsp) of the status register (sr), as shown below. description md dsp processing mode access of resources protected in privileged mode or privileged instruction execution dsp extended functions 0 0 user mode prohibited invalid 0 1 user dsp mode prohibited valid 1 0 privileged mode allowed invalid 1 1 privileged dsp mode allowed valid as shown above, the extension of the dsp function by the dsp bit can be specified independently of the control by the md bit. note, however, that the dsp bit can be modified only in privileged mode. before the dsp bit is modified, a transition to privileged mode or privileged dsp mode is necessary. 3.2.2 dsp mode memory map in dsp mode, a part of the p2 area in the logical address space can be accessed in user dsp mode. when this area is accessed in user dsp mode, this area is referred to as a uxy area. x/y memory is then assigned to this uxy area. accordingly, x/y memory can also be accessed in user dsp mode. table 3.1 logical address space address range name protection description h'a5000000 to h'a5ffffff p2/uxy privileged or dsp 16-mbyte physical address space, non- cacheable, non-address translatable can be accessed in privileged mode, privileged dsp mode, and user dsp mode
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 74 of 950 rej09b0079-0200 3.2.3 cpu register sets in dsp mode, the status register (sr) in the cpu unit is extended to add control bits and three control registers: a repeat start register (sr), repeat end register (re), and module register are added as control registers. 31 31 31 31 16 15 0 0 0 30292827 161514131211109876543210 0 md rb bl rc[11:0] 0 0 0 dsp dmy dmx m q i3 i2 i1 i0 rf1 rf0 s t me ms rs re repeat start register (rs) status register (sr) repeat end register (re) modulo register (mod) figure 3.2 cpu registers in dsp mode extension of status register (sr): in dsp mode, the following control bits are added to the status register (sr). these added bits are called dsp extension bits. these dsp extension bits are valid only in dsp mode. bit bit name initial value r/w description 31 to 28 for details, refer to section 2, cpu. 27 to 16 rc11 to rc0 all 0 r/w repeat counter holds the number of repeat times in order to perform loop control, and can be modified in privileged mode, privileged dsp mode, or user dsp mode. at reset, this bit is initialized to 0. this bit is not affected in the exception handling state. 15 to 13 for details, refer to section 2, cpu. 12 dsp 0 r/w dsp bit enables or disables the dsp extended functions. if this bit is set to 1, the dsp extended functions are enabled. this bit can be modified in privileged mode or privileged dsp mode. this bit cannot be modified in user dsp mode. at reset, this bit is initialized to 0. this bit is not affected in the exception handling state.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 75 of 950 rej09b0079-0200 bit bit name initial value r/w description 11 10 dmy dmx 0 0 r/w r/w modulo control bits enable or disable modulo addressing for x/y memory access. these bits can be modified in privileged mode, privileged dsp mode, or user dsp mode. at reset, these bits are initialized to 0. thes e bits are not affected in the exception handling state. 9 to 4 ? ? ? for details, refer to section 2, cpu. 3 2 fr1 fr0 0 0 r/w r/w repeat flag bits used by repeat control instructions. these bits can be modified in privileged mode, privileged dsp mode, or user dsp mode. at reset, these bits are initialized to 0. these bits are not affected in t he exception handling state. 1 to 0 ? ? ? for details, refer to section 2, cpu. note: when data is written to the sr register, 0 sh ould be written to bits t hat are specified as 0. repeat start register (rs): the repeat start register (rs) holds the start address of a loop repeat module that is controlled by th e repeat function. this register can be accessed in dsp mode. at reset, the initial value of this register is undefine d. this register is not affected in the exception handling state. repeat end register (re): the repeat end register (re) holds the end address of a loop repeat module that is controlled by the repeat function. this register can be accessed in dsp mode. at reset, this register is initialized to 0. this regist er is not affected in the exception handling state. modulo register (mod): the modulo register stores the modulo end address and modulo start address for modulo addressing in upper and lower 16 bits. the upper and lower 16 bits of the modulo register are referred to as the me register and ms register , respectively. this register can be accessed in dsp mode. at reset, the initial value of this register is undefined. this register is not affected in the exception handling state. the above registers can be accessed by the control register load instruction (ldc) and store instruction (stc). note that the ldc and stc instructions for the rs, re, and mod registers can be used only in privileged dsp mode and user dsp mode. the ldc and stc instruction for the sr register can be executed only when the md bit is set to 1 or in user dsp mode. note, however, that the ldc and stc instructions can modify only the rc11 to rc0, rf1 to rf0, dmx, and dmy bits in the sr, as described below. ?
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 76 of 950 rej09b0079-0200 ? in privileged and privileged dsp modes, all sr bits can be modified. ? in user dsp mode, the sr can be read by the stc instruction. ? in user dsp mode, the ldc instruction can be issued to the sr but only the dsp extension bits can be modified. table 3.2 operation of sr bits in each processing mode privileged mode user mode privileged dsp mode user dsp mode field md = 1 & dsp = 0 md = 0 & dsp = 0 md = 1 & dsp = 1 md = 0 & dsp = 1 access to dsp-related bit with dedicated instruction initial value after reset md s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng 1 rb s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng 1 bl s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng 1 rc [11:0] s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ok setrc instruction 000000000000 dsp s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng 0 dmy s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ok 0 dmx s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ok 0 q s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng x m s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng x i[3:0] s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng 1111 rf[1:0] s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ok setrc instruction x s s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng x t s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng x [legend] s: stc instruction l: ldc instruction ok: stc/ldc operation is enabled. invalid instruction: exception occurs w hen an invalid instruction is executed. ng: previous value is retained. no change. x: undefined
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 77 of 950 rej09b0079-0200 before entering the exception handling state, all bits including the dsp extension bits of the sr registers are saved in the ssr. before returning from the exception handling, all bits including the dsp extension bits of the sr must be restored. if the repeat control must be recovered before entering the exception hand ling state, the rs and re registers mu st be recovered to the value that existed before exception handling. in addition, if it is necessary to recover modulo control before entering the exception handling st ate, the mod register must be recovered to the value that existed before exception handling. 3.2.4 dsp registers the dsp unit incorporates eight data registers (a 0, a1, x0, x1, y0, y1, m0 , and m1) and a status register (dsr). figure 3.3 shows the dsp register configuration. these are 32-bit width registers with the exception of registers a0 and a1. registers a0 and a1 include 8 guard bits (fields a0g and a1g), giving them a total width of 40 bits. the dsr register stores the dsp data operation result (zero, negative, others). the dsp register has a dc bit whose function is similar to the t bit of the cpu register. for details on dsr bits, refer to section 3.5, dsp data operation instructions. 39 a0g a1g a0 a1 m0 m1 x0 x1 y0 y1 .................................................... ts[2:0] tc gt v n z cs[2:0] dc (a) dsp data registers (b) dsp status register (dsr) 32 31 0 31 12 11 9 8 7 6 5 4 3 1 0 initial value dsr : all 0 others: undefined figure 3.3 dsp register configuration
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 78 of 950 rej09b0079-0200 3.3 cpu extended instructions 3.3.1 repeat control instructions in dsp mode, a specific function is provided to ex ecute repeat loops effici ently. by using this function, loop programs can be executed without overhead caused by the compare and branch instructions. examples of repeat loop programs: examples of repeat loop programs are shown below. ? example 1: repeat loop consisting of 4 or more instructions ldrs rptstart ; sets repeat start instruction address to the rs register ldre rptstart +4 ; sets (repeat detection instruction address + 4) to the re register setrc #4 ; sets the number of repetitions (4) to the rc[11:0] bits of the sr register instr0 ; at least one instruction is required from setrc instruction to [repeat start instruction] rptstart: instr1 ; [repeat start instruction] ... ... ; ... ... ; rptdtct: instr(n-3) ; three instruction prior to the repeat end instruction is regarded as repeat detection instruction rptend2: instr(n-2) ; rptend1: instr(n-1) ; rptend: instrn ; [repeat end instruction] in the above program example, instructions from the rptstart address (instr1 instruction) to the rptend address (instrn instructi on) are repeated four times. thes e repeated instructions in the program are called repeat loop. the start and end instructions of the repeat loop are called the repeat start instruction and repeat end instruct ion, respectively. the cpu sequentially executes instructions and starts repeat loop control if the cpu detects the completion of a specific instruction. this specific instruction is called the repeat detection instruction. in a repeat loop consisting of 4 or more instructions, an instruction three instructions prior to the repeat end instruction is regarded as the repeat detection inst ruction. in a repeat loop consisting of 4 or more instructions, the same instruction is regarded as the rptstart instruction and rptdtct instruction.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 79 of 950 rej09b0079-0200 to control the repeat loop, the dsp extended cont rol registers, such as the re register and rs register and the rc[11:0] and rf[1:0] bits of th e sr register, are used. these registers can be specified by the ldre, ldrs, and setrc instructions. ? repeat end register (re) the re register is specified by the ldre in struction. the re register specifies (repeat detection instruction address +4). in a repeat loop consisting of 4 or more instructions, an instruction three instructions prior to the repeat end instruction is regarded as the repeat detection instruction. a repeat loop consisting of three or less instructions is described later. ? repeat start register (rs) the rs register is specified by the ldrs instruction. in a repeat loop consisting of 4 or more instructions, the rs register sp ecifies the repeat start instruct ion address. in a repeat loop consisting of three or less instructions, a specif ic address is specified in the rs. this is described later. ? repeat counter (rc[11:0] bits of the sr) the repeat counter is specifies the number of repetitions by the setrc instruction. during repeat loop execution, the rc holds the remaining number of repetitions. ? repeat flags (rf[1:0] bits of the sr) the repeat flags are automatically specified according to the rs and re register values during setrc instruction execution. the repeat flags store information on the number of instructions included in the repeat loop. normally, the us er cannot modify the repeat flag values. the cpu always executes instructions by comparing the re register to program counter values. because the pc stores (the curren t instruction address +4), if the re matches the pc during repeat instruction detection execution, a repeat detection in struction can be detected . if a repeat detection instruction is executed without branching and if rc[11:0] > 0, then repeat control is performed. if rc[11:0] 2 when the repeat end instruction is completed, the rc[11:0] is decremented by 1 and then control is passed to the addr ess specified by the rs register. examples 2 to 4 show program examples of the repeat loop consisting of three instructions, two instructions, and one instruction, respectively. in these examples, an instruction immediately prior to the repeat start instruction is regarded as a rep eat detection instruction. the rs register specifies the specific value that indicates th e number of repeat instructions.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 80 of 950 rej09b0079-0200 ? example 2: repeat loop consisting of three instructions ldrs rptstart +4 ; sets (repeat detection instruction address + 4) to the rs register ldre rptstart +4 ; sets (repeat detection instruction address + 4) to the re register setrc #4 ; sets the number of repetitions (4) to the rc[11:0] bits of the sr register ; if re-rs==0 during setrc instruction execution, the repeat loop is regarded as three-instruction repeat. rptdtct: instr0 ; an instruction prior to the repeat start instruction is regarded as a repeat detection instruction. rptstart: instr1 ; [repeat start instruction] instr2 ; rptend: instr3 ; [repeat end instruction] ? example 3: repeat loop consisting of two instructions ldrs rptstart +6 ; sets (repeat detection instruction address + 6) to the rs register ldre rptstart +4 ; sets (repeat detection instruction address + 4) to the re register setrc #4 ; sets the number of repetitions (4) to the rc[11:0] bits of the sr register ; if re-rs==-2 during setrc instruction execution, the repeat loop is regarded as two-instruction repeat. rptdtct: instr0 ; an instruction prior to the repeat start instruction is regarded as a repeat detection instruction. rptstart: instr1 ; [repeat start instruction] rptend: instr2 ; [repeat end instruction]
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 81 of 950 rej09b0079-0200 ? example 4: repeat loop consisting of one instruction ldrs rptstart +8 ; sets (repeat detection instruction address + 8) to the rs register ldre rptstart +4 ; sets (repeat detection instruction address + 4) to the re register setrc #4 ; sets the number of repetitions (4) to the rc[11:0] bits of the sr register ; if re-rs==-4 during setrc instruction execution, the repeat loop is regarded as one-instruction repeat. rptdtct: instr0 ; an instruction prior to the repeat start instruction is regarded as a repeat detection instruction. rptstart: rptend: instr1 ; [repeat start instruction] == [repeat end instruction] in repeat loops consisting of three instructions , two instructions and on e instruction, specific addresses are specified in the rs register. re ? rs is calculated during setrc instruction execution, and the number of instructions included in the repeat loop is determined according to the result. a value of 0, ?2,and ?4 in the result correspond to 3 instructions, two instructions, and one instruction, respectively. if repeat instruction execution is completed without branching and if rc[11:0]>0, an instruction following the repeat detection instruction is regard ed as a repeat start instruction and instruction execution is repeated for the nu mber of times corresponding to the recognized number of instructions. if rc[11:0] 2 when the repeat end instructio n is completed, the rc[11:0] is decremented by 1 and then control is passed to the address specified by the rs register. if rc[11:0] ==1(or 0) when the repeat end instruction is completed, the rc[11:0] is cleared to 0 and then the control is passed to the next instruction following the repeat end instruction. note: if re ? rs is a positive value, the cpu regard s the repeat loop as a four-instruction repeat loop. (in a repeat loop consisting of four or more instructions, re ? rs is always a positive value. for details, refer to example 1 above.) if re ? rs is positive, or a value other than 0, ?2,and ?4, correct operation cannot be guaranteed.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 82 of 950 rej09b0079-0200 the rule is shown in table 3.3. table 3.3 rs and re setting rule number of instructions in repeat loop 1 2 3 4 rs rptstart0 + 8 rptstart0 + 6 rptstart0 + 4 rptstart re rptstart0 + 4 rptstart0 + 4 rptstart0 + 4 rptend3 + 4 note: the terms used above in table 3.3, are defined as follows. rptstart: address of the repeat start instruction rptstart0: address of the instruction one inst ruction prior to the r epeat start instruction rptend3: address of the instruction three inst ructions prior to the repeat end instruction repeat control instructions and repeat control macros: to describe a repeat loop, the rs and re registers must be specifie d appropriately by the ldrs and ldrs instructions and then the number of repetitions must be specified by the sertc instruction. an 8-bit immediate data or a general register can be used as an operand of th e setrc instruction. to specify the rc as a value greater than 256, use setrc rm type instructions. table 3.4 repeat control instructions instruction operation number of execution states ldrs @(disp,pc) calculates (disp x 2 + pc) and stores the result to the rs register 1 ldre @(disp,pc) calculates (disp x 2 + pc) and stores the result to the re register 1 setrc #imm sets 8-bit immediate data imm to the rc[11:0] bits of the sr register and sets the information related to the number of repetitions to the rf[1:0] bits of the sr. rc[11:0] can be specified as 0 to 255. 1 setrc rm sets the[11:0] bits of t he rm register to the rc[11:0] bits of the sr register and sets the information related to the number of repetitions to the rf[1:0] bits of the sr. rc[11:0] can be specified as 0 to 4095. 1 the rs and re registers mu st be specified appropriately accordin g to the rules shown in table 3.3. the sh assembler supports control macros (repeat) as shown in table 3.5 to solve problems.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 83 of 950 rej09b0079-0200 table 3.5 repeat control macros instruction operation number of execution states repeat rptstart, rptend, #imm specifies rp tstart as repeat start instruction, rptend as repeat end instruction, and 8-bit immediate data #imm as nu mber of repetitions. this macro is extended to three instructions: ldrs, ldre, and setrc which are converted correctly. 3 repeat rptstart, rptend, rm specifies rp tstart as repeat start instruction, rptend as repeat end inst ruction, and the [11:0] bits of rm as number of repetitions. this macro is extended to three instructions: ldrs, ldre, and setrc which are converted correctly. 3 using the repeat macros shown in table 3.5, examples 1 to 4 shown above can be simplified to examples 5 to 8 as shown below. ? example 5: repeat loop consisting of 4 or more instructions (extended to the instruction stream shown in example 1, above) repeat rptstart, rptend, #4 instr0 ; rptstart: instr1 ; [repeat start instruction] ... ... ; ... ... ; instr(n-3) ; instr(n-2) ; instr(n-1) ; rptend: instrn ;[repeat end instruction] ? example 6: repeat loop consisting of three instructions (extended to the instruction stream shown in example 2, above) repeat rptstart, rptend, #4 instr0 ; rptstart: instr1 ; [repeat start instruction] instr2 ; rptend: instr3 ; [repeat end instruction]
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 84 of 950 rej09b0079-0200 ? example 7: repeat loop consisting of two instructions (extended to the instruction stream shown in example 3, above) repeat rptstart, rptend, #4 instr0 ; rptstart: instr1 ; [repeat start instruction] rptend: instr2 ; [repeat end instruction] ? example 8: repeat loop consisting of one instruction instructions (extended to the instruction stream shown in example 4, above) repeat rptstart, rptend, #4 instr0 ; rptstart: rptend: instr1 ; [repeat start instruction] == [repeat end instruction] in the dsp mode, the system control instructions (ldc and stc) that handle the rs and re registers are extended. the rc[11:0] bits and rf[1:0] bits of the sr can be controlled by the ldc and stc instructions for the sr register. these instructions should be used if an exception is enabled during repeat loop executi on. the repeat loop can be resu med correctly by storing the rs and re register values and rc[11:0] bits and rf[1:0] bits of the sr register before exception handling and by restoring the stored values after exception handling. however, note that there are some restrictions on exception acceptance during repeat loop execution. for details refer to restrictions on repeat loop control in section 3.3.1, repeat control instructions and section 4, exceptation handling. table 3.6 dsp mode extended system control instructions instruction operation number of execution states stc rs, rn rs rn 1 stc re, rn re rn 1 stc.l rs, @-rn rn-4 rn, rs (rn) 1 stc.l re, @-rn rn-4 rn, re (rn) 1 ldc.l @rn+, rs (rn) rs, rn+4 rn 4 ldc.l @rn+, re (rn) re, rn+4 rn 4 ldc rn,rs rn rs 4 ldc rn, re rn re 4
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 85 of 950 rej09b0079-0200 restrictions on repeat loop control 1. repeat control instruction assignment the setrc instruction must be executed after executing the ldrs and ldre instructions. in addition, note that at least one instruction is required between the setrc instruction and a repeat start instruction. 2. illegal instruction one or more instructions following the repeat detection instruction if one of the following instructions is execut ed between an instruc tion following a repeat detection instruction to a repeat end instruction, an illegal instruction exception occurs. ? branch instructions bra, bsr, bt, bf, bt/f, bf/s, bsrf, rts, braf, rte, jsr, jmp, trapa ? repeat control instructions setrc, ldrs, ldre ? load instructions for sr, rs, and re registers ldc rn,sr, ldc @rn+,sr, ldc rn,re, ldc @rn+,re, ldc rn,rs, ldc @rn+,rs note: this restriction applies to all instructions for a repeat loop consisting of one to three instructions and to three instructions including a repeat end instruct ion for a repeat loop consisting of four or more instructions. 3. instructions prohibited during repeat loop (in a repeat loop consisting of four or more instructions) the following instructions must not be placed between the repeat start instruction and repeat detection instruction in a repeat loop consisting of four or more instructions. otherwise, the correct operation ca nnot be guaranteed. ? repeat control instructions setrc, ldrs, ldre ? load instructions for sr, rs, and re registers ldc rn,sr, ldc @rn+,sr, ldc rn,re, ldc @rn+,re, ldc rn,rs, ldc @rn+,rs note: multiple repeat loops cannot be guaranteed. describe the inner loop by repeat control instructions, and the external loop by other instructions such as dt or bf/s. 4. restriction on branching to an instruction following the repeat detection instruction and an exception acceptance
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 86 of 950 rej09b0079-0200 execution of a repeat detection instruction must be completed without any branch so that the cpu can recognize the repeat lo op. therefore, when the executio n branches to an instruction following the repeat detection in struction, the control will no t be passed to a repeat start instruction after executing a rep eat end instruction because the re peat loop is not recognized by the cpu. in this case, the rc[11:0] bits of the sr register will not be changed. ? if a conditional branch instruction is used in th e repeat loop, an instru ction before a repeat detection instruction must be speci fied as a branch destination. ? if a subroutine call is used in the repeat loop, a delayed slot instruction of the subroutine call instruction must be placed before a repeat detection instruction. here, a branch includes a return from an excep tion processing routine. if an exception whose return address is placed in an instruction following the repeat detection instruct ion occurs, the repeat control cannot be returned correctly. accordingly, an excep tion acceptance is restricted from the repeat detection instruct ion to the repeat end instruction. exceptions such as interrupts that can be retained by the cpu are retained. for ex ceptions that cannot be retained by the cpu, a transition to an exception occurs but a program cannot be returned to the previous execution state correctly. for details, refer to section 4, exception handling. notes: 1. if a trapa instruction is used as a repeat detection instruction, an instruction following the repeat detection instruction is re garded as a return address. in this case, a control cannot be returned to the repeat co ntrol correctly. in a tr apa instruction, an address of an instruction following the repeat detection address is regarded as return address. accordingly, to return to the repeat contro l correctly, place a return address prior to the repeat detection instruction. 2. if a sleep instruction is placed following a repeat detection instruct ion, a transition to the low-power consumption state or an exce ption acceptance such as interrupts can be performed correctly. in this case, however, the repeat control cannot be returned correctly. to return to the repeat contro l correctly, the sleep instruction must be placed prior to th e repeat detection instruction. 5. branch from a repeat detection instruction if a repeat detection instruction is a delayed slot instruction of a delayed branch instruction or a branch instruction, a repeat loop can be ac knowledged when a branch does not occur in a branch instruction. if a branch occurs in a bran ch instruction, a repeat control is not performed and a branch destination instruction is executed. 6. program counter during repeat control
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 87 of 950 rej09b0079-0200 if rc[11:0] 2, the program counter (pc) value is not correct for instructions two instructions following a repeat detection instruction. in a repeat loop consisting of one to three instructions, the pc indicates the correct value (instruction address + 4) for an in struction (repeat start instruction) following a repeat detection instruction but the pc continues to indicate the same address (repeat start in struction address) from the subseq uent instruction to a repeat end instruction. in a repeat loop consisting of four or more instructions, the pc indicates the correct value (instruction address + 4) for an instruction following a repeat detec-tion instruction, but pc indicates the rs and (rs +2 ) for instructions two and three instructions following the repeat detection instruction. here, rs indicates the value stored in the repeat start register (rs). the correct operation cannot be guaranteed for the incorrect pc values. accordingly, pc relative addressi ng instructions placed two or mo re instructions following the repeat detection instruction cannot be execute d correctly and the correct results cannot be obtained. ? pc relative addressing instructions mova @(disp, pc), rn mov.w @(disp, pc), rn mov.l @(disp, pc), rn (including the case when the mov #imm,rn is extended to mov.w @(disp, pc), rn or mov.l @(disp, pc), rn) table 3.7 pc value during re peat control (when rc[11:0] 2) number of instructions in repeat loop 1 2 3 4 rptdtct rptdtct + 4 rptdtct + 4 rptdtct + 4 rptdtct +4 rptdtct1 rptdtct1 + 4 rptdtct1 + 4 rptdtc t1 + 4 rptdtct1 + 4 rptdtct2 ? rptdtct1 + 4 rptdtct1 + 4 rs rptdtct3 ? ? rptdtct1 + 4 rs + 2 note: in table 3.7, the following labels are used. rptdtct: an address of the repeat detection instruction rptdtct1: an address of the instruction one instruction following the repeat start instruction (in a repeat loop consisting of one to three instructions, rptstart is a repeat start instruction) rptdtct2: an address of the instruction two instruction following the repeat start instruction rptdtct3: an address of the instruction thr ee instruction following the repeat start instruction 7. repeat counter and repeat control
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 88 of 950 rej09b0079-0200 the cpu always executes a program with comp aring the repeat end register (re) and the program counter (pc). if the pc matches the re while the rc[11:0] bits of the sr register are other than 0, the repeat control function is initiated. ? if rc 2, a control is passed to a repeat start in struction after a repeat end instruction has been executed. the rc is decremented by 1 at the completion of the re peat end instruction. in this case, restrictions 1 to 6 are also applied. ? if rc == 1, the rc is decremented to 0 at the completion of the repeat end instruction and a control is passed to the subsequent instructi on. in this case, restri ctions 1 to 6 are also applied. ? if rc == 0, the repeat control function is not initiated even if a repeat detection instruction is executed. the repeat loop is executed once as normal instru ctions and a control is not be passed to a repeat start instruction even if a repeat end instruction is executed. 3.3.2 extended repeat control instructions in the repeat control function described in section 3.3.1, repeat control instructions, there are some restrictions. to reduce these restrictions, this lsi supports the extend ed repeat instructions to extend the repeat control function. these ex tended repeat control instructions were not supported in the conventional sh-dsp. to keep compatibility with the conventional sh-dsp, use the conventional repeat control instructions ca lled compatible repeat control instructions. program examples using the extended repeat control instructions: examples of repeat loop programs using the extended repeat control instructions are shown below.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 89 of 950 rej09b0079-0200 ? example 1: repeat loop consisting of 4 or more instructions ldrs rptstart ; sets repeat start instruction address to the rs register ldre rptend ; sets repeat end instruction address to the re register ldrc #4 ; sets the number of repetitions (4) to the rc[11:0] bits of the sr register instr0 ; at least one instruction is required from ldrc instruction to [repeat start instruction] rptstart: instr1 ; [repeat start instruction] ... ... ; ... ... ; instr(n-3) ; instr(n-2) ; instr(n-1) ; rptend: instrn ; [repeat end instruction] ? example 2: repeat loop consisting of three instructions ldrs rptstart ; sets repeat start instruction address to the rs register ldre rptend ; sets repeat end instruction address to the re register ldrc #4 ; sets the number of repetitions (4) to the rc[11:0] bits of the sr register instr0 ; at least one instruction is required from ldrc instruction to [repeat start instruction] rptstart: instr1 ; [repeat start instruction] instr2 ; rptend: instr3 ; [repeat end instruction]
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 90 of 950 rej09b0079-0200 ? example 3: repeat loop consisting of two instructions ldrs rptstart ; sets repeat start instruction address to the rs register ldre rptend ; sets repeat end instruction address to the re register ldrc #4 ; sets the number of repetitions (4) to the rc[11:0] bits of the sr register instr0 ; at least one instruction is required from ldrc instruction to [repeat start instruction] rptstart: instr1 ; [repeat start instruction] rptend: instr2 ; [repeat end instruction] ? example 4: repeat loop consisting of one instructions ldrs rptstart ; sets repeat start instruction address to the rs register ldre rptend ; sets repeat end instruction address to the re register ldrc #4 ; sets the number of repetitions (4) to the rc[11:0] bits of the sr register instr0 ; at least one instruction is required from ldrc instruction to [repeat start rptstart: instruction] rptstart: rptend: instr1 ; [repeat start instruction]= [repeat end instruction] in extended repeat control instructions, a rep eat start instruction a ddress and a repeat end instruction address are stored in the rs register and re register, respectively, regardless of the number of repeat instructions. in addition, the ex tended repeat control can be performed by using the ldrc instruction instead of the setrc instruc tion. during the extended repeat control, a repeat loop can be recognized by executing a repeat end instruction. therefore, there is no restriction on branches or exceptions. extended repeat control instructions: to describe the extended repeat loop, the repeat start and end addresses must be specified to the rs and re registers by the ldrs and ldre instructions, respectively. for the ldrs and ldre instructions of the extended repeat control instructions, the ldrs and ldre instructions of the compatible repeat control instructions are used. the number of repetitions are specified by th e ldrc instruction. an 8-bit immediate data or the general register values can be used as an operand of the ldrc instruction. if 256 or greater value is specified to the rc, us e the ldrc rm type instructions.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 91 of 950 rej09b0079-0200 table 3.8 extended repeat control instructions instruction operation number of execution states ldrs @(disp,pc) calculates (disp x 2 + pc) and stores the result to the rs register 1 ldre @(disp,pc) calculates (disp x 2 + pc) and stores the result to the re register 1 ldrc #imm sets 8-bit immediate data imm to the rc[11:0] bits of the sr register and sets the information related to the number of repetitions to the rf[1:0] bits of the sr. rc[11:0] can be specified as 0 to 255. during extended repeat control, bit 0 of the re register is set to 1. 1 ldrc rm sets the[11:0] bits of the rm register to the rc[11:0] bits of the sr register and sets the information related to the number of repetitions to the rf[1:0] bits of the sr. rc[11:0] can be specified as 0 to 4095. during extended repeat control, bit 0 of the re register is set to 1. 1 by executing the ldrc instruction, the cpu performs the extended repeat control function. to indicate that the cpu is being in extended repeat co ntrol, bit 0 of the re register is set to 1 by executing the ldrc instruction. to change the re register value by a process such as an exception handling, bit 0 of the re register must be saved and restored correctly. by saving and restoring the rc[11:0] bits, dsp bit, and rf[1:0] bits of the sr register, re register, and rs register correctly, a control is re turned to the extended repeat function correctly after processing such as exception handling. restrictions on extended repeat loop control 1. extended repeat control instruction assignment the ldrc instruction must be executed after ex ecuting the ldrs and ld re instructions. in addition, note that at least one instruction is required between the ldrc instruction and a repeat start instruction. 2. illegal instruction one or more instructions following the repeat detection instruction if one of the following instructions is executed as a repeat end instruction, an illegal instruction exception occurs. ? branch instructions
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 92 of 950 rej09b0079-0200 bra, bsr, bt/s, bf/s, bsrf, rts, braf, rte, jsr, jmp ? repeat control instructions setrc, ldrs, ldre, ldrc ? load instructions for sr, rs, and re registers lcd rn,sr, ldc @rn+,sr, ldc rn,re, ldc @rn+,re, ldc rn,rs, ldc @rn+,rs note: a branch instruction without delay (bt, bf, trapa) can be placed as a repeat end instruction. a delay stop of a delayed branch instruction can also be placed as a repeat end instruction. in this case, the rc[11:0] value is decremented by 1 regardless of branch occurrence. if no branch occurs, a control return s to a repeat start instruction. if a branch occurs, a control is passed to a branch destination. 3. repeat counter and repeat control the cpu always execute a program with comparin g the repeat end register (re) and the (pc ? 4) (current instruction address). if the (pc ? 4) [31:1] matches the re [31:1] while bit 0 of re register is set to 1 and rc [11:0] of sr register is not 0, the extended repeat control function is initiated. ? if rc 2, a control is passed to a repeat start in struction after a repeat end instruction has been executed. the rc is decremented by 1 at th e completion of the repeat end instruction. ? if rc == 1, the rc is decremented to 0 at the completion of the repeat end instruction and a control is passed to the subsequent instruction. ? if rc == 0, the repeat control function is not initiated even if a repeat detection instruction is executed. the repeat loop is executed once as normal instru ctions and a control is not be passed to a repeat start instruction even if a repeat end instruction is executed.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 93 of 950 rej09b0079-0200 3.4 dsp data transfer instructions in dsp mode, data transfer instructions are added for the dsp unit registers. the newly added instructions are classified into the following three groups. 1. double data transfer instructions the dsp unit is connected to the x memory an d y memory via the specific buses called x bus and y bus. by using the data tr ansfer instructions using the x and y buses, two data items can be transferred between the dsp unit and x/y memo ries simultaneously. these instructions are called double data transfer instructions. thes e double data transfer instructions can be described in combination with the dsp operation in structions to execute data transfer and data operation in parallel, 2. single data transfer instructions the dsp unit is also connected to the l bus that is used by the cpu. the dsp registers other than the dsr can access any logical addresses gene rated by the cpu. in this case, the single data transfer instructions are us ed. the single data transfer instructions cannot be used in combination with the dsp operation instructions and can access only one data item at a time. 3. system control instructions some of the dsp unit registers are handled as the cpu system registers. to control these system registers, the system c ontrol registers are supported. th e dsp registers are connected to the cpu general registers via the data transfer bus (c bus). in any dsp data transfer instru ctions, an address to be accessed is generated and output by the cpu. for dsp data transfer instructions, some of the cpu general registers are used for address generation and specific addressing modes are used.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 94 of 950 rej09b0079-0200 x memory dsp unit xdb [15:0] xab [15:0] cpu ya b [15:0] cdb [31:0] dsr a0 a1 m0 m1 x0 x1 y0 y1 a0g a1g lab [31:0] ldb [31:0] ydb [15:0] y memory [legend] xab: xdb: yab: ydb: lab: ldb: cdb: x bus (address) x bus (data) y bus (address) y bus (data) l bus (address) l bus (data) c bus (data) figure 3.4 dsp registers and bus connections double data transfer instructions (movx.w, movy.w, movx.l, movy.l): with double data transfer group in structions, x memory and y memo ry can be accessed in parallel. in this case, the specific buses called x bus and y bus are used to access x memory and y memory, respectively. to fetch the cpu instructions, the l bus is used. accordingly, no conflict occurs among x, y, and l buses. load instructions for x memory specify the x0 or x1 register as the de stination operand. load instructions for y memory specify the y0 or y1 register as the destination operand. store registers for x or y memory specify the a0 or a1 register as the source operand. these instructions use only word data (16 bits). when a word data transfer instruction is executed, the upper word of register operand is used. to load word data, data is loaded to the upper word of the destination register and the lower word of the destinatio n register is automatically cleared to 0.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 95 of 950 rej09b0079-0200 double data transfer instructions can be described in parallel to the dsp operation instructions. even if a conditional operation instruction is specified in parallel to a double data transfer instruction, the specified condition does not affect the data transfer operations. for details, refer to section 3.5, dsp data operation instructions. double data transfer instruc tions can access only the x memory or y memory and cannot access other memory space. the x bus and y bus are 16 bits and support 64-byte address spaces corresponding to address areas h?a5000000 to h?a500ffff and h?a5010000 to h?a501ffff, respectively. because these areas are included in the p2/uxy area, they ar e not affected by the cache and address translation unit. single data transfer instructions: the single data transfer in structions access any memory location. all dsp registers other than the dsr* can be specified as source and destination operands. guard bit registers a0g and a1g can also be specified as two independent registers. because these instructions use th e l bus (lab and ldb), these in structions can access any logical space handled by the cpu. if these instructions access the c acheable area while the cache is enabled, the area accessed by thes e instructions are cached. the x memory and y memory are mapped to the logical address space and can al so be accessed by the single data transfer instructions. in this case, bus conflict may occu r between data transfer and instruction fetch because the cpu also uses the l bus for instruction fetches. the single data transfer instructions can handle both word and longword data. in word data transfer, only the upper word of the operand register is valid. in word data load, word data is loaded into the upper word of the destination registers and the lower word of the destination is automatically cleared to 0. if the guard bits are supported, the sign bit is extended before storage. in longword data load, longword data is loaded into the upper and lower word of the destination register. if the guard bits are supported, the sign bit is extended before storage. when the guard register is stored, the sign bit is extended to the upper 24 bits of the ldb and are loaded onto the ldb bus. notes: * because the dsr register is defined as the system register, it can be accessed by the lds or sts instruction. 1. any data transfer instruction is ex ecuted at the ma stage of the pipeline. 2. any data transfer instruction does not modify the condition code bits of the dsr register. system control instructions: the dsr, a0, x0, x1, y0, and y1 registers in the dsp unit can also be used as the cpu system registers. accordingly, data tr ansfer operations between these dsp system registers and general registers or memory can be executed by the sts and lds instructions. these dsp system re gisters can be treated as the cp u system register such as pr, macl and mach and can use the same addressing modes.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 96 of 950 rej09b0079-0200 table 3.9 extended system cont rol instructions in dsp mode instruction operation execution states sts dsr,rn dsr rn 1 sts a0,rn a0 rn 1 sts x0,rn x0 rn 1 sts x1,rn x1 rn 1 sts y0,rn y0 rn 1 sts y1,rn y1 rn 1 sts.l dsr,@-rn rn ? 4 rn, dsr (rn) 1 sts.l a0,@-rn rn ? 4 rn, a0 (rn) 1 sts.l x0,@-rn rn ? 4 rn, x0 (rn) 1 sts.l x1,@-rn rn ? 4 rn, x1 (rn) 1 sts.l y0,@-rn rn ? 4 rn, y0 (rn) 1 sts.l y1,@-rn rn ? 4 rn, y1 (rn) 1 lds.l @rn+,dsr (rn) dsr, rn + 4 rn 1 lds.l @rn+,a0 (rn) a0, rn + 4 rn 1 lds.l @rn+,x0 (rn) x0, rn + 4 rn 1 lds.l @rn+,x1 (rn) x1, rn + 4 rn 1 lds.l @rn+,y0 (rn) y0, rn + 4 rn 1 lds.l @rn+,y1 (rn) y1, rn + 4 rn 1 lds rn,dsr rn dsr 1 lds rn,a0 rn a0 1 lds rn,x0 rn x0 1 lds rn,x1 rn x1 1 lds rn,y0 rn y0 1 lds rn,y1 rn y1 1
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 97 of 950 rej09b0079-0200 3.4.1 general registers the dsp instructions 10 general registers in the 16 general registers as address pointers or index registers for double data transfers and single data transfers. in the following descriptions, another register function in the dsp instructions is also indicated within parentheses [ ]. ? double data transfer instru ctions (x memory and y memory are accessed simultaneously) in double data transfers, x memory y memory can be accessed simultaneously. to specify x and y memory addresses, two address pointers are supported. address pointer index register x memory (movx.w) r4, r5[ax] r8 [ix] y memory (movy.w) r6, r7[ay] r9 [iy] ? single data transfer instructions in single data transfer, any logical address sp ace can be accessed via the l bus. the following address pointers and index registers are used. address pointer index register any logical space (movs.w/l) r4, r5, r2, r3[as] r8 [is] 31 general registers (dsp mode) x and y double data transfers: r4, 5 r8 single data transfer s: r4, 5, 2, 3 r8 r6, 7 r9 [ax] [ix] [as] [is] [ay] [iy] : address register set for the for x data memory : index regiser for x address register set ax : address register set for all data memories : index regiser used for single data transfers : address register set for the for y data memory : index regiser for y address register set ay r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 [as2] [as3] [as0] [as1, ax1] [ay0] [ay1] [ix, is] [iy] 0 figure 3.5 general registers (dsp mode)
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 98 of 950 rej09b0079-0200 in assembler, r0 to r9 are used as symbols. in the dsp data tr ansfer instructions, the following register names (alias) can also be used. in assembler, described as shown below. ix: .reg (r8) ix indicates the alias of register 8. other aliases are shown below. ax0: .reg (r4) ax1: .reg (r5) ix: .reg (r8) ay0: .reg (r6) ay1: .reg (r7) iy: .reg (r9) as0: .reg (r4); this definition is used for if the alias is required in the single data transfer as1: .reg (r5); this definition is used for if the alias is required in the single data transfer as2: .reg (r2) as3: .reg (r3) is: .reg (r8); this definition is used for if th e alias is required in the single data transfer
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 99 of 950 rej09b0079-0200 3.4.2 dsp data addressing table 3.10 shows the relationship between the double data transfer instructions and single data transfer instructions. table 3.10 overview of da ta transfer instructions double data transfer instructions single data transfer instructions movx.w movy.w movs.w movs.l address register ax: r4, r5, ay: r6, r7 as: r2, r3, r4, r5 index register ix: r8, iy: r9 is: r8 addressing nop/inc (+2)/index addition: post-increment nop/inc (+2, +4)/index addition: post-increment addressing ? dec (?2, ?4): pre-decrement modulo addressing possible not possible data bus xdb, ydb ldb data length 16 bits (word) 16/32 bits (word/longword) bus conflict no yes memory x/y data memory entire memory space source register dx, dy: a0, a1 ds : a0/a1, m0/m1, x0/x1, y0/y1, a0g, a1g destination register dx: x0/x1 dy: y0/y1 ds: a0/a1, m0/m1, x0/x1, y0/y1, a0g, a1g addressing mode for double data transfer instructions: the double data transfer instructions supports the following three addressing modes. ? non-update address register addressing the ax and ay register s are address po inters. they are not updated. ? increment address register addressing the ax and ay registers are address pointers. af ter a data transfer, they are each incremented by 2 (post- increment). ? addition index register addressing the ax and ay registers are address pointers. after a data tr ansfer, the value of the ix or iy register is added to each (post-in crement). the double da ta transfer instructi ons do not supports
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 100 of 950 rej09b0079-0200 decrement addressing mode. to perform decrementing, ?2 is set in the index register and addition index register addressing is specified. when using x/y data addressing, bit 0 of the address pointer is invalid. accordingly, bit 0 of the address pointer and index register must be cleared to 0 in x/y data addressing. when accessing x and y memory using the x and y buses, the upper word of ax and ay is ignored. the result of ay+ or ay+iy is stored in the lower word of ay, while the upper word retains its original value. the ax and ax +ix oper ations are executed in longword (32 bits) and the upper word may be changed according to the result. single data addressing: the following four kinds of addressing can be used with single data transfer instructions. ? non-update address register addressing the as register is an address pointer. an acce ss to @as is performed but as is not updated. ? increment address register addressing: the as register is an address pointer. after an access to @as, the as register is incremented by 2 or 4 (post-increment). ? addition index register addressing: the as register is an address pointer. after an access to @as, the value of the is register is added to the as register (post-increment). ? decrement address register addressing: the as register is an address pointer. before a data transfer, ?2 or ?4 is added to the as register (i.e. 2 or 4 is s ubtracted) (pre-decrement). in single data transfer instructions, all bits in 32-bit address are valid. 3.4.3 modulo addressing in double data transfer instructions, a modulo addressing can be used. if the address pointer value reaches the preset modulo end address while a modulo addressi ng mode is specified, the address pointer value becomes the modulo start address. to control modulo addressing, the modulo register (mod) extended in the dsp mode and the dmx and dmy bits of the sr register are used. the mod register is provided to set the start and end addresses of the modulo address area. the upper and lower words of the mod register store modulo start address (ms) and modulo end
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 101 of 950 rej09b0079-0200 address (me), respectively. the ldc and stc in structions are extended for mod register handling. if the dmx bit of the sr register is set, the modulo addressing is speci fied for the x address register. if the dmy bit of the sr register is set, the modulo addressing is specified for the y address register. modulo addressing is valid for either the x or the y address register, only; it cannot be set for both at the same time. therefore, dmx and dmy cannot both be set simultaneously (if they are, the dmy setting will be valid). ( in the future, this specification may be changed.) the dmx and dmy bits of the sr can be specified by the stc or ldc instruction for the sr register. if an exception is accepted during modulo addres sing, the dmx and dmy bits of the sr and mod register must be saved. by restoring these register values, a control is returned to the modulo addressing after an exception handling. table 3.11 modulo addressing control instructions instruction operation execution states stc mod, rn mod rn 1 stc.l mod, @ ? rn rn ? 4 rn, mod (rn) 1 ldc @rn+, mod (rn) mod, rn + 4 rn 4 ldc rn, mod rn mod 4
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 102 of 950 rej09b0079-0200 an example of the use of modulo addressing is shown below. mov.l #h?70047000,r10 ;specify ms=h?7000 me = h?7004 ldc r10,mod ;specify me:ms to mod register stc sr,r10 ; mov.l #h?fffff3ff,r11 ; mov.l #h?00000400,r12 ; and r11,r10 ; or r12,r10 ; ldc r10,sr ; specify sr.dmx=1, sr.dmy=0, and x modulo addressing mode mov.l #h?a5007000,r14 movx.w @r4+,x0 ; r4: h?a5007000 h?a5007002 movx.w @r4+,x0 ; r4: h?a5007002 h?a5007004 movx.w @r4+,x0 ; r4: h?a5007004 h?a5007000 (matches to me and ms is set) movx.w @r4+,x0 ; r4: h?a5007000 h?a5007002 movx.w @r4+,x0 ; r4: h?a5007000 h?a5007002 the start and end addresses are specified in ms and me, then the dmx or dmy bit is set to 1. when the x or y data transfer instruction specifi ed by the dmx or dmy is executed, the address register contents before updating are compared with me * , and if they match, start address ms is stored in the address register as the value after updating. when the addressing type of the x/y data transfer instruction is no-update, the x/y data transfer instruction is not returned to ms even if they match me. when the addressing type of the x/y data transfer instruction is addition index register addressing, the address pointed way not match the address poin ter me and exceed it. in this case, the address pointer value does not become the modulo start address. the maximum modulo size is 64 kbytes. this is sufficient to access the x and y data memory. note: * not only with modulo addressing, but when x and y data addressing is used, bit 0 is ignored. 0 must always be written to bit 0 of the address pointer, index register, ms, and me.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 103 of 950 rej09b0079-0200 3.4.4 memory data formats memory data formats that can be used in the dsp instructions are classified into word, and longword. an address error will occur if word data starting from an address other than 2n or longword data starting from an address other than 4n is accessed by movs.l, lds.l, or sts.l instruction. in such cases, the data accessed cannot be guaranteed an address error will not occur if word data starting from an addres s other than 2n is accessed by the movx.w or movy.w instruction. when using the movx.w or movy.w instruction, an address must be specified on the boundary 2n. if an address is sp ecified other than 2n, the data accessed cannot be guaranteed. 3.4.5 instruction formats of double and single transfer instructions the format of double data transfer instructions is shown in tables 3.12, and that of single data transfer instructions in table 3.13.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 104 of 950 rej09b0079-0200 table 3.12 double data tr ansfer instruction formats type mnemonic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nopx 0 0 0 0 0 movx.w @ax,dx 1 1 1 1 0 0 ax dx 0 0 1 movx.w @ax+,dx 1 0 movx.w @ax+ix,dx 1 1 movx.w da,@ax da 1 0 1 movx.w da,@ax+ 1 0 x memory data transfer movx.w da,@ax+ix 1 1 nopy 0 0 0 0 0 movy.w @ay,dy 1 1 1 1 0 0 ay dy 0 0 1 movy.w @ay+,dy 1 0 movy.w @ay+iy,dy 1 1 movy.w da,@ay da 1 0 1 movy.w da,@ay+ 1 0 y memory data transfer movy.w da,@ay+iy 1 1 note: ax: 0 = r4, 1 = r5 ay: 0 = r6, 1 = r7 dx: 0 = x0, 1 = x1 dy: 0 = y0, 1 = y1 da: 0 = a0, 1 = a1
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 105 of 950 rej09b0079-0200 table 3.13 single data tr ansfer instruction formats type mnemonic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 movs.w @-as,ds 1 1 1 1 0 1 as ds 0:( * ) 0 0 0 0 movs.w @as,ds 0:r4 1:( * ) 0 1 movs.w @as+,ds 1:r5 2:( * ) 1 0 movs.w @as+is,ds 2:r2 3:( * ) 1 1 movs.w ds,@-as 3:r3 4:( * ) 0 0 0 1 movs.w ds,@as 5:a1 0 1 movs.w ds,@as+ 6:( * ) 1 0 movs.w ds,@as+is 7:a0 1 1 movs.l @-as,ds 8:x0 0 0 1 0 movs.l @as,ds 9:x1 0 1 movs.l @as+,ds a:y0 1 0 movs.l @as+is,ds b:y1 1 1 movs.l ds,@-as c:m0 0 0 1 1 movs.l ds,@as d:a1g 0 1 movs.l ds,@as+ e:m1 1 0 single data transfer movs.l ds,@as+is f:a0g 1 1 note: * codes reserved for system use.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 106 of 950 rej09b0079-0200 3.5 dsp data operation instructions 3.5.1 dsp registers this lsi has eight data registers (a0, a1, x0, x1, y0, y1, m0 and m1) and one control register (dsr) as dsp registers (figure 3.3). four kinds of operation access the dsp data regist ers. the first is dsp da ta processing. when a dsp fixed-point data operation uses a0 or a1 as th e source register, it uses the guard bits (bits 39 to 32). when it uses a0 or a1 as the destination register, guard bits 39 to 32 are valid. when a dsp fixed-point data operation uses a dsp register other than a0 or a1 as the source register, it sign-extends the source value to bits 39 to 32. when it uses one of these registers as the destination register, bits 39 to 32 of the result are discarded. the second kind of operation is an x or y da ta transfer operation, movx.w, movy.w. this operation accesses the x and y memories through the 16-bit x and y data bu ses (figure 3.4). the register to be loaded or stored by this operation always comprises the upper 16 bits (bits 31 to 16). x0 or x1 can be the destination of an x memory load and y0 or y1 can be the destination of a y memory load, but no other register can be the destination register in this operation. when data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the register (bits 15 to 0) are automatically cleared. a0 an d a1 can be stored in the x or y memory by this operation, but no other registers can be stored. the third kind of operation is a single-data transfer instruct ion, movs.w or movs.l. these instructions access any memory location through the ldb (figure 3.4). all dsp registers connect to the ldb and can be the source or destination register of the data transfer. these instructions have word and longword access modes. in word mode, registers to be loaded or stored by this instruction comprise the upper 16 bits (bits 31 to 16) for dsp registers except a0g and a1g. when data is loaded into a register other than a0g and a1g in word mode, the lower half of the register is cleared. when a0 or a1 is used, the data is sign-extended to bits 39 to 32 and the lower half is cleared. when a0g or a1g is the destinati on register in word mode, data is loaded into an 8-bit register, but a0 or a1 is not cleared. in longword mode, when the destination register is a0 or a1, it is sign-extended to bits 39 to 32. the fourth kind of operation is system control instructions such as lds, sts, lds.l, or sts.l. the dsr, a0, x0, x1, y0, and y1 registers of the ds p register can be treated as system registers. for these registers, data transfer instructions between the cpu general registers and system registers or memory access instructions are supported.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 107 of 950 rej09b0079-0200 tables 3.14 and 3.15 show the data type of registers used in dsp instructions. some instructions cannot use some registers shown in the tables because of instruction code limitations. for example, pmuls can use a1 as the source register, but cannot use a0. these tables ignore details of register selectability. table 3.14 destination regi ster in dsp instructions guard bits register bits registers instructions 39 32 31 16 15 0 fixed-point, psha, pmuls sign-extended 40-bit result integer, pdmsb sign-extended 24-bit result cleared dsp operation logical, pshl cleared 16-bit result cleared movs.w sign-extended 16-bit data cleared a0, a1 data transfer movs.l sign-extended 32-bit data movs.w data no update a0g, a1g data transfer movs.l data no update fixed-point, psha, pmuls 32-bit result dsp operation integer, logical, pdmsb, pshl 16-bit result cleared movx/y.w, movs.w 16-bit result cleared x0, x1 y0, y1 m0, m1 data transfer movs.l 32-bit data
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 108 of 950 rej09b0079-0200 table 3.15 source register in dsp operations guard bits register bits registers instructions 39 32 31 16 15 0 fixed-point, pdmsb, psha 40-bit data integer 24-bit data dsp operation logical, pshl, pmuls 16-bit data movx/y.w, movs.w 16-bit data a0, a1 data transfer movs.l 32-bit data movs.w data a0g, a1g data transfer movs.l data fixed-point, pdmsb, psha sign * 32-bit data integer sign * 16-bit data dsp operation logical, pshl, pmuls 16-bit data movs.w 16-bit data x0, x1 y0 , y1 m0, m1 data transfer movs.l 32-bit data note: * the data is sign-extended and input to the alu. the dsp unit incorporates one cont rol register and dsp status regi ster (dsr). the dsr register stores the dsp data operation result (zero, negative, others). the dsp register also has the dc bit whose function is similar to the t bit of the cpu register. the dc bit functions as status flag. conditional dsp data operations are controlled based on the dc bit. these operation control affects only the dsp unit instructions. in other words, these operations control affects only the dsp registers and does not affect address register update and cpu instructions such as load and store instructions. a condition to be reflected on the dc bit should be specified to the dc status selection bits (cs[2:0]). the unconditional dsp type data instructions other than pmuls, movx, movy, and movs change the condition flag and dc bit. however, the cpu instructions including the mac instruction do not modify the dc bit. in addition, conditional dsp instructions do not modify the dsr.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 109 of 950 rej09b0079-0200 table 3.16 dsr register bits bits bit name initial value r/w function 31 to 12 ? all 0 r reserved bits these bits are always read as 0. the write value should always be 0. 11 to 9 ts2 to ts0 all 0 r/w t bit status selection specifies the operation result status to be set in the t bit in the sr register if the tc bit is 1. if the s bit of the sr register is set to 1, an overflow is detected. 000: carry/borrow mode 001: negative value mode 010: zero mode 011: overflow mode 100: signed greater mode 101: signed greater than or equal to mode 110: reserved (setting prohibited) 111: reserved (setting prohibited) 8 tc 0 r/w tc bit 0: the t bit of the sr register is not affected by the dsp instruction. 1: the t bit of the sr register changes according to the ts bit of the dsr register while the dsp instruction is executed. note, however, the t bit does not change during conditional dsp instruction execution. 7 gt 0 r/w signed greater bit indicates that the operation result is positive (except 0), or that operand 1 is greater than operand 2 1: operation result is posit ive, or operand 1 is greater than operand 2 6 z 0 r/w zero bit indicates that the operation re sult is zero (0), or that operand 1 is equal to operand 2 1: operation result is zero (0), or operands are equal
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 110 of 950 rej09b0079-0200 bits bit name initial value r/w function 5 n 0 r/w negative bit indicates that the operation re sult is negative, or that operand 1 is smaller than operand 2 1: operation result is negative, or operand 1 is smaller than operand 2 4 v 0 r/w overflow bit indicates that the operation result has overflowed 1: operation result has overflowed 3 to 1 cs2 to cs0 all 0 r/w dc bit status selection designate the mode for select ing the operation result status to be set in the dc bit 000: carry/borrow mode 001: negative value mode 010: zero mode 011: overflow mode 100: signed greater mode 101: signed greater than or equal to mode 110: reserved (setting prohibited) 111: reserved (setting prohibited) 0 dc 0 r/w dsp status bit sets the status of the oper ation result in the mode designated by the cs bits 0: designated mode status has not occurred (false) 1: designated mode status has occurred indicates the operation result by carry or borrow regardless of the cs bit status after the paddc or psubc instruction has been executed.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 111 of 950 rej09b0079-0200 the dsr is assigned to the syst em registers. for the dsr, the following load and store instructions are supported. sts dsr,rn; sts.l dsr,@-rn; lds rn,dsr; lds.l @rn+,dsr; if the dsr is read by the sts instruction, upper bits (bits 31 to 16) are all 0 3.5.2 dsp operation instruction set dsp operation instructions are instructions for digital signal processing performed by the dsp unit. these instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. the instruction code is divided into an a field and b field; a parallel data transfer instruction is specified in the a field, and a single or double data operation instruction in the b field. instructions can be specified independently, and are also executed independently. b-field data operation instructions are of three kinds: double data operation instructions, conditional single data operation instructions, and unconditional single data operation instructions. the formats of the dsp operation instructions are shown in table 3.17 . the respective operands are selected independently from the dsp regist ers. the correspondence between dsp operation instruction operands and registers is shown in table 3.18.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 112 of 950 rej09b0079-0200 table 3.17 dsp operation instruction formats type instruction formats double data operation instructions aluop. sx, sy, du mltop. se, df, dg conditional single data operation instructions dct aluop. sx, sy, dz dcf aluop. sx, sy, dz dct aluop. sx, dz dcf aluop. sx, dz dct aluop. sy, dz dcf aluop. sy, dz unconditional single data operation instructions aluop. sx, sy, dz aluop. sx, dz aluop. sy, dz mltop. se, sf, dg table 3.18 correspondence between dsp instruction operands and registers alu/shift operations multiply operations register sx sy dz du se sf dg a0 yes yes yes yes a1 yes yes yes yes yes yes m0 yes yes yes m1 yes yes yes x0 yes yes yes yes yes x1 yes yes yes y0 yes yes yes yes yes y1 yes yes yes when writing parallel instructions, the b-field instruction is written first, followed by the a-field instruction. a sample parallel processing program is shown in figure 3.6.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 113 of 950 rej09b0079-0200 padd pinc pcmp dcf movx.w movx.w movx.w @r4+, @r5+r8, @r4, x0 x0 x1 movy.w movy.w [nopy] @r6+, @r7+, y0 y1 a0, m1, m1, m0, a1 m0 a0 pmuls x0, y0, m0 figure 3.6 sample parallel instruction program [ ] mean that the contents can be omitted. the no operation instructions nopx and nopy can be omitted. for details on the b field in dsp data operation instructions, refer to section 3.6.4, dsp operation instructions. the dsr register condition code bit (dc) is always updated on the basis of the result of an unconditional alu or shift operation instruction. conditional instructions do not update the dc bit. multiply instructions, also, do not update the dc bit. dc bit updating is performed by means of the cs[2:0] bits in the dsr register. the dc bit update rules are shown in table 3.19.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 114 of 950 rej09b0079-0200 table 3.19 dc bit update definitions cs [2:0] condition mode description 0 0 0 carry or borrow mode the dc bit is set if an alu arithm etic operation generates a carry or borrow, and is cleared otherwise. when a psha or pshl shift instruction is executed, the last bit data shifted out is copied into the dc bit. when an alu logical operation is executed, the dc bit is always cleared. 0 0 1 negative value mode when an alu or shift (psha) arit hmetic operation is executed, the msb of the result, including the guard bits, is copied into the dc bit. when an alu or shift (pshl) logical operation is executed, the msb of the result, excluding the guard bits, is copied into the dc bit. 0 1 0 zero value mode the dc bit is set if t he result of an alu or shift operation is all- zeros, and is cleared otherwise. 0 1 1 overflow mode the dc bit is set if the re sult of an alu or shift (psha) arithmetic operation exceeds the destination register range, excluding the guard bits, and is cleared otherwise. when an alu or shift (pshl) logical operation is executed, the dc bit is always cleared. 1 0 0 signed greater-than mode this mode is similar to signed greater-or-equal mode, but dc is cleared if the result is all-zeros. dc = ~{(negative value ^ over-range) | zero value}; in case of arithmetic operation dc = 0; in case of logical operation 1 0 1 signed greater-or- equal mode if the result of an alu or shi ft (psha) arithmetic operation exceeds the destination register range, including the guard bits (over-range), the definition is t he same as in negative value mode. if the result is not over-rang e, the definition is the opposite of that in negative value mode. when an alu or shift (pshl) logical operation is executed, the dc bit is always cleared. dc = ~(negative value ^ over-range); in case of arithmetic operation dc = 0 ; in case of logical operation 1 1 0 reserved (setting prohibited) 1 1 1 reserved (setting prohibited)
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 115 of 950 rej09b0079-0200 ? conditional operations and data transfer some instructions belonging to this class can be executed conditionally, as described earlier. the specified condition is valid only for the b field of the instruction, and is not valid for data transfer instructions for which a parallel specif ication is made. examples are shown in figure 3.7. dct padd x0,y0,a0 movx.w @r4+,x0 movy.w a0,@r6+r9 ; when condition is true before execution: after execution: x0=h'33333333, y0=h'55555555, a0=h'123456789a, r4=h'00008000, r6=h'00005000, r9=h'00000004 (r4)=h'1111, (r6)=h'2222 x0=h'11110000, y0=h'55555555, a0=h'0088888888, r4=h'00008002, r6=h'00005004, r9=h'00000004 (r4)=h'1111, (r6)=h'3456 when condition is false before execution: after execution: x0=h'33333333, y0=h'55555555, a0=h'123456789a, r4=h'00008000, r6=h'00005000, r9=h'00000004 (r4)=h'1111, (r6)=h'2222 x0=h'11110000, y0=h'55555555, a0=h'123456789a, r4=h'00008002, r6=h'00005004, r9=h'00000004 (r4)=h'1111, (r6)=h'3456 figure 3.7 examples of conditional operations and data transfer instructions ? assignment of nopx and nopy instruction codes when there is no data transfer instruction to be parallel-processed simultaneously with a dsp operation instruction, an nopx or nopy instru ction can be written as the data transfer instruction, or the instruction can be omitted. the instruction code is the same whether an nopx or nopy instruction is written or the in struction is omitted. examples of nopx and nopy instruction codes are shown in table 3.20.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 116 of 950 rej09b0079-0200 table 3.20 examples of nopx and nopy instruction codes instruction code padd x0,y0,a0 movx.w @r4+,x0 movy.w @r6+r9,y0 1111100000001011 1011000100000111 padd x0,y0,a0 nopx movy.w @r6+r9,y0 1111100000000011 1011000100000111 padd x0,y0,a0 nopx nopy 1111100000000000 1011000100000111 padd x0,y0,a0 nopx 1111100000000000 1011000100000111 padd x0,y0,a0 1111100000000000 1011000100000111 movx.w @r4+,x0 movy.w @r6+r9,y0 1111000000001011 movx.w @r4+,x0 nopy 1111000000001000 movs.w @r4+,x0 1111010010001000 nopx movy.w @r6+r9,y0 1111000000000011 movy.w @r6+r9,y0 1111000000000011 nopx nopy 1111000000000000 nop 0000000000001001 3.5.3 dsp-type data formats this lsi has several different data formats that depend on the instruction. this section explains the data formats for dsp type instructions. figure 3.8 shows three dsp-type data formats with different binary point positions. a cpu-type data format with the binary point to the right of bit 0 is also shown for reference. the dsp-type fixed point data format has the binary point between bit 31 and bit 30. the dsp- type integer format has the binary point between bit 16 and bit 15. the dsp-type logical format does not have a binary point. the valid data lengths of the data formats depend on the instruction and the dsp register.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 117 of 950 rej09b0079-0200 39 s 31 30 0 ?2 8 to +2 8 ? 2 ?31 39 s 32 31 0 ?2 23 to +2 23 ? 1 39 s s 31 30 16 15 16 15 0 ?1 to +1 ? 2 ?15 39 31 16 15 0 s 31 0 ?2 15 to +2 15 ? 1 16 15 31 22 0 ?32 to +32 16 15 s 31 21 0 ?16 to +16 16 15 s 31 30 0 ?1 to +1 ? 2 ?31 s 31 0 ?2 31 to +2 31 ? 1 dsp type fixed point with guard bits without guard bits multiplier input dsp type integer dsp type logical with guard bits cpu type integer s: sign bit longword : binary point : does not affect the operations without guard bits shift amount for arithmetic shift (psha) shift amount for logical shift (pshl) figure 3.8 data formats the shift amount for the arithmetic shift (psha) instruction has a 7-bit field that can represent values from ?64 to +63, but ?32 to +32 are valid numbers for the instruction. also the shift amount for a logical shift operation has a 6-bit field, but ?16 to +16 are valid numbers for the instruction. the results when an invalid shif t amount is specified cannot be guaranteed.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 118 of 950 rej09b0079-0200 3.5.4 alu fixed-point operations figure 3.9 shows the alu arithmetic operation flow. table 3.21 shows the variation of this type of operation and table 3.22 shows the correspondence between each operand and registers. 39 31 31 39 31 0 source 1 0 destination alu dsr 39 0 source 2 guard guard guard gt z n v dc figure 3.9 alu fixed-point arithmetic operation flow note: the alu fixed-point arithmetic operations are basically 40-bit operation; 32 bits of the base precision and 8 bits of the guard-bit parts. so the signed bit is copied to the guard-bit parts when a register not providing the guard-bit parts is specified as the source operand. when a register not providing the guard-bit part s is specified as a de stination operand, the lower 32 bits of the operation result are input into the destination register. alu fixed-point operations are executed between registers. each source and destination operand are selected independently from one of the dsp registers. when a register providing guard bits is specified as an operand, the guard bits are activat ed for this type of operation. these operations are executed in the dsp stage, as shown in figure 3.10. the dsp stage is the same stage as the ma stage in which memory access is performed.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 119 of 950 rej09b0079-0200 table 3.21 variation of alu fixed-point operations mnemonic function source 1 source 2 destination padd addition sx sy dz (du) psub subtraction sx sy dz (du) paddc addition with carry sx sy dz psubc subtraction with borrow sx sy dz pcmp comparison sx sy ? sx all 0 dz pcopy data copy all 0 sy dz sx all 0 dz pabs absolute all 0 sy dz sx all 0 dz pneg negation all 0 sy dz pclr clear all 0 all 0 dz table 3.22 correspondence be tween operands and registers register sx sy dz du a0 yes yes yes a1 yes yes yes m0 yes yes m1 yes yes x0 yes yes yes x1 yes yes y0 yes yes yes y1 yes yes as shown in figure 3.10, data loaded from the memory at the ma stage, which is programmed at the same line as the alu operation, is not used as a source operand for this operation, even though the destination operand of the data load operation is identical to the source operand of the alu operation. in this case, previous operation results are used as the source operands for the alu operation, and then updated as the destination operand of the data load operation.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 120 of 950 rej09b0079-0200 if 12 movx movx movx movx & padd movx & padd movx & padd 3456 id ex ma/dsp padd x0, y0, a0 movx.w @(r4, r8), x0 movx.w @r4+, x0 slot stage operation sequence example addressing addressing previous cycle result is used. figure 3.10 operation sequence example every time an alu arithmetic operation is executed, the dc, n, z, v, and gt bits in dsr are basically updated in accordance with the operatio n result. however, in case of a conditional operation, they are not updated ev en though the specified condition is true and the operation is executed. in case of an unconditional operation, they are always updated in accordance with the operation result. the definition of a dc bit is selected by cs[2:0] (condition selection) bits in dsr. the dc bit result is as follows: carry or borrow mode: cs[2:0] = 000: the dc bit indicates that car ry or borrow is generated from the most significant bit of the operation result, except the guard-bit parts. some examples are shown in figure 3.11. this mode is the default condition. when the input data is negative in a pabs or pneg instruction, carry is generated.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 121 of 950 rej09b0079-0200 example 1 carry detecting point guard bits carry is detected 0000 0000 +) 0000 0000 1111 0000 1111 0000 1111 0000 1111 0001 0000 0001 0000 0000 0000 0000 example 2 carry detecting point guard bits carry is not detected 1111 0011 +) 1111 1111 0111 0001 0000 0000 0000 0000 0000 0000 0011 (1) 11101000 0000 0000 0000 example 3 borrow detecting point guard bits borrow is not detected 0000 0000 ?) 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0000 0000 0000 0000 0000 0000 example 4 borrow detecting point guard bits borrow is detected 0000 0000 ?) 0000 0000 0001 0001 0000 0000 0000 0000 0001 0010 111111111111111111111111 figure 3.11 dc bit generation examples in carry or borrow mode negative value mode: cs[2:0] = 001: the dc flag indicates the same value as the msb of the operation result. when the result is a negative number, the dc bit shows 1. when it is a positive number, the dc bit shows 0. the alu always executes 40-bit arithmetic operation, so the sign bit to detect whether positive or negative is always got from the msb of the operation result regardless of the destination operand. some examples are shown in figure 3.12. example 1 sign bit guard bits negative value 1100 0000 +) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1100 0000 0000 0000 0000 0001 example 2 sign bit guard bits positive value 0011 0000 +) 0000 0000 0000 1000 0000 0000 0000 0000 0000 0001 0011 0000 1000 0000 0000 0001 figure 3.12 dc bit generation examples in negative value mode zero value mode: cs[2:0] = 010: the dc flag indicates whether the operation result is 0 or not. when the result is 0, the dc bit shows 1. when it is not 0, the dc bit shows 0. overflow mode: cs[2:0] = 011: the dc bit indicates whether or not overflow occurs in the result. when an operation yields a result beyond th e range of the destinatio n register, except the
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 122 of 950 rej09b0079-0200 guard-bit parts, the dc bit is set. even though guard bits are provided in the destination register, the dc bit always indicates the result of when no guard bits are provided. so, the dc bit is always set if the guard-bit parts are used for large number representation. some dc bit generation examples in overflow mode are shown in figure 3.13. example 1 overflow detecting field guard bits overflow case 1111 1111 +) 1111 1111 1111 1000 1111 0000 1111 0000 1111 0000 11111111 0111 111111111111 example 2 overflow detecting field guard bits non overflow case 1111 1111 +) 1111 1111 1111 1000 1111 0000 1111 0000 1111 0001 11111111 1000 0000 0000 0000 figure 3.13 dc bit generation examples in overflow mode signed greater than mode: cs[2:0] = 100: the dc bit indicates whet her or not the source 1 data (signed) is greater than the source 2 data (signed) as the result of compare operation pcmp. this mode is similar to the negative value m ode described before, because the result of a compare operation is a positive va lue if the source 1 data is greater than the source 2 data. however, the signed bit of the result shows a negative value if the compare operation yields a result beyond the range of the destination operand, including the guard-bit parts (called ?over- range?), even though the source 1 data is greater than the source 2 data. the dc bit is updated concerning this type of special case in this condition mode. the equation below shows the definition of getting this condition: dc = ~ {(negative ^ over-range) | zero} when the pcmp operation is executed under this condition mode, the result of the dc bit is the same as the t bit?s result of the cmp/gt operation of the cpu instruction. signed greater than or equal mode: cs[2:0] = 101: the dc bit indicates whether the source 1 data (signed) is greater than or equal to the source 2 data (signed) as the result of compare operation pcmp. this mode is similar to the signed greater than mode described before but the equal case is also included in this mode. the equation below shows the definition of getting this condition: dc = ~ (negative ^ over-range) when the pcmp operation is executed under this condition mode, the result of the dc bit is the same as the t bit?s result of a cmp/ge operation of the sh core instruction.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 123 of 950 rej09b0079-0200 the n bit always indicates the same state as the dc bit set in negative value mode by the cs[2:0] bits. see the negative value mode part above. the z bit always indicates th e same state as the dc bit set in zero value mode by the cs[2:0] bits. see the zero value mode part above. the v bit always indicates the same state as the dc bit se t in overflow mode by the cs[2:0] bits. see the overflow mode part above. the gt bit always indi cates the same state as the dc bit set in signed greater than mode by the cs[2:0] bits. see the signed greater than mode part above. note: the dc bit is always updated as th e carry/borrow flag for ?paddc? and ?psubc? regardless of the cs[2:0] state. ? overflow protection the s bit in sr is effective for any alu fixed-point arithmetic operations in the dsp unit. see section 3.5.11, overflow protection, for details. 3.5.5 alu integer operations figure 3.14 shows the alu integer arithmetic operation flow. table 3.23 shows the variation of this type of operation. the correspondence betw een each operand and registers is the same as alu fixed-point operations as shown in table 3.22. 31 31 39 ignored cleared to 0 31 39 0 source 1 0 destination alu dsr 39 0 source 2 gt z n v dc guard guard guard figure 3.14 alu integer arithmetic operation flow
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 124 of 950 rej09b0079-0200 table 3.23 variation of alu integer operations mnemonic function source 1 source 2 destination sx +1 dz pinc increment by 1 +1 sy dz sx ?1 dz pdec decrement by 1 ?1 sy dz note: the alu integer operations are basically 24 -bit operation, the upper 16 bits of the base precision and 8 bits of the guard-bits parts. so the signed bit is copied to the guard-bit parts when a register not providing the guard-bit pa rts is specified as the source operand. when a register not providing the guard-bit parts is specified as a destination operand, the upper word excluding the guard bits of the operation re sult are input into the destination register. in alu integer arithmetic operations, the lower wo rd of the source operand is ignored and the lower word of the destination operand is automati cally cleared. the guard-bi t parts are effective in integer arithmetic operations if they are supporte d. others are basically the same operation as alu fixed-point arithmetic operations. as shown in table 3.23, however, this type of operation provides two kinds of instructions only, so that the second operand is actually either +1 or ?1. when a word data is loaded into one of the dsp uni t?s registers, it is input as an upper word data. when a register providing guard bits is specified as an operand, the guard bits are also activated. these operations, as well as fixed-point operati ons, are executed in the dsp stage, as shown in figure 3.10. the dsp stage is the same stag e as the ma stage in which memory access is performed. every time an alu arithmetic operation is executed, the dc, n, z, v, and gt bits in dsr are basically updated in accordance with the operatio n result. this is the same as fixed-point operations but the lower word of each source and destination operand is not used in order to generate them. see section 3.5.4, alu fixed-point operations, for details. in case of a conditional operation, they are not updat ed even though the speci fied condition is true and the operation is executed. in case of an unconditional operatio n, they are always updated in accordance with the operatio n result. see section 3.5.4, alu fi xed-point operations, for details. ? overflow protection the s bit in sr is effective for any alu intege r arithmetic operations in dsp unit. see section 3.5.11, overflow protection, for details.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 125 of 950 rej09b0079-0200 3.5.6 alu logical operations figure 3.15 shows the alu logical operation flow. table 3.24 shows the variation of this type of operation. the correspondence be tween each operand and registers is the same as the alu fixed- point operations as shown in table 3.21. the alu logical operation is executed between regi sters. each source and destination operand is selected independently from one of the dsp registers. as shown in figure 3.15, this type of operation uses only the upper word of each operand. the lower word and guard-bit parts are ignored for the source operand and those of th e destination operand are automatically cleared. these operations are also executed in the dsp stag e, as shown in figure 3. 10. the dsp stage is the same stage as the ma stage in which memory access is performed. 31 31 31 39 39 39 ignored cleared to 0 0 source 1 0 destination alu dsr 0 source 2 gt z n v dc figure 3.15 alu logical operation flow table 3.24 variation of alu logical operations mnemonic function source 1 source 2 destination pand logical and sx sy dz por logical or sx sy dz pxor logical exclusive or sx sy dz every time an alu logical operat ion is executed, the dc, n, z, v, and gt bits in the dsr register are basically updated in accordance with the operation re sult. in case of a conditional operation, they are not updated ev en though the specified condition is true and the operation is executed. in case of an unconditional operation, they are always updated in accordance with the
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 126 of 950 rej09b0079-0200 operation result. the definition of the dc bit is selected by the cs[2:0] (condition selection) bits in dsr. the dc bit result is: carry or borrow mode: cs[2:0] = 000: the dc bit is always cleared. negative value mode: cs[2:0] = 001: bit 31 of the operation result is loaded into the dc bit. zero value mode: cs[2:0] = 010: the dc bit is set when the operation result is zero; otherwise it is cleared. overflow mode: cs[2:0] = 011: the dc bit is always cleared. signed greater than mode: cs[2:0] = 100: the dc bit is always cleared. signed greater than or equal mode: cs[2:0] = 101: the dc bit is always cleared. the n bit always indicates the same state as the dc bit set in ne gative value mode by the cs[2:0] bits. see the negative value mode part above. the z bit always indicates th e same state as the dc bit set in zero value mode by the cs[2:0] bits. see the zero value mode part above. the v bit always indicates the same state as the dc bit set in overflow mode by the cs[2:0] bits. see the overflow mode part above. the gt bit always indi cates the same state as the dc bit set in signed greater than mode by the cs[2:0] bits. see the signed greater than mode part above. 3.5.7 fixed-point multiply operation figure 3.16 shows the multiply operation flow. table 3.25 shows the variation of this type of operation and table 3.26 shows the correspondence between each operand and registers. the multiply operation of the dsp unit is single-word signed single-precision multiplication. these operations are executed in the dsp stage, as shown in figure 3.10. the dsp stage is the same stage as the ma stage in which memory access is performed. if a double-precision multiply operation is need ed, the cpu standard double-word multiply instructions can be made of use.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 127 of 950 rej09b0079-0200 39 31 0 source 1 s 39 31 1 0 mac ignored s0 39 31 0 source 2 s destination 0 figure 3.16 fixed-point multiply operation flow table 3.25 variation of fixed-point multiply operation mnemonic function source 1 source 2 destination pmuls signed multiplication se sf dg table 3.26 correspondence be tween operands and registers register se sf dg a0 ? ? yes a1 yes yes yes m0 ? ? yes m1 ? ? yes x0 yes yes ? x1 yes ? ? y0 yes yes ? y1 ? yes ? note: the multiply operations basically generat e 32-bit operation results. so when a register providing the guard-bit parts are specified as a destination operand, the guard-bit parts will copy bit 31 of the operation result. the multiply operation of the dsp unit side is not integer but fixed-point arithmetic. so, the upper words of each multiplier and multipli cand are input into a mac unit as shown in figure 3.16. in the sh's standard multiply operations, the lower wo rds of both source operands are input into a mac unit. the operation result is also different fr om the sh's case. the sh 's multiply operation
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 128 of 950 rej09b0079-0200 result is aligned to the lsb of the destination, but the fixed-point multiply operation result is aligned to the msb, so that the lsb of the fixed-point multiply operation result is always 0. multiply is always unconditional, but does not affect any condition code bits, dc, n, z, v, and gt , in dsr. ? overflow protection the s bit in sr is effective for this multiply operation in the dsp unit. see section 3.5.11, overflow protection, for details. if the s bit is 0, overflow occurs only when h'8000*h'8000 ((-1.0)*(-1.0)) operation is executed as signed fixed-point multiply. the result is h'00 8000 0000 but it does not mean ( +1.0 ). if the s bit is 1, overflow is prevented and the result is h'00 7fff ffff . 3.5.8 shift operations shift operations can use either register or immediate value as the shift amount operand. other source and destination operands are specified by the register. there are two kinds of shift operations of arithmetic and logical shifts. table 3.27 shows the variation of this type of operation. the correspondence between each operand and registers, except fo r immediate operands, is the same as the alu fixed-point operations as shown in table 3.21. table 3.27 variation of shift operations mnemonic function source 1 source 2 destination psha sx, sy, dz arithmetic shift sx sy dz pshl sx, sy, dz logical shift sx sy dz psha #imm1, dz arithmetic shift with immediate. dz imm1 dz pshl #imm2, dz logical shift with immediate. dz imm2 dz ?32 <= imm1 <= +32, ?16 <= imm2 <= +16
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 129 of 950 rej09b0079-0200 arithmetic shift: figure 3.17 shows the arithmetic shift operation flow. dsr gt z n v dc updated 39 32 31 16 15 0 sy 39 32 31 16 15 0 0 shift out shift out (msb copy) ignored left shift right shift 39 32 31 23 22 16 imm1 60 15 0 shift amount data (source 2) >=0 <0 +32- -32 figure 3.17 arithmetic shift operation flow note: the arithmetic shift operations are basically 40-bit operation, that is , the 32 bits of the base precision and eight bits of the guard-bit parts. so the signed bit is copied to the guard- bit parts when a register not providing the guard-bit parts is specified as the source operand. when a register not providing the guard-bit parts is specified as a destination operand, the lower 32 bits of the operation result are input into the destination register. in this arithmetic shift operation, all bits of th e source 1 and destination operands are activated. the shift amount is specified by the source 2 operand as an inte ger data. the source 2 operand can be specified by either a register or immediate operand. the available shift range is from ?32 to +32. here, a negative value means th e right shift, and a positive valu e means the left shift. it is possible for any source 2 operand to specify from ?64 to +63 but the result is unknown if an invalid shift value is specified. in case of a shift with an immediate operan d instruction, the source 1 operand must be the same register as the destination?s. this operation is executed in the dsp stage, as shown in figure 3.10 as well as in fixed-point operations. the dsp stage is the same stage as the ma stage in which memory access is performed. every time an arithmetic shift operation is execute d, the dc, n, z, v, and gt bits in dsr are basically updated in accordance with the operation result. in case of a conditional operation, they are not updated even though the sp ecified condition is true and th e operation is executed. in case of an unconditional operation, th ey are always updated in accord ance with the operation result. the definition of the dc bit is selected by the cs[2:0] (condition selection) bits in dsr. the dc bit result is: 1. carry or borrow mode: cs[2:0] = 000 the dc bit indicates the last shifted out data as the operation result. 2. negative value mode: cs[2:0] = 001
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 130 of 950 rej09b0079-0200 the dc bit is set when the operation result is a negative value, and cleared when the operation result is zero or a positive value. 3. zero value mode: cs[2:0] = 010 the dc bit is set when the operation re sult is zero; otherwise it is cleared. 4. overflow mode: cs[2:0] = 011 the dc bit is set when an overflow occurs. 5. signed greater than mode: cs[2:0] = 100 the dc bit is always cleared. 6. signed greater than or equal mode: cs[2:0] = 101 the dc bit is always cleared. the n bit always indicates the same state as the dc bit set in ne gative value mode by the cs[2:0] bits. see the negative value mode part above. the z bit always indicates th e same state as the dc bit set in zero value mode by the cs[2:0] bits. see the zero value mode part above. the v bit always indicates the same state as the dc bit set in overflow mode by the cs[2:0] bits. see the overflow mode part above. the gt bit always indi cates the same state as the dc bit set in signed greater than mode by the cs[2:0] bits. see the signed greater than mode part above. ? overflow protection the s bit in sr is also effective for arithmeti c shift operation in the dsp unit. see section 3.5.11, overflow protection, for details.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 131 of 950 rej09b0079-0200 logical shift: figure 3.18 shows the logical shift operation flow. 39 32 31 16 15 0 sy 39 32 31 16 15 0 shift out shift out 0 0 cleared to 0 ignored left shift right shift 39 32 31 22 21 16 imm2 50 15 0 shift amount data (source 2) > = 0 < 0 +16- -16 dsr gt z n v dc updated figure 3.18 logical shift operation flow as shown in figure 3.18, the logical shift operation uses the upper word of the source 1 operand and the destination operand. the lower word and guard-bit parts are ignored for the source operand and those of the destination operand ar e automatically cleared as in the alu logical operations. the shift amount is specified by the so urce 2 operand as an integer data. the source 2 operand can be specified by either the register or immediate operand. the available shift range is from ?16 to +16. here, a negative value means the right shift, and a positive value means the left shift. it is possible for any source 2 operand to specify from ?32 to +31, but the result is unknown if an invalid shift value is specified. in case of a shift with an immediate operand instruction, the source 1 operand must be the same register as the destination's. these operations are executed in the dsp stage, as shown in figure 3.10. the dsp st age is the same stage as the ma stage in which memory access is performed. every time a logical shift operation is executed, th e dc, n, z, v, and gt bits in dsr are basically updated in accordance with the operation result. in case of a conditional op eration, they are not updated even though the specified condition is true and the operation is executed. in case of an unconditional operation, they are always updated in accordance with the operation result. the definition of the dc bit is selected by the cs[2:0 ] (condition selection) bits in dsr. the dc bit result is: 1. carry or borrow mode: cs[2:0] = 000 the dc bit indicates the last shifted out data as the operation result. 2. negative value mode: cs[2:0] = 001 bit 31 of the operation result is loaded into the dc bit. 3. zero value mode: cs[2:0] = 010
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 132 of 950 rej09b0079-0200 the dc bit is set when the operation re sult is zero; otherwise it is cleared. 4. overflow mode: cs[2:0] = 011 the dc bit is always cleared. 5. signed greater than mode: cs[2:0] = 100 the dc bit is always cleared. 6. signed greater than or equal mode: cs[2:0] = 101 the dc bit is always cleared. the n bit always indicates the same state as the dc bit set in ne gative value mode by the cs[2:0] bits. see the negative value mode part above. the z bit always indicates th e same state as the dc bit set in zero value mode by the cs[2:0] bits. see the zero value mode part above. the v bit always indicates the same state as the dc bit set in overflow mode by the cs[2:0] bits, but it is always cleared in this oper ation. so is the gt bit. 3.5.9 most significant bit detection operation the pdmsb, most significant bit detection operation, is used to calculate the shift amount for normalization. figure 3.19 shows the pdmsb operation flow and table 3.28 shows the operation definition. table 3.29 shows the possible variations of this type of operation. the correspondence between each operand and registers is the same as for alu fixed-point operations, as shown in table 3.21. note: the result of the msb detection operation is basically 24 bits as well as alu integer operation, the upper 16 bits of the base precision and eight bits of the guard-bit parts. when a register not providing the guard-bit part s is specified as a de stination operand, the upper word of the operation result is input into the destination register. as shown in figure 3.19, the pdmsb operation uses all bits as a source operand, but the destination operand is treated as an integer op eration result because shift amount data for normalization should be integer data as descri bed in section 3.5.8, shift operations. these operations are executed in the dsp stage, as shown in figure 3.10. the dsp stage is the same stage as the ma stage in which memory access is performed. every time a pdmsb operation is executed, the dc, n, z, v, and gt bits in dsr are basically updated in accordance with the operation result. in case of a conditional operation, they are not updated, even though the specified condition is tr ue, and the operation is executed. in case of an unconditional operation, they are always updated with the operation result.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 133 of 950 rej09b0079-0200 39 31 39 31 0 0 cleared to 0 priority encoder source 1 or 2 dsr gt z n v dc guard guard figure 3.19 pdmsb operation flow the definition of the dc bit is selected by the cs0?cs2 (condition selection) bits in dsr. the dc bit result is carry or borrow mode: cs[2:0] = 000: the dc bit is always cleared. negative value mode: cs[2:0] = 001: the dc bit is set when the op eration result is a negative value, and cleared when the operation result is zero or a positive value. zero value mode: cs[2:0] = 010: the dc bit is set when the operation result is zero; otherwise it is cleared. overflow mode: cs[2:0] = 011: the dc bit is always cleared. signed greater than mode: cs[2:0] = 100: the dc bit is set when the operation result is a positive value; otherwise it is cleared. signed greater than or equal mode: cs[2:0] = 101: the dc bit is set when the operation result is zero or a positive value; otherwise it is cleared.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 134 of 950 rej09b0079-0200 table 3.28 operation definition of pdmsb source data result for dst guard bit upper word lower word guard bit upper word 39 38 ? 33 32 31 30 29 28 ? 3 2 1 0 39?32 31?22 21 20 19 18 17 16 deci- mal 0 0 ? 0 0 0 0 0 0 ? 0 0 0 0 all 0 all 0 0 1 1 1 1 1 +31 0 0 ? 0 0 0 0 0 0 ? 0 0 0 1 all 0 all 0 0 1 1 1 1 0 +30 0 0 ? 0 0 0 0 0 0 ? 0 0 1 * all 0 all 0 0 1 1 1 0 1 +29 0 0 ? 0 0 0 0 0 0 ? 0 1 * * all 0 all 0 0 1 1 1 0 0 +28 : : : 0 0 ? 0 0 0 0 0 1 ? * * * * all 0 all 0 0 0 0 0 1 0 +2 0 0 ? 0 0 0 0 1 * ? * * * * all 0 all 0 0 0 0 0 0 1 +1 0 0 ? 0 0 0 1 * * ? * * * * all 0 all 0 0 0 0 0 0 0 0 0 0 ? 0 0 1 * * * ? * * * * all 1 all 1 1 1 1 1 1 1 ?1 0 0 ? 0 1 * * * * ? * * * * all 1 all 1 1 1 1 1 1 0 ?2 : : : 0 1 ? * * * * * * ? * * * * all 1 all 1 1 1 1 0 0 0 ?8 1 0 ? * * * * * * ? * * * * all 1 all 1 1 1 1 0 0 0 ?8 : 1 1 ? 1 0 * * * * ? * * * * all 1 all 1 1 1 1 1 1 0 ?2 1 1 ? 1 1 0 * * * ? * * * * all 1 all 1 1 1 1 1 1 1 ?1 1 1 ? 1 1 1 0 * * ? * * * * all 0 all 0 0 0 0 0 0 0 0 1 1 ? 1 1 1 1 0 * ? * * * * all 0 all 0 0 0 0 0 0 1 +1 1 1 ? 1 1 1 1 1 0 ? * * * * all 0 all 0 0 0 0 0 1 0 +2 : : : 1 1 ? 1 1 1 1 1 1 ? 1 0 * * all 0 all 0 0 1 1 1 0 0 +28 1 1 ? 1 1 1 1 1 1 ? 1 1 0 * all 0 all 0 0 1 1 1 0 1 +29 1 1 ? 1 1 1 1 1 1 ? 1 1 1 0 all 0 all 0 0 1 1 1 1 0 +30 1 1 ? 1 1 1 1 1 1 ? 1 1 1 1 all 0 all 0 0 1 1 1 1 1 +31 note: * means don?t care.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 135 of 950 rej09b0079-0200 table 3.29 variation of pdmsb operation mnemonic function source source 2 destination pdmsb msb detection sx ? dz ? sy dz the n bit always indicates the same state as the dc bit set in negative value mode by the cs[2:0] bits. see the negative value mode part above. the z bit always indicates th e same state as the dc bit set in zero value mode by the cs[2:0] bits. see the zero value mode part above. the v bit always indicates the same state as the dc bit se t in overflow mode by the cs[2:0] bit. see the overflow mode part above. the gt bit always indi cates the same state as the dc bit set in signed greater than mode by the cs[2:0] bits. see the signed greater than mode part above. 3.5.10 rounding operation the dsp unit provides the function that rounds from 32 bits to 16 bits. in case of providing guard- bit parts, it rounds from 40 bits to 24 bits. when a round instruction is executed, h'00008000 is added to the source operand data and then, the lower word is cleared. figure 3.20 shows the rounding operation flow and figure 3.21 shows the operation definition. table 3.30 shows the variation of this type of operation. the corresp ondence between each operand and registers is the same as alu fixed-point operations as shown in table 3.21. as shown in figure 3.21, the rounding operation uses full-size data for both source and destination operands. these operations are executed in the ds p stage as shown in figure 3.10. the dsp stage is the same stage as the ma stage in which memory access is performed. every time rounding operation is executed, the dc, n, z, v, and gt bits in dsr are basically updated in accordance with the operation result. in case of a conditional operation, they are not updated, even though the specified condition is tr ue, and the operation is executed. in case of an unconditional operation, they are always updated with the operation results. the definition of the dc bit is selected by the cs0?cs2 (condition selection) bits in dsr. the result of these condition code bits is the same as the alu-fixed point arithmetic operations.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 136 of 950 rej09b0079-0200 31 31 0 alu h'00008000 39 39 0 cleared to 0 source 1 or 2 dsr gt z n v dc guard guard figure 3.20 rounding operation flow 0 h'00 0002 h'00 0001 h'00 0001 8000 h'00 0002 0000 h'00 0002 8000 rounded result analog value true value figure 3.21 definition of rounding operation table 3.30 variation of rounding operation mnemonic function source 1 source 2 destination prnd rounding sx ? dz ? sy dz ? overflow protection the s bit in sr is effective for any rounding operations in the dsp unit. see section 3.5.11, overflow protection, for details.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 137 of 950 rej09b0079-0200 3.5.11 overflow protection the s bit in sr is effective for any arithmetic operations executed in the dsp unit, including the sh's standard multiply and mac operations. the s bit in sr is used as the overflow protection enable bit. the arithmetic opera tion overflows when th e operation result exceeds the range of two?s complement representation without guard-bit parts. table 3.31 shows the definition of overflow protection for fixed-point arithmetic operations, including fixed-point signed by signed multiplication described in section 3.5.7, fixed-point multiply operation. table 3.32 shows the definition of overflow protection for integer arithmetic operations. the lower word of the saturation value of the integer arithmetic opera tion is don?t care. lower word value cannot be guaranteed. when the overflow protection is ef fective, overflow never occurs. so, the v bit is cleared, and the dc bit is also cleared when the overflow mode is selected by the cs[2:0] bits. table 3.31 definition of overflow protect ion for fixed-point arithmetic operations sign overflow condition fixed value hex representation positive result > 1 ? 2 ?31 1 ? 2 ?31 00 7fff ffff negative result < ?1 ?1 ff 8000 0000 table 3.32 definition of overflow prot ection for integer arithmetic operations sign overflow condition fixed value hex representation positive result > 2 15 ? 1 2 15 ? 1 00 7fff **** negative result < ?2 15 ?2 15 ff 8000 **** note: * means don't care.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 138 of 950 rej09b0079-0200 3.5.12 local data move instruction the dsp unit of this lsi provides additional two independent registers, macl and mach, in order to support cpu standard multiply/mac operations. they can be also used as temporary storage registers by local data move instructions between mach/l and other dsp registers. figure 3.22 shows the flow of seven local data move instructions. table 3.33 shows the variation of this type of instruction. plds psts cannot be used x0 y0 mach macl x1 y1 m1 a1 m0 a0 a0g a1g dsr figure 3.22 local data move instruction flow table 3.33 variation of local data move operations mnemonic function operand plds data move from dsp register to macl/mach dz psts data move from macl/mach to dsp register dz this instruction is very similar to other transfer instructions. if either the a0 or a1 register is specified as the destination operand of psts, the signed bit is sign-extended and copied into the corresponding guard-bit parts, a0g or a1g. the dc bit in dsr and other condition code bits are not updated regardless of the instruction result. this instruction can operate as a conditional. this instruction can operate with movx and movy in parallel.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 139 of 950 rej09b0079-0200 3.5.13 operand conflict when an identical destination operand is specified with multiple parallel instructions, data conflict occurs. table 3.34 shows th e correspondence between eac h operand and registers. table 3.34 correspondence be tween operands and registers x-memory load y-memory load 6-operand alu 3-operand multiply 3-operand alu ax ix dx ay iy dy sx sy du se sf dg sx sy dz a0 * 1 * 2 * 2 * 1 * 1 a1 * 1 * 2 * 1 * 1 * 2 * 1 * 1 m0 * 1 * 1 * 1 * 1 m1 * 1 * 1 * 1 * 1 x0 * 2 * 1 * 2 * 1 * 1 * 1 * 2 x1 * 2 * 1 * 1 * 1 * 2 y0 * 2 * 1 * 2 * 1 * 1 * 1 * 2 dsp registers y1 * 2 * 1 * 1 * 1 * 2 notes: 1. registers available for operands 2. registers available for operand s (when there is operand conflict) there are three cases of operand conflict problems. ? when alu operation and multiply instructions specify the same destination operand (du and dg) ? when x-memory load and alu operation specify the same destination operand (dx and du, or dz) ? when y-memory load and alu operation specify the same destination operand (dy and du, or dz) in these cases above, the result is not guaranteed.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 140 of 950 rej09b0079-0200 3.6 dsp extended function instruction set 3.6.1 cpu extended instructions table 3.35 dsp mode extended system control instructions instruction instruction code operation execution states t bit category setrc #imm 10000010iiiiiiii imm rc (of sr) 1 ? setrc rn 0100nnnn00010100 rn[11:0] rc(of sr) 1 ? ldrs @(disp,pc) 10001100dddddddd (disp x 2 + pc) rs 1 ? ldre @(disp,pc) 10001110dddddddd (disp x 2 + pc) re 1 ? stc mod,rn 0000nnnn01010010 mod rn 1 ? stc rs,rn 0000nnnn01100010 rs rn 1 ? stc re,rn 0000nnnn01110010 re rn 1 ? sts dsr,rn 0000nnnn01101010 dsr rn 1 ? sts a0,rn 0000nnnn01111010 a0 rn 1 ? sts x0,rn 0000nnnn10001010 x0 rn 1 ? sts x1,rn 0000nnnn10011010 x1 rn 1 ? sts y0,rn 0000nnnn10101010 y0 rn 1 ? sts y1,rn 0000nnnn10111010 y1 rn 1 ? sts.l dsr,@-rn 0100nnnn01100010 rn-4 rn, dsr (rn) 1 ? sts.l a0,@-rn 0100nnnn01110010 rn-4 rn, a0 (rn) 1 ? sts.l x0,@-rn 0100nnnn10000010 rn-4 rn, x0 (rn) 1 ? sts.l x1,@-rn 0100nnnn10010010 rn-4 rn, x1 (rn) 1 ? sts.l y0,@-rn 0100nnnn10100010 rn-4 rn, y0 (rn) 1 ? sts.l y1,@-rn 0100nnnn10110010 rn-4 rn, y1 (rn) 1 ? stc.l mod,@-rn 0100nnnn01010011 rn-4 rn, mod (rn) 1 ? stc.l rs,@-rn 0100nnnn01100011 rn-4 rn, rs (rn) 1 ? stc.l re,@-rn 0100nnnn01110011 rn-4 rn, re (rn) 1 ? lds.l @rn + ,dsr 0100nnnn01100110 (rn) dsr, rn + 4 rn 1 ? lds.l @rn + ,a0 0100nnnn01110110 (rn) a0, rn + 4 rn 1 ? lds.l @rn + ,x0 0100nnnn10000110 (rn) x0, rn + 4 rn 1 ? lds.l @rn + ,x1 0100nnnn10010110 (rn) x1, rn + 4 rn 1 ?
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 141 of 950 rej09b0079-0200 instruction instruction code operation execution states t bit category lds.l @rn + ,y0 0100nnnn10100110 (rn) y0, rn + 4 rn 1 ? lds.l @rn + ,y1 0100nnnn10110110 (rn) y1, rn + 4 rn 1 ? ldc.l @rn + ,mod 0100nnnn01010111 (rn) mod, rn + 4 rn 4 ? ldc.l @rn + ,rs 0100nnnn01100111 (rn) rs, rn + 4 rn 4 ? ldc.l @rn + ,re 0100nnnn01110111 (rn) re, rn + 4 rn 4 ? lds rn,dsr 0100nnnn01101010 rn dsr 1 ? lds rn,a0 0100nnnn01111010 rn a0 1 ? lds rn,x0 0100nnnn10001010 rn x0 1 ? lds rn,x1 0100nnnn10011010 rn x1 1 ? lds rn,y0 0100nnnn10101010 rn y0 1 ? lds rn,y1 0100nnnn10111010 rn y1 1 ? ldc rn,mod 0100nnnn01011110 rn mod 4 ? ldc rn,rs 0100nnnn01101110 rn rs 4 ? ldc rn,re 0100nnnn01111110 rn re 4 ?
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 142 of 950 rej09b0079-0200 3.6.2 double-data tr ansfer instructions table 3.36 double data transfer instruction instruction instruction code operation execution states dc nopx 1111000 * 0 * 0 * 00 ** x memory no access 1 ? movx.w @ax,dx 111100a * d * 0 * 01 ** (ax) msw of dx, 0 lsw of dx 1 ? movx.w @ax + ,dx 111100a * d * 0 * 10 ** (ax) msw of dx, 0 lsw of dx, ax + 2 ax 1 ? movx.w @ax + ix,dx 111100a * d * 0 * 11 ** (ax) msw of dx, 0 lsw of dx, ax + ix ax 1 ? movx.w da,@ax 111100a * d * 1 * 01 ** msw of da (ax) 1 ? movx.w da,@ax + 111100a * d * 1 * 10 ** msw of da (ax), ax + 2 ax 1 ? x memory data transfer movx.w da,@ax + ix 111100a * d * 1 * 11 ** msw of da (ax), ax + ix ax 1 ? nopy 111100 * 0 * 0 * 0 ** 00 y memory no access 1 ? movy.w @ay,dy 111100 * a * d * 0 ** 01 (ay) msw of dy, 0 lsw of dy 1 ? movy.w @ay + ,dy 111100 * a * d * 0 ** 10 (ay) msw of dy, 0 lsw of dy, ay + 2 ay 1 ? movy.w @ay + iy,dy 111100 * a * d * 0 ** 11 (ay) msw of dy, 0 lsw of dy, ay + iy ay 1 ? movy.w da,@ay 111100 * a * d * 1 ** 01 msw of da (ay) 1 ? movy.w da,@ay + 111100 * a * d * 1 ** 10 msw of da (ay), ay + 2 ay 1 ? y memory data transfer movy.w da,@ay + iy 111100 * a * d * 1 ** 11 msw of da (ay), ay + iy ay 1 ?
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 143 of 950 rej09b0079-0200 3.6.3 single-data transfer instructions table 3.37 single data transfer instructions instruction instruction code operation execu- tion states dc category movs.w @-as,ds 111101aadddd0000 as-2 as, (as) msw of ds, 0 lsw of ds 1 ? movs.w @as,ds 111101aadddd0100 (as) msw of ds, 0 lsw of ds 1 ? movs.w @as + ,ds 111101aadddd1000 (as) msw of ds, 0 lsw of ds, as + 2 as 1 ? movs.w @as + ix,ds 111101aadddd1100 (as) msw of ds, 0 lsw of ds, as + ix as 1 ? movs.w ds,@-as 111101aadddd0001 as-2 as, msw of ds (as) 1 ? * movs.w ds,@as 111101aadddd0101 msw of ds (as) 1 ? * movs.w ds,@as + 111101aadddd1001 msw of ds (as), as + 2 as 1 ? * movs.w ds,@as + ix 111101aadddd1101 msw of ds (as), as + ix as 1 ? * movs.l @-as,ds 111101aadddd0010 as-4 as, (as) ds 1 ? movs.l @as,ds 111101aadddd0110 (as) ds 1 ? movs.l @as + ,ds 111101aadddd1010 (as) ds, as + 4 as 1 ? movs.l @as + ix,ds 111101aadddd1110 (as) ds, as + ix as 1 ? movs.l ds,@-as 111101aadddd0011 as-4 as, ds (as) 1 ? movs.l ds,@as 111101aadddd0111 ds (as) 1 ? movs.l ds,@as + 111101aadddd1011 ds (as), as + 4 as 1 ? movs.l ds,@as + ix 111101aadddd1111 ds (as), as + ix as 1 ? note: * if guard bit registers a0g and a1g are specified in source operand ds, the data is output to the ldb[7:0] bus and the sign bit is copied into the upper bits, [31:8]. the correspondence between dsp da ta transfer operands and registers is shown in table 3.38.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 144 of 950 rej09b0079-0200 table 3.38 correspondence between dsp data transf er operands and registers register ax ix dx ay iy dy da as ds r0 r1 r2 (as2) yes r3 (as3) yes r4 (ax0) yes yes r5 (ax1) yes yes r6 (ay0) yes r7 (ay1) yes r8 (ix) yes sh register r9 (iy) yes a0 yes yes a1 yes yes m0 yes m1 yes x0 yes yes x1 yes yes y0 yes yes y1 yes yes a0g yes dsp register a1g yes note: yes: the register which can be set.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 145 of 950 rej09b0079-0200 3.6.4 dsp operation instructions table 3.39 dsp operation instructions instruction instruction code operation execu- tion states dc pmuls se,sf,dg 111110 ********** 0100eeff0000gg00 se * sf ->dg (signed) 1 ? padd sx,sy,du pmuls se,sf,dg 111110 ********** 0111eeffxxyygguu sx + sy ->du se * sf ->dg (signed) 1 * psub sx,sy,du pmuls se,sf,dg 111110 ********** 0110eeffxxyygguu sx-sy ->du se * sf ->dg (signed) 1 * padd sx,sy,dz 111110 ********** 10110001xxyyzzzz sx + sy ->dz 1 * dct padd sx,sy,dz 111110 ********** 10110010xxyyzzzz if dc=1, sx + sy ->dz if dc=0, nop 1 ? dcf padd sx,sy,dz 111110 ********** 10110011xxyyzzzz if dc=0, sx + sy ->dz if dc=1, nop 1 ? psub sx,sy,dz 111110 ********** 10100001xxyyzzzz sx-sy ->dz 1 * dct psub sx,sy,dz 111110 ********** 10100010xxyyzzzz if dc=1, sx-sy ->dz if dc=0, nop 1 ? dcf psub sx,sy,dz 111110 ********** 10100011xxyyzzzz if dc=0, sx-sy ->dz if dc=1, nop 1 ? psha sx,sy,dz 111110 ********** 10010001xxyyzzzz if sy>=0, sx<dz (arithmetic shift) if sy<0, sx>>sy ->dz 1 * dct psha sx,sy,dz 111110 ********** 10010010xxyyzzzz if dc=1 & sy>=0, sx<dz (arithmetic shift) if dc=1 & sy<0, sx>>sy ->dz if dc=0, nop 1 ? dcf psha sx,sy,dz 111110 ********** 10010011xxyyzzzz if dc=0 & sy>=0, sx<dz (arithmetic shift) if dc=0 & sy<0, sx>>sy ->dz if dc=1, nop 1 ?
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 146 of 950 rej09b0079-0200 instruction instruction code operation execution states dc pshl sx,sy,dz 111110 ********** 10000001xxyyzzzz if sy>=0, sx<dz (logical shift) if sy<0, sx>>sy ->dz 1 * dct pshl sx,sy,dz 111110 ********** 10000010xxyyzzzz if dc=1 & sy>=0, sx<dz (logical shift) if dc=1 & sy<0, sx>>sy ->dz if dc=0, nop 1 ? dcf pshl sx,sy,dz 111110 ********** 10000011xxyyzzzz if dc=0 & sy>=0, sx<dz (logical shift) if dc=0 & sy<0, sx>>sy ->dz if dc=1, nop 1 ? pcopy sx,dz 111110 ********** 11011001xx00zzzz sx ->dz 1 * pcopy sy,dz 111110 ********** 1111100100yyzzzz sy ->dz 1 * dct pcopy sx,dz 111110 ********** 11011010xx00zzzz if dc=1, sx ->dz if dc=0, nop 1 ? dct pcopy sy,dz 111110 ********** 1111101000yyzzzz if dc=1, sy ->dz if dc=0, nop 1 ? dcf pcopy sx,dz 111110 ********** 11011011xx00zzzz if dc=0, sx ->dz if dc=1, nop 1 ? dcf pcopy sy,dz 111110 ********** 1111101100yyzzzz if dc=0, sy ->dz if dc=1, nop 1 ? pdmsb sx,dz 111110 ********** 10011101xx00zzzz sx ->dz normalization count shift value 1 * pdmsb sy,dz 111110 ********** 1011110100yyzzzz sy ->dz normalization count shift value 1 * dct pdmsb sx,dz 111110 ********** 10011110xx00zzzz if dc=1, normalization count shift value sx ->dz if dc=0, nop 1 ? dct pdmsb sy,dz 111110 ********** 1011111000yyzzzz if dc=1, normalization count shift value sy ->dz if dc=0, nop 1 ? dcf pdmsb sx,dz 111110 ********** 10011111xx00zzzz if dc=0, normalization count shift value sx ->dz if dc=1, nop 1 ? dcf pdmsb sy,dz 111110 ********** 1011111100yyzzzz if dc=0, normalization count shift value sy ->dz if dc=1, nop 1 ?
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 147 of 950 rej09b0079-0200 instruction instruction code operation execution states dc pinc sx,dz 111110 ********** 10011001xx00zzzz msw of sx + 1 ->dz 1 * pinc sy,dz 111110 ********** 1011100100yyzzzz msw of sy + 1 ->dz 1 * dct pinc sx,dz 111110 ********** 10011010xx00zzzz if dc=1, msw of sx + 1 ->dz if dc=0, nop 1 ? dct pinc sy,dz 111110 ********** 1011101000yyzzzz if dc=1, msw of sy + 1 ->dz if dc=0, nop 1 ? dcf pinc sx,dz 111110 ********** 10011011xx00zzzz if dc=0, msw of sx + 1 ->dz if dc=1, nop 1 ? dcf pinc sy,dz 111110 ********** 1011101100yyzzzz if dc=0, msw of sy+ 1 ->dz if dc=1, nop 1 ? pneg sx,dz 111110 ********** 11001001xx00zzzz 0-sx ->dz 1 * pneg sy,dz 111110 ********** 1110100100yyzzzz 0-sy ->dz 1 * dct pneg sx,dz 111110 ********** 11001010xx00zzzz if dc=1, 0-sx ->dz if dc=0, nop 1 ? dct pneg sy,dz 111110 ********** 1110101000yyzzzz if dc=1, 0-sy ->dz if dc=0, nop 1 ? dcf pneg sx,dz 111110 ********** 11001011xx00zzzz if dc=0, 0-sx ->dz if dc=1, nop 1 ? dcf pneg sy,dz 111110 ********** 1110101100yyzzzz if dc=0, 0-sy ->dz if dc=1, nop 1 ? por sx,sy,dz 111110 ********** 10110101xxyyzzzz sx | sy ->dz 1 * dct por sx,sy,dz 111110 ********** 10110110xxyyzzzz if dc=1, sx | sy ->dz if dc=0, nop 1 ? dcf por sx,sy,dz 111110 ********** 10110111xxyyzzzz if dc=0, sx | sy ->dz if dc=1, nop 1 ?
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 148 of 950 rej09b0079-0200 instruction instruction code operation execution states dc pand sx,sy,dz 111110 ********** 10010101xxyyzzzz sx & sy ->dz 1 * dct pand sx,sy,dz 111110 ********** 10010110xxyyzzzz if dc=1, sx & sy ->dz if dc=0, nop 1 ? dcf pand sx,sy,dz 111110 ********** 10010111xxyyzzzz if dc=0, sx & sy ->dz if dc=1, nop 1 ? pxor sx,sy,dz 111110 ********** 10100101xxyyzzzz sx ^ sy ->dz 1 * dct pxor sx,sy,dz 111110 ********** 10100110xxyyzzzz if dc=1, sx ^ sy ->dz if dc=0, nop 1 ? dcf pxor sx,sy,dz 111110 ********** 10100111xxyyzzzz if dc=0, sx ^ sy ->dz if dc=1, nop 1 ? pdec sx,dz 111110 ********** 10001001xx00zzzz sx [39:16]-1 ->dz 1 * dct pdec sx,dz 111110 ********** 10001010xx00zzzz if dc=1, sx [39:16]-1 ->dz if dc=0, nop 1 ? dcf pdec sx,dz 111110 ********** 10001011xx00zzzz if dc=0, sx [39:16]-1 ->dz if dc=1, nop 1 ? pdec sy,dz 111110 ********** 1010100100yyzzzz sy [31:16]-1 ->dz 1 * dct pdec sy,dz 111110 ********** 1010101000yyzzzz if dc=1, sy [31:16]-1 ->dz if dc=0, nop 1 ? dcf pdec sy,dz 111110 ********** 1010101100yyzzzz if dc=0, sy [31:16]-1 ->dz if dc=1, nop 1 ? pclr dz 111110 ********** 100011010000zzzz h'00000000 ->dz 1 * dct pclr dz 111110 ********** 100011100000zzzz if dc=1, h'00000000 ->dz if dc=0, nop 1 ? dcf pclr dz 111110 ********** 100011110000zzzz if dc=0, h'00000000 ->dz if dc=1, nop 1 ?
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 149 of 950 rej09b0079-0200 instruction instruction code operation execution states dc psha #imm,dz 111110 ********** 00010iiiiiiizzzz if imm>=0, dz<dz (arithmetic shift) if imm<0, dz>>imm ->dz 1 * pshl #imm,dz 111110 ********** 00000iiiiiiizzzz if imm>=0, dz<dz (logical shift) if imm<0, dz>>imm ->dz 1 * psts mach,dz 111110 ********** 110011010000zzzz mach ->dz 1 ? dct psts mach,dz 111110 ********** 110011100000zzzz if dc=1, mach ->dz 1 ? dcf psts mach,dz 111110 ********** 110011110000zzzz if dc=0, mach ->dz 1 ? psts macl,dz 111110 ********** 110111010000zzzz macl ->dz 1 ? dct psts macl,dz 111110 ********** 110111100000zzzz if dc=1, macl ->dz 1 ? dcf psts macl,dz 111110 ********** 110111110000zzzz if dc=0, macl ->dz 1 ? plds dz,mach 111110 ********** 111011010000zzzz dz ->mach 1 ? dct plds dz,mach 111110 ********** 111011100000zzzz if dc=1, dz ->mach 1 ? dcf plds dz,mach 111110 ********** 111011110000zzzz if dc=0, dz ->mach 1 ? plds dz,macl 111110 ********** 111111010000zzzz dz ->macl 1 ? dct plds dz,macl 111110 ********** 111111100000zzzz if dc=1, dz ->macl 1 ? dcf plds dz,macl 111110 ********** 111111110000zzzz if dc=0, dz ->macl 1 ? paddc sx,sy,dz 111110 ********** 10110000xxyyzzzz sx + sy + dc ->dz carry ->dc 1 carry
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 150 of 950 rej09b0079-0200 instruction instruction code operation execution states dc psubc sx,sy, dz 111110 ********** 10100000xxyyzzzz sx-sy-dc ->dz borrow ->dc 1 borrow pcmp sx,sy 111110 ********** 10000100xxyy0000 sx-sy ->dc update 1 * pabs sx,dz 111110 ********** 10001000xx00zzzz if sx<0, 0-sx ->dz if sx>=0, sx->dz 1 * pabs sy,dz 111110 ********** 1010100000yyzzzz if sy<0, 0-sy ->dz if sy>=0, sy ->dz 1 * prnd sx,dz 111110 ********** 10011000xx00zzzz sx + h'00008000 ->dz h'0000 ->lsw of dz 1 * prnd sy,dz 111110 ********** 1011100000yyzzzz sy + h'00008000 ->dz h'0000 ->lsw of dz 1 * note: * see table 3.19.
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 151 of 950 rej09b0079-0200 3.6.5 operation code map in dsp mode table 3.40 shows the operation code map including an instruction codes extended in the dsp mode. table 3.40 operation code map instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0000 rn fx 0000 0000 rn fx 0001 0000 rn 00md 0010 stc sr, rn stc gbr, rn stc vbr, rn stc ssr, rn 0000 rn 01md 0010 stc spc, rn stc mod, rn stc rs, rn stc re, rn 0000 rn 10md 0010 stc r0_bank, rn stc r1_bank, rn stc r2_bank, rn stc r3_bank, rn 0000 rn 11md 0010 stc r4_bank, rn stc r5_bank, rn stc r6_bank, rn stc r7_bank, rn 0000 rm 00md 0011 bsrf rm braf rm 0000 rm 10md 0011 pref @rm 0000 rn rm 01md mov.b rm, @(r0, rn) mov.w rm, @(r0, rn) mov.l rm, @(r0, rn) mul.l rm, rn 0000 0000 00md 1000 clrt sett clrmac ldtlb 0000 0000 01md 1000 clrs sets 0000 0000 10md 1000 0000 0000 11md 1000 0000 0000 fx 1001 nop div0u 0000 0000 fx 1010 0000 0000 fx 1011 rts sleep rte 0000 rn fx 1000 0000 rn fx 1001 movt rn 0000 rn 00md 1010 sts mach, rn sts macl, rn sts pr, rn 0000 rn 01md 1010 sts dsr, rn sts a0, rn 0000 rn 10md 1010 sts x0, rn sts x1, rn sts y0, rn sts y1, rn 0000 rn fx 1011
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 152 of 950 rej09b0079-0200 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0000 rn rm 11md mov. b @(r0, rm), rn mov.w @(r0, rm), rn mov.l @(r0, rm), rn mac.l @rm+,@rn+ 0001 rn rm disp mov.l rm, @(disp:4, rn) 0010 rn rm 00md mov.b rm, @rn mo v.w rm, @rn mov.l rm, @rn 0010 rn rm 01md mov.b rm, @ ? rn mov.w rm, @ ? rn mov.l rm, @ ? rn div0s rm, rn 0010 rn rm 10md tst rm, rn and rm, rn xor rm, rn or rm, rn 0010 rn rm 11md cmp/str rm, rn xtrct rm , rn mulu.w rm, rn mulsw rm, rn 0011 rn rm 00md cmp/eq rm, rn cm p/hs rm, rn cmp/ge rm, rn 0011 rn rm 01md div1 rm, rn dmulu.l rm,rn cmp/hi rm, rn cmp/gt rm, rn 0011 rn rm 10md sub rm, rn subc rm, rn subv rm, rn 0011 rn rm 11md add rm, rn dmuls.l rm,rn addc rm, rn addv rm, rn 0100 rn fx 0000 shll rn dt rn shal rn 0100 rn fx 0001 shlr rn cm p/pz rn shar rn 0100 rn fx 0010 sts.l mach, @ ? rn sts.l macl, @ ? rn sts.l pr, @ ? rn 0100 rn 00md 0011 stc.l sr, @ ? rn stc.l gbr, @ ? rn stc.l vbr, @ ? rn stc.l ssr, @ ? rn 0100 rn 01md 0011 stc.l spc, @ ? rn stc.l mod, @ ? rn stc.l rs, @ ? rn stc.l re, @ ? rn 0100 rn 10md 0011 stc.l r0_bank, @ ? rn stc.l r1_bank, @ ? rn stc.l r2_bank, @ ? rn stc.l r3_bank, @ ? rn 0100 rn 11md 0011 stc.l r4_bank, @ ? rn stc.l r5_bank, @ ? rn stc.l r6_bank, @ ? rn stc.l r7_bank, @ ? rn 0100 rn fx 0100 rotl rn setrc rn rotcl rn 0100 rn fx 0101 rotr rn cmp/pl rn rotcr rn 0100 rm 00md 0110 lds.l @rm+, mach lds.l @rm+, macl lds.l @rm+, pr 0100 rm 01md 0110 lds.l @rm+, dsr lds.l @rm+, a0 0100 rm 10md 0110 lds.l @rm+, x0 lds.l @rm+, x1 lds.l @rm+, y0 lds.l @rm+, y1
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 153 of 950 rej09b0079-0200 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0100 rm 00md 0111 ldc.l @rm+, sr ldc.l @rm+ , gbr ldc.l @rm+, vbr ldc.l @rm+, ssr 0100 rm 01md 0111 ldc.l @rm+, spc ldc.l @rm+, mod ldc.l @rm+, rs ldc.l @rm+, re 0100 rm 10md 0111 ldc.l @rm+, r0_bank ldc.l @rm+, r1_bank ldc.l @rm+, r2_bank ldc.l @rm+, r3_bank 0100 rm 11md 0111 ldc.l @rm+, r4_bank ldc.l @rm+, r5_bank ldc.l @rm+, r6_bank ldc.l @rm+, r7_bank 0100 rn fx 1000 shll2 rn shll8 rn shll16 rn 0100 rn fx 1001 shlr2 rn sh lr8 rn shlr16 rn 0100 rm 00md 1010 lds rm, mach lds rm, macl lds rm, pr 0100 rm 01md 1010 lds rm, dsr lds rm, a0 0100 rm 10md 1010 lds rm, x0 lds rm, x1 lds rm, y0 lds rm, y1 0100 rm/ rn fx 1011 jsr @rm tas.b @rn jmp @rm 0100 rn rm 1100 shad rm, rn 0100 rn rm 1101 shld rm, rn 0100 rm 00md 1110 ldc rm, sr ldc rm , gbr ldc rm, vbr ldc rm, ssr 0100 rm 01md 1110 ldc rm, spc ldc rm, mod ldc rm, rs ldc rm, re 0100 rm 10md 1110 ldc rm, r0_bank ldc rm, r 1_bank ldc rm, r2_bank ldc rm, r3_bank 0100 rm 11md 1110 ldc rm, r4_bank ldc rm, r 5_bank ldc rm, r6_bank ldc rm, r7_bank 0100 rn rm 1111 mac.w @rm+, rn+ 0101 rn rm disp mov.l @(disp:4, rm), rn 0110 rn rm 00md mov.b @rm, rn mov.w @r m, rn mov.l @rm, rn mov rm, rn 0110 rn rm 01md mov.b @rm+, rn mov.w @r m+, rn mov.l @rm+, rn not rm, rn 0110 rn rm 10md swap.b rm, rn swap.w rm, rn negc rm, rn neg rm, rn 0110 rn rm 11md extu.b rm, rn extu.w rm , rn exts.b rm, rn exts.w rm, rn 0111 rn imm add #imm : 8, rn rn disp 1000 00md imm mov.b r0, @(disp: 4, rn) mov.w r0, @(disp: 4, rn) setrc #imm
section 3 dsp operating unit rev. 2.00 dec. 07, 2005 page 154 of 950 rej09b0079-0200 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 1000 01md rm disp mov.b @(disp:4, rm), r0 mov.w @(disp: 4, rm), r0 1000 10md imm/disp cmp/eq #imm:8, r0 bt disp: 8 bf disp: 8 1000 11md imm/disp ldrs @(disp:8,pc) bt/s disp: 8 ldre @(disp:8,pc) bf/s disp: 8 1001 rn disp mov.w @(disp : 8, pc), rn 1010 disp bra disp : 12 1011 disp bsr disp: 12 1100 00md imm/disp mov.b r0, @(disp: 8, gbr) mov.w r0, @(disp: 8, gbr) mov.l r0, @(disp: 8, gbr) trapa #imm: 8 1100 01md disp mov.b @(disp: 8, gbr), r0 mov.w @(disp: 8, gbr), r0 mov.l @(disp: 8, gbr), r0 mova @(disp: 8, pc), r0 1100 10md imm tst #imm: 8, r0 and #imm: 8, r0 xor #imm: 8, r0 or #imm: 8, r0 1100 11md imm tst.b #imm: 8, @(r0, gbr) and.b #imm: 8, @(r0, gbr) xor.b #imm: 8, @(r0, gbr) or.b #imm: 8, @(r0, gbr) 1101 rn disp mov.l @(disp: 8, pc), rn 1110 rn imm mov #imm:8, rn 1111 00 ** ******** movx.w, movy.w double data transfer instruction 1111 01 ** ******** movs.w, movs.l single data transfer instruction 1111 10 ** ******** movx.w, movy.w double data transfer instruct ion, with dsp parallel operation instruction (32-bit instruction ) 1111 11 ** ******** notes: 1. for details, refer to the sh-3/sh-3e/sh3-dsp programming manual. 2. instructions in the hatched areas are dsp extended instructions. these instructions can be executed only when the dsp bit of the sr register is set to 1.
section 4 exception handling rev. 2.00 dec. 07, 2005 page 155 of 950 rej09b0079-0200 section 4 exception handling exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. for example, if an attempt is made to execute an undefined instruction code or an instruction protected by the cpu processing mode, a control function may be required to return to the source program by executing the appropriate opera tion or to report an abnormality and carry out end processing. in additio n, a function to control processing requested by lsi on-chip modules or an lsi external module to the cpu may also be required. transferring control to a user-defined exception processing routine and executing the process to support the above functions are called exception handling. this lsi has two types of exceptions: general exceptions and interrupts. the user can execute the required processing by assigning exception handling routines corresponding to the required exception processing and then return to the source program. a reset input can terminate the normal program execution and pass control to the reset vector after register initialization. this reset operation can also be regarded as an exception handling. this section describes an overview of the exception handling operation. here, general exceptions and interrupts are referred to as exception handling. for interrupts, this section describes only the process executed for interrupt requests. for details on how to generate an interrupt request, refer to section 8, interrupt controller (intc). 4.1 register descriptions there are five registers for exception handling. a register with an undefined initial value should be initialized by the software. re fer to section 24, list of regi sters, for the addresses and access sizes of these registers. ? trapa exception register (tra) ? exception event register (expevt) ? interrupt event register (intevt) ? interrupt event register 2 (intevt2) ? exception address register (tea)
section 4 exception handling rev. 2.00 dec. 07, 2005 page 156 of 950 rej09b0079-0200 figure 4.1 shows the bit configuration of each register. 31 tra expevt intevt intevt2 tra expevt intevt intevt2 tea tea 10 9 2 1 0 31 12 11 0 0 0 0 0 0 31 12 11 0 31 12 11 0 31 0 figure 4.1 register bit configuration 4.1.1 trapa exception register (tra) tra is assigned to address h ffffffd0 and consists of the 8-bi t immediate data (imm) of the trapa instruction. tra is automatically specified by the hardware when the trapa instruction is executed. only bits 9 to 2 of the tra can be re-written using the software. bit bit name initial value r/w description 31 to 10 ? ? r reserved these bits are always read as 0. the write value should always be 0. 9 to 2 tra ? r/w 8-bit immediate data 1, 0 ? ? r reserved these bits are always read as 0. the write value should always be 0.
section 4 exception handling rev. 2.00 dec. 07, 2005 page 157 of 950 rej09b0079-0200 4.1.2 exception event register (expevt) expevt is assigned to address h ffffffd4 and consists of a 12-bit exception code. exception codes to be specified in expevt are those for resets and general exceptions. these exception codes are automatically specified by the hardware when an exception occurs. only bits 11 to 0 of expevt can be re-written using the software. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 expevt * r/w 12-bit exception code note: * initialized to h 000 at power-on reset and h 020 at manual reset. 4.1.3 interrupt even t register (intevt) intevt is assigned to address h ffffffd8 and consists of the ex ception code or the interrupt priority code. whether the occurr ence of an interrupt sets the exception code or the interrupt priority code depends on the interrupt sources. (see section 8.3.5, interrupt exception handling and priority, for details.) these exception codes and interrupt priority codes are automatically specified by the hardware when an exception occu rs. only bits 11 to 0 in intevt can be re- written using the software. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 intevt ? r/w 12-bit exception code
section 4 exception handling rev. 2.00 dec. 07, 2005 page 158 of 950 rej09b0079-0200 4.1.4 interrupt event register 2 (intevt2) intevt2 is assigned to address h a4000000 and consists of the exception code. exception codes to be specified in intevt2 are those for in terrupt requests. these exception codes are automatically specified by the hardware when an exception occurs. intevt2 cannot be modified using the software. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 intevt2 ? r 12-bit exception code 4.1.5 exception address register (tea) tea is assigned to address h fffffffc and the logical address fo r an exception occurrence is stored in this register when an exception rela ted to memory accesses occurs. tea can be modified using the software. bit bit name initial value r/w description 31 to 0 tea 0 r/w logical address for exception occurrence
section 4 exception handling rev. 2.00 dec. 07, 2005 page 159 of 950 rej09b0079-0200 4.2 exception handling function 4.2.1 exception handling flow in exception handling, the contents of the program counter (pc) and status register (sr) are saved in the saved program counter (spc) and saved status register (ssr), respectively, and execution of the exception handler is invoked from a vector address. by executing the return from exception handler (rte) in the exception handler routine, it restores the contents of pc and sr, and returns to the processor state at the poi nt of interruption and the addre ss where the exception occurred. a basic exception handling sequence consists of the following operations. if an exception occurs and the cpu accepts it, operations 1 to 8 are executed. 1. the contents of pc is saved in spc. 2. the contents of sr is saved in ssr. 3. the block (bl) bit in sr is set to 1, masking any subsequent exceptions. 4. the mode (md) bit in sr is set to 1 to place the privileged mode. 5. the register bank (rb) bit in sr is set to 1. 6. an exception code identifying the exception event is written to bits 11?0 of the exception event (expevt) or interrupt even t (intevt or intevt2) register. 7. if a trapa instruction is executed, an 8-bit immediate data specified by the trapa instruction is set to tra. for an exception related to memory accesses, the logic address where the exception occurred is written to tea. * 1 8. instruction execution jumps to the designated exception vector address to invoke the handler routine. the above operations from 1 to 8 are executed in sequence. during these operations, no other exceptions may be accepted unless multiple exception accepta nce is enabled. in an exception handling routine for a general ex ception, the appropriate exception handling must be executed based on an exception source determined by the expevp. in an interrupt exception handling routine, the appropriate exception handlin g must be executed based on an exception source determined by the intevt or intevt2. after the exception handling routine has been completed, program execution can be resumed by executing an rte instruction. the rte instruction causes the following operations to be executed. 1. the contents of the ssr are restored into the sr to return to the pro cessing state in effect before the exception handling took place. 2. a delay slot instruction of the rte instruction is executed.* 2
section 4 exception handling rev. 2.00 dec. 07, 2005 page 160 of 950 rej09b0079-0200 3. control is passed to the address stored in the spc. the above operations from 1 to 3 are executed in sequence. during these operations, no other exceptions may be accepted. by changing the spc and ssr before executing the rte instruction, a status different from that in effect before the exception handling can also be specified. notes: 1. the mmu registers are modi fied if an mmu exception occurs. 2. for details on the cpu processing mode in which rte delay slot instructions are executed, please refer to s ection 4.5, usage notes. 4.2.2 exception vector addresses a vector address for general exceptions is determined by adding a vector offset to a vector base address. the vector offset for general exce ptions other than the tlb error exception is h 00000100. the vector offset for interrupts is h 00000600. the vector base address is loaded into the vector base register (vbr) using the software. the vector base address should reside in the p1 or p2 fixed physical address space. 4.2.3 exception codes the exception codes are written to bits 11 to 0 in expevt (for reset or general exceptions) or intevt2 (for interrupt requests) to identify each sp ecific exception event. s ee section 8, interrupt controller (intc), for details on the exceptio n codes for interrupt requests. table 4.1 lists exception codes for resets and general exceptions. 4.2.4 exception request and bl bit (multiple exception prevention) the bl bit in sr is set to 1 when a reset or exce ption is accepted. while th e bl bit is set to 1, acceptance of general exceptions is restricted as de scribed below, making it possible to effectively prevent multiple exceptio ns from being accepted. if the bl bit is set to 1, an interrupt request is not accepted and is retained. the interrupt request is accepted when the bl bit is clear ed to 0. if the cpu is in low power consum ption mode, an interrupt is accepted even if the bl bit is set to 1 and the cpu returns from the low power consumption mode. a dma error is not accepted and is retained if the bl bit is set to 1 and accepted when the bl bit is cleared to 0. user break requests generated while the bl bit is set are ignored and are not retained. accordingly, user breaks are not accep ted even if the bl bit is cleared to 0.
section 4 exception handling rev. 2.00 dec. 07, 2005 page 161 of 950 rej09b0079-0200 if a general exception other than a dma address error or user break occurs while the bl bit is set to 1, the cpu enters a state similar to that in e ffect immediately after a re set, and passes control to the reset vector (h a0000000) (multiple exception). in this case, unlike a normal reset, modules other than the cpu are not initialized, the contents of expevt, spc, and ssr are undefined, and this status is not detected by an external device. to enable acceptance of multiple exceptions, the contents of spc and ssr must be saved while the bl bit is set to 1 after an exception has been accept ed, and then the bl b it must be cleared to 0. before restoring the spc and ssr, the bl bit must be set to 1. 4.2.5 exception source accepta nce timing and priority exception request of instruction synchronou s type and instruction asynchronous type: resets and interrupts are requested asynchronously regardless of the program flow. in general exceptions, a dma address error and a user break under the specific condition are also requested asynchronously. the user cannot expect on wh ich instruction an excep tion is requested. for general exceptions other than a dma address error and a user break under a specific condition, each general exception corresponds to a specific instruction. re-execution type and processi ng-completion type exceptions: all exceptions are classified into two types: a re-execution type and a processing-completion type. if a re-execution type exception is accepted, the curr ent instruction exec uted when the exception is accepted is terminated and the instruction address is saved to the spc. after returning from the exception processing, program execution resu mes from the instruction where the exception was accepted. in a processing-completion type exception, the curr ent instruction executed when the exception is accepted is completed, the next in struction address is saved to the spc, and then the exception processing is executed. during a delayed branch instruction and delay slot, the following operations are executed. a re- execution type exception detected in a delay slot is accepted before executing the delayed branch instruction. a processing-completion type exception detected in a delayed branch instruction or a delay slot is accepted when the delayed branch in struction has been execute d. in this case, the acceptance of delayed branch instru ction or a delay slot precedes the execution of the branch destination instruction. in the above description, a delay slot indicates an instruction following an unconditional delayed branch instruction or an instruction following a conditional delayed branch instruction whose branch condition is satisfied. if a branch does not occur in a conditional delayed branch, the normal processing is executed.
section 4 exception handling rev. 2.00 dec. 07, 2005 page 162 of 950 rej09b0079-0200 acceptance priority and test priority: acceptance priorities are de termined for all exception requests. the priority of resets, general exceptions , and interrupts are determined in this order: a reset is always accepted regardless of the cpu stat us. interrupts are accepted only when resets or general exceptions are not requested. if multiple general exceptions occur simultaneously in the same instruction, the priority is determined as follows. 1. a processing-completion type exception generated at the previous instruction* 2. a user break before instruction execution (re-execution type) 3. an exception related to an instruction fetch (cpu address error and mmu related exceptions: re-execution type) 4. an exception caused by an instruction decode (general illegal instruct ion exceptions and slot illegal instruction exceptions: re-execution ty pe, unconditional trap: processing-completion type) 5. an exception related to data access (cpu address error and mmu re lated exceptions: re- execution type) 6. unconditional trap (processing-completion type) 7. a user break other than one before instruction execution (processing-completion type) 8. dma address error (processing-completion type) note: * if a processing-completion type exceptio n is accepted at an in struction, exception processing starts before the next instruction is executed. this exception processing executed before an exception generated at the next instruction is detected. only one exception is accepted at a time. accepting multiple exceptions sequenti ally results in all exception requests being processed.
section 4 exception handling rev. 2.00 dec. 07, 2005 page 163 of 950 rej09b0079-0200 table 4.1 exception event vectors exception type current instruction exception event priority * 1 exception order process at bl=1 vector code vector offset power-on reset 1 ? reset h'000 ? manual reset 1 ? reset h'020 ? reset (asynchronous) aborted h-udi reset 1 1 reset h'000 ? user break(before instruction execution) 2 0 ignored h'1e0 h'00000100 re-executed cpu address error (instruction access) * 4 2 1 reset h'0e0 h'00000100 * 5 tlb miss (instruction access) * 4 2 1-1 reset h'040 h'00000400 tlb invalid (instruction access) * 4 2 1-2 reset h'040 h'00000100 tlb protection violation (instruction access) * 4 2 1-3 reset h'0a0 h'00000100 illegal general instruction exception 2 2 reset h'180 h'00000100 illegal slot instruction exception 2 2 reset h'1a0 h'00000100 completed unconditional trap (trapa instruction) 2 4 reset h'160 h'00000100 re-executed cpu address error (data read/write) * 4 2 3 reset h'0e0/ h?100 h'00000100 * 5 tlb miss (data read/write) * 4 2 3-1 reset h'040/ h?060 h'00000400 tlb invalid (data read/write) * 4 2 3-2 reset h'040/ h?060 h'00000100 general exception events (synchronous) tlb protection violation (data read/write) * 4 2 3-3 reset h'0a0/ h?0c0 h'00000100 initial page write (data write) * 4 2 3-4 reset h'080 h'00000100 completed user breakpoint (after instruction execution, address) 2 5 ignored h'1e0 h'00000100
section 4 exception handling rev. 2.00 dec. 07, 2005 page 164 of 950 rej09b0079-0200 exception type current instruction exception event priority * 1 exception order process at bl=1 vector code vector offset user breakpoint (data break, i-bus break) 2 5 ignored h'1e0 h'00000100 general exception events (asynchronous) completed dma address error 2 6 retained h'5c0 h'00000100 general interrupt requests (asynchronous) completed interrupt requests 3 ? * 2 retained ? * 3 h'00000600 notes: 1. priorities are indicated from high to low, 1 being the highest and 3 the lowest. a reset has the highest priority. an interrupt is accepted only when general exceptions are not requested. 2. for details on priorities in multiple in terrupt sources, refer to section 8, interrupt controller (intc). 3. if an interrupt is accepted, the interrupt source register (expevt) is not changed. the interrupt source code is specified in interrupt source register 2 (expevt2). for details, refer to section 8, inte rrupt controller (intc). 4. if one of these exceptions occurs in a specif ic part of the repeat loop, a specific code and vector offset are specified. 5. these exception codes are valid when the mmu is used.
section 4 exception handling rev. 2.00 dec. 07, 2005 page 165 of 950 rej09b0079-0200 4.3 individual exception operations this section describes the conditions for specific exception handling, and the processor operations. resets and general exceptions are described in particular. for details on interrupt operations, refer to section 8, interrupt controller (intc). 4.3.1 resets power-on reset: ? conditions power-on reset is request ? operations set expevt to h'000, initialize the cpu and on-chip peripheral modules, and branch to the reset vector h a0000000. for details, refer to the register descriptions in the relevant sections. be sure to perform power-on reset at the time of a power supply injection. manual reset: ? conditions manual reset is request ? operations set expevt to h'020, initialize the cpu and on-chip peripheral modules, and branch to the reset vector h a0000000. for details, refer to the register descriptions in the relevant sections. h-udi reset: ? conditions an h-udi reset command is input (see section 23.4.4 h-udi reset.) ? operations expevt is set to h'000, vector base register (vbr) and status register (sr) are initialized, and branched to the reset vector (h'a0000000). vbr is cleared to h'00000000 by initialization. in sr, the md, rb, and bl bits are set to 1, the dsp bit is cleared to 0, and the interrupt mask bits (i3 to i0) are set to b'1111. then, the cpu and on-chip peripheral modules are initialized. for details, see the regi ster description in each section.
section 4 exception handling rev. 2.00 dec. 07, 2005 page 166 of 950 rej09b0079-0200 4.3.2 general exceptions cpu address error: ? conditions ? instruction is fetched from odd address (4n + 1, 4n + 3) ? word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3) ? longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) ? the area ranging from h'8000000 0 to h'ffffffff in logical space is accessed in user mode ? types instruction synchronous, re-execution type ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an ex ception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code an exception occurr ed during read: h 0e0 an exception occurred during write: h 100 ? remarks the logical address (32 bits) that caused the exception is set in tea. illegal general instruction exception: ? conditions ? when undefined code not in a delay slot is decoded delayed branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s note: for details on undefined code, refer to table 2.12 in section 2, operation code map. when an undefined code other than h fc00 to h ffff is decoded, operation cannot be guaranteed. ? when a privileged instruction not in a delay slot is decoded in user mode privileged instructions: ld c, stc, rte, ldtlb, sleep; instructions that access gbr with ldc/stc are not privileged instructions.
section 4 exception handling rev. 2.00 dec. 07, 2005 page 167 of 950 rej09b0079-0200 ? types instruction synchronous, re-execution type ? save address an instruction address wh ere an exception occurs ? exception code h 180 ? remarks none illegal slot instruction: ? conditions ? when undefined code in a delay slot is decoded delayed branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s ? when a privileged instruction in a delay slot is decoded in user mode privileged instructions: ldc, stc, rte, ldtlb, sleep; instructions that access gbr with ldc/stc are not privileged instructions. ? when an instruction that rewrites pc in a delay slot is decoded instructions that rewrite pc: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt, bf, bt/s, bf/s, trapa, ldc rm, sr, ldc.l @rm+, sr ? types instruction synchronous, re-execution type ? save address a delayed branch instruction address ? exception code h 1a0 ? remarks none
section 4 exception handling rev. 2.00 dec. 07, 2005 page 168 of 950 rej09b0079-0200 unconditional trap: ? conditions trapa instruction executed ? types instruction synchronous, processing-completion type ? save address an address of an instruction following trapa ? exception code h 160 ? remarks the exception is a processing-completion type , so pc of the instruction after the trapa instruction is saved to spc. the 8-bit immediate value in the trapa instruction is quadrupled and set in tra[9:2]. user break point trap: ? conditions when a break condition set in the us er break controller is satisfied ? types break (l bus) before instru ction execution: instruction synchronous, re-execution type operand break (l bus): instruction synchronous, processing-completion type data break (l bus): instruction asynchronous, processing-completion type i bus break: instruction asynchronous, processing-completion type ? save address re-execution type: an address of the instruction where a break occurs (a delayed branch instruction address if an instruc tion is assigned to a delay slot) processing-completion type: an address of the instruction following the instruction where a break occurs (a delayed branch instruction destination address if an instruction is assigned to a delay slot) ? exception code h 1e0 ? remarks for details on the user break controller, refer to section 9, user break controller.
section 4 exception handling rev. 2.00 dec. 07, 2005 page 169 of 950 rej09b0079-0200 dma address error: ? conditions ? word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) ? longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) ? types instruction asynchronous, processing-completion type ? save address an address of the instruction following the inst ruction where an exception occurs (a delayed branch instruction destination address if an instruction is assigned to a delay slot) ? exception code h 5c0 ? remarks an exception occurs when a dma transfer is executed while an illegal instruction address described above is specified in the dmac. since the dma transfer is performed asynchronously with the cpu instruction op eration, an exception is also requested asynchronously with the instruction execution. for details on the dmac, refer to section 13, direct memory acce ss controller (dmac). 4.3.3 general exceptio ns (mmu exceptions) when the address translation unit of the memory management unit (mmu) is valid, mmu exceptions are checked after a cpu address er ror has been checked. four types of mmu exceptions are defined: tlb miss exception, tlb invalid exception, tlb protection exception, initial page write exception. these exceptions are checked in this order. a vector offset for a tlb miss exception is defined as h 00000400 to simplify exception source determination. for details on mmu exception opera tions, refer to section 5, memory management unit (mmu). tlb miss exception: ? conditions comparison of tlb addresses shows no address match. ? types instruction synchronous, re-execution type
section 4 exception handling rev. 2.00 dec. 07, 2005 page 170 of 950 rej09b0079-0200 ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an ex ception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code an exception occurr ed during read: h 040 an exception occurred during write: h 060 ? remarks the logical address (32 bits) that caused the ex ception is set in tea and the mmu registers are updated. the vector address of the tlb miss exception becomes vb r + h'0400. to speed up tlb miss processing, the offset differs from other exceptions. tlb invalid exception: ? conditions comparison of tlb addresses shows address match but v = 0. ? types instruction synchronous, re-execution type ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an ex ception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code an exception occurr ed during read: h 040 an exception occurred during write: h 060 ? remarks the logical address (32 bits) that caused the ex ception is set in tea and the mmu registers are updated. tlb protection exception: ? conditions when a hit access violates the tlb protection information (pr bits). ? types instruction synchronous, re-execution type
section 4 exception handling rev. 2.00 dec. 07, 2005 page 171 of 950 rej09b0079-0200 ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an ex ception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code an exception occurr ed during read: h 0a0 an exception occurred during write: h 0c0 ? remarks the logical address (32 bits) that caused the ex ception is set in tea and the mmu registers are updated. initial page write exception: ? conditions a hit occurred to the tlb for a data write access, but d = 0. ? types instruction synchronous, re-execution type ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an ex ception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code h 080 ? remarks the logical address (32 bits) that caused the ex ception is set in tea and the mmu registers are updated.
section 4 exception handling rev. 2.00 dec. 07, 2005 page 172 of 950 rej09b0079-0200 4.4 exception processing while dsp extension function is valid when the dsp extension function is valid (the dsp bit of sr is set to 1), some exception processing acceptance conditions or exception processing may be changed. 4.4.1 illegal instruction exception a nd slot illegal instruction exception in the dsp mode, a dsp extension instruction can be executed. if a dsp ex tension instruction is executed when the dsp bit of sr is cleared to 0 (in a mode other than the dsp mode), an illegal instruction exception occurs. in the dsp mode, stc and ldc instructions for th e sr register can be executed even in user mode. (note, however, that only the rc[11:0], dmx, dmy, and rf[1:0] bits in the dsp extension bits can be changed.) 4.4.2 cpu address error in the dsp mode, a part of the space p2 (uxy area: h a5000000 to h a5ffffff) can be accessed in user mode and no cpu address error will occur even if the area is accessed. 4.4.3 exception in repeat control period if an exception is requested or an exception is accepted during repeat control, the exception may not be accepted correctly or a program executio n may not be returned correctly from exception processing that is different fr om the normal state. these rest rictions may occur from repeat detection instruction to repeat end instruction while the repeat counter is 1 or more. in this section, this period is called the repeat control period. the following shows program exampl es where the number of instructions in th e repeat loop are 4 or more, 3, 2, and 1, respectively. in this section, a repeat detection instruction and its instruction address are described as rptdtct. the first, seco nd, and third instructions following the repeat detection instruction are described as rptdtct1, rptdtct2, and rptdtct3. in addition, [a], [b], [c1], and [c2] in the following examples indicat e instructions where a re striction occurs. table 4.2 summarizes the instruction positions and restriction types.
section 4 exception handling rev. 2.00 dec. 07, 2005 page 173 of 950 rej09b0079-0200 table 4.2 instruction positi ons and restriction types instruction position spc * 1 illegal instruction * 2 interrupt, break * 3 cpu address error * 4 [a] [b] retained [c1] added retained instruction/data [c2] illegal added retained instruction/data notes: 1. a specific address is specified in the spc if an exception oc curs while sr.rc[11:0] 2. 2. there are a greater number of instructions that can be illegal instructions while sr.rc[11:0] 1. 3. an interrupt, break or dma address e rror request is retain ed while sr.rc[11:0] 1. 4. a specific exception code is specified while sr.rc[11:0] 1. ? example 1: repeat loop consisting of four or greater instructions ldrs rptstart ; [a] ldrs rptdtct + 4 ; [a] setrc #4 ; [a] instr0 ; [a] rptstart: instr1 ; [a][repeat start instruction] ??? ; [a] ??? ; [a] rptdtct: rptdtct ; [b] a repeat detection instruction is an instruction three instructions before a repeat end instruction rptdtct1 ; [c1] rptdtct2 ; [c2] rptend: rptdtct3 ; [c2][repeat end instruction] instrnext ; [a]
section 4 exception handling rev. 2.00 dec. 07, 2005 page 174 of 950 rej09b0079-0200 ? example 2: repeat loop consisting of three instructions ldrs rptdtct + 4 ; [a] ldrs rptdtct + 4 ; [a] setrc #4 ; [a] rptdtct: rptdtct ; [b] a repeat detection instruction is an instruction prior to a repeat start instruction rptstart: rptdtct1 ; [c1][repeat start instruction] rptdtct2 ; [c2] rptend: rptdtct3 ; [c2][repeat end instruction] instrnext ; [a] ? example 3: repeat loop consisting of two instructions ldrs rptdtct + 6 ; [a] ldrs rptdtct + 4 ; [a] setrc #4 ; [a] rptdtct: rptdtct ; [b] a repeat detection instruction is an instruction prior to a repeat start instruction rptstart: rptdtct1 ; [c1][repeat start instruction] rptend: rptdtct2 ; [c2][repeat end instruction] instrnext ; [a]
section 4 exception handling rev. 2.00 dec. 07, 2005 page 175 of 950 rej09b0079-0200 ? example 4: repeat loop consisting of one instruction ldrs rptdtct + 8 ; [a] ldrs rptdtct + 4 ; [a] setrc #4 ; [a] rptdtct: rptdtct ; [b] a repeat detection instruction is an instruction prior to a repeat start instruction rptstart: rptend: rptdtct1 ; [c1][repeat start instruction]== [repeat end instruction] instrnext ; [a]
section 4 exception handling rev. 2.00 dec. 07, 2005 page 176 of 950 rej09b0079-0200 spc saved by exception in repeat control period: if an exception is accepted in the repeat control period while the repeat counter (rc[11:0]) in the sr register is two or greater, the program counter to be saved may not indicate the value to be returned correctly. to execute the repeat control after returning from an exception proce ssing, the return addr ess must indicate an instruction prior to a repeat de tection instruction. ac cordingly, if an exception is accepted in repeat control period, an exception other than re-execution type exception by a repeat detection instruction cannot return to the repeat control correctly. table 4.3 spc value when re-execution ty pe exception occurs in repeat control (rc[11:0] 2) number of instructions in repeat loop instruction where exception occurs 1 2 3 4 or greater rptdtct rptdtct rptd tct rptdtct rptdtct rptdtct1 rptdtct1 rptdtc t1 rptdtct1 rptdtct1 rptdtct2 ? rptdtct1 rptdtct1 rs-4 rptdtct3 ? ? rptdtct1 rs-2 note: the following labels are used here. rptdtct: repeat detection instruction address rptdtct1: an instruction address one instructi on following the repeat detection instruction rptdtct2: an instruction address two instruct ion following the repeat detection instruction rptdtct3: an instruction address three instruct ion following the repeat detection instruction rs: repeat start instruction address if a re-execution type exception is accepted at an instruction in the hatched areas above, a return address to be saved in the spc is incorre ct. if rc[11:0] is 1 or 0, a correct return address is saved in the spc. illegal instruction exception in repeat control period: if one of the following instructions is executed at the address following rptdtct1, a general illegal instruction exception occurs. for details on an address to be saved in the spc, refer to the description in section 4.4.3, spc saved by exception in repeat control period. ? branch instructions bra, bsr, bt, bf, bt/s, bf/s, bsrf, rts, braf, rte, jsr, jmp, trapa ? repeat control instructions setrc, ldrs, ldre ? load instructions for sr, rs, and re ldc rn, sr, ldc @rn+, sr, ldc rn, re, ld c @rn+, re, ldc rn,rs, ldc @rn+, rs
section 4 exception handling rev. 2.00 dec. 07, 2005 page 177 of 950 rej09b0079-0200 note: in a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. in a repeat loop consisting of four or more instructions, restrictions apply to only the three instructions that include a repeat end instruction. exception retained in repeat control period: in the repeat control period, an interrupt or some exception will be retained to pr event an exception acceptance at an instruction where returning from the exception cannot be performed correctly. for details, refer to repeat loop program examples 1 to 4. in the examples, exceptions genera ted at instructions indicated as [b], [c], [c1], or [c2], the following processing is executed. ? interrupt, dma address error an exception request is not accepted and retained at instructions [b] and [c]. if an instruction indicates as [a] is executed at the next time, an exception request is accepted.* as shown in program examples 1 to 4, any in terrupt or dma address error cannot be accepted in a repeat loop consisting of four instructions or less. note: * an interrupt request or a dma address error exception request is retained in the interrupt controller (intc) and the direct memory access controller (dmac) until the cpu can accept a request. ? user break before instruction execution a user break before instructio n execution is accepted at instruct ion [b], and an address of instruction [b] is saved in the spc. this exce ption cannot be accepted at instruction [c] but the exception request is retained until an instru ction [a] or [b] is executed at the next time. then, the exception request is accep ted before an instruction [a] or [b] is executed. in this case, an address of instruction [a] or [b] is saved in the spc. ? user break after instruction execution a user break after instruction execution cannot be accepted at instructions [b] and [c] but the exception request is retained until an instruction [a ] or [b] is executed at the next time. then, the exception request is accepted before an instruct ion [a] or [b] is executed. in this case, an address of instruction [a] or [b] is saved in the spc. table 4.4 exception acceptance in repeat loop exception type instruction [b] instruction [c] interrupt not accepted not accepted dma address error not accepted not accepted user break before instruction ex ecution accepted not accepted user break after instruction exec ution not accepted not accepted
section 4 exception handling rev. 2.00 dec. 07, 2005 page 178 of 950 rej09b0079-0200 cpu address error in repeat control period: if a cpu address error occurs in the repeat control period, the exception is accepted but an ex ception code (h'070) indicating the repeat loop period is specified in the expevt. if a cpu ad dress error occurs in in structions following a repeat detection instruction to re peat end instruction, an exceptio n code for instru ction access or data access is specified in the expevt. the spc is saved according to the description in section 4.4.3, spc saved by exception in repeat control period. after the cpu address error exceptio n processing, the repeat control cannot be returned correctly. to execute a repeat loop correctly, care must be taken not to generate a cpu address error in the repeat control period. note: in a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. in a repeat loop consisting of four or more instructions, restrictions apply to only the four instructions that include a repeat end instruction. the restric tion occurs when sr.rc[11:0] 1. table 4.5 instruction where a specific excepti on occurs when memory access exception occurs in repeat co ntrol (sr.rc[11:0] 1) number of instructions in repeat loop instruction where exception occurs 1 2 3 4 or greater rptdtct rptdtct1 instruction/data access instruction/data access instruction/data access instruction/data access rptdtct2 ? instruction/data access instruction/data access instruction/data access rptdtct3 ? ? instruction/data access instruction/data access note: the following labels are used here. rptdtct: repeat detection instruction rptdtct1: an instruction of one instructi on following the repeat detection instruction rptdtct2: an instruction of two instruction following the repeat detection instruction rptdtct3: an instruction of three instruction following t he repeat detection instruction
section 4 exception handling rev. 2.00 dec. 07, 2005 page 179 of 950 rej09b0079-0200 mmu exception in repeat control period: if an mmu exception occurs in the repeat control period, a specific exception code is generated as well as a cpu address error. for a tlb miss exception, tlb invalid exception, and initial page write exception, an exception code (h 070) is specified in the expevt. for a tlb prot ection exception, an exception code (h 0d0) is specified in the expevt. in a tlb miss exception, vector offset is specified as h 00000100. an instruction where an exception occurs and the spc value to be saved are the same as those for the cpu address error. after this exception processing, the repeat cont rol cannot be returned correctly. to execute a repeat loop correctly, care must be taken not to generate an mmu related exception in the repeat control period. note: in a repeat loop consisting of one to thre e instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. in a repeat loop consisting of four or more instructions, restrictions apply to only the four instructions that include a repeat end instruction. the restrict ion occurs when sr.rc[11:0] 1. 4.5 usage notes 1. an instruction assigned at a delay slot of the rte instruction is executed after the contents of the ssr is restored into the sr. an acceptance of an exception related to instruction access is determined according to the sr before rest ore. an acceptance of other exceptions is determined by processing mode of the sr after restore, and bl bit value. a processing- completion type exception is accep ted before an instruction at the rte branch destination address is executed. however, no te that the correct operation ca nnot be guaranteed if a re- execution type exception occurs. 2. in an instruction assigned at a delay slot of the rte instruction, a user break cannot be accepted. 3. if the md and bl bits of the sr register are changed by the ldc instruction, an exception is accepted according to the changed sr value fr om the next instruction.* a processing- completion type exception is accepted after the ne xt instruction is executed. an interrupt and dma address error in re-execution type exceptions are accepted before the next instruction is executed. note: * if an ldc instruction is executed for the sr, the following instru ctions are re-fetched and an instruction fetch exception is accept ed according to the modified sr value.
section 4 exception handling rev. 2.00 dec. 07, 2005 page 180 of 950 rej09b0079-0200
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 181 of 950 rej09b0079-0200 section 5 memory management unit (mmu) this lsi has an on-chip memory management unit (mmu) that supports a virtual memory system. the on-chip translation look-aside buffer (tlb ) caches information for user-created address translation tables located in external memory. it enables high-speed translation of virtual addresses into physical addresses. address translation uses the paging system and supports two page sizes (1 kbyte or 4 kbytes). the access rights to virtual addr ess space can be set for each of the privileged and user modes to provide memory protection. 5.1 role of mmu the mmu is a feature designed to make efficient use of physical memory. as shown in figure 5.1, if a process is smaller in size than the physical memory, the entire pro cess can be mapped onto physical memory. however, if the process increases in size to the ex tent that it no longer fits into physical memory, it becomes necessary to partiti on the process and to map those parts requiring execution onto memory as occasion demands (figure 5.1 (1)). having the process itself consider this mapping onto physical memory would impose a large burden on the process. to lighten this burden, the idea of virtual memory was born as a means of performing en bloc mapping onto physical memory (figure 5.1 (2)). in a virtual memory system, substantially more virtual memory than physical memory is provided, and the process is mapped onto this virtual memory. thus a process only has to consider operation in virtual memory. mapping from virtual memory to physical memory is handled by the mmu. the mmu is normally controlled by the operating system, switching physical memory to allow the virtual memory required by a process to be mapped onto physical memory in a smooth fashion. switching of physical memory is performed via secondary storage, etc. the virtual memory system that cam e into being in this way is particularly effective in a time- sharing system (tss) in which a number of processes are running simultaneously (figure 5.1 (3)). if processes running in a tss had to take mapping onto virtual memory into consideration while running, it would not be possible to increase efficiency. virtual memory is thus used to reduce this load on the individual processes and so improve efficiency (figure 5.1 (4)). in the virtual memory system, virtual memory is allocated to each process. the task of the mmu is to perform efficient mapping of these virtual memory areas onto physical memory. it also has a memory protection feature that prevents one proce ss from inadvertently accessing anot her process?s physical memory. when address translation from virtual memory to physical memory is performed using the mmu, it may occur that the relevant translation information is not recorded in the mmu, with the result that one process may inadvertently access the virtual memory allocated to another process. in this case, the mmu will generate an exception, change the physical memory mapping, and record the new address translation information.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 182 of 950 rej09b0079-0200 although the functions of the mmu could also be implemented by software alone, the need for translation to be performed by software each time a process accesses physical memory would result in poor efficiency. for this reason, a buffer for address translation (translation look-aside buffer: tlb) is provided in hardware to hold frequently used address translation information. the tlb can be described as a cach e for storing address translati on information. unlike cache memory, however, if address translation fails, that is, if an exception is generated, switching of address translation information is normally perf ormed by software. this makes it possible for memory management to be performed flexibly by software. the mmu has two methods of mapping from virtual memory to physical memory: a paging method using fixed-length address translation, and a segment method using variable-length address translation. with the paging method, the unit of translation is a fixed-size address space (usually of 1 to 64 kbytes) called a page. in the following text, the address space in virtual memory is referred to as virtual address space, and address space in physical me mory as physical memory space.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 183 of 950 rej09b0079-0200 process 1 physical memory physical memory process 1 mmu physical memory process 1 process 3 process 2 process 1 process 1 process 2 process 3 virtual memory mmu (1) (2) (3) (4) physical memory physical memory virtual memory figure 5.1 mmu functions 5.1.1 mmu of this lsi virtual address space: this lsi supports a 32-bit virtual ad dress space that enables access to a 4-gbyte address space. as shown in figures 5.2 and 5.3, the virtual address space is divided into several areas. in privileged mode, a 4-gbyte space comprising areas p0 to p4 are accessible. in user mode, a 2-gbyte space of u0 area is accessible, and a 16-mbyte space of uxy area is also accessible if the dsp bit of the sr register is set to 1. access to any area (excluding the u0 area and uxy area) in user mode w ill result in an address error. if the mmu is enabled by setting the at bit of the mmucr register to 1, p0, p3, and u0 areas can be used as any physical addr ess area in 1- or 4-kbyte page units. by using an 8-bit address space identifier, p0, p2, and u0 ar eas can be increased to up to 256 areas. mapping from virtual address to 29-bit phys ical address can be achieved by the tlb.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 184 of 950 rej09b0079-0200 1. p0, p3, and u0 areas the p0, p3, and u0 areas can be address translated by the tlb and can be accessed through the cache. if the mmu is enabled, these areas can be mapped to any physical address space in 1- or 4-kbyte page units via the tlb. if the ce bit in the cache control register (ccr1) is set to 1 and if the corresp onding cache enable bit (c bit) of the tlb entry is set to 1, access via the cache is enabled. if the mmu is disabled, replaci ng the upper three bits of an address in these areas with 0s creates the address in the corresponding physical ad dress space. if the ce bit of the ccr1 register is set to 1, access via the cache is enabled. when the cache is used, either the copy-back or write-through mode is selected for write access via the wt bit in ccr1. if these areas are mapped to the on-chip module control register area or on-chip memory area in area 1 in the physical addr ess space via the tlb, the c bit of the corresponding page must be cleared to 0. 2. p1 area the p1 area can be accessed via the cache and cannot be address-tran slated by the tlb. whether the mmu is enabled or not, replacing the upper three bits of an address in these areas with 0s creates the address in the corresponding physical addr ess space. use of the cache is determined by the ce bit in th e cache control register (ccr1). wh en the cache is used, either the copy-back or write-through mode is select ed for write access by the cb bit in the ccr1 register. 3. p2 area the p2 area cannot be accessed via the cache and cannot be address-tran slated by the tlb. whether the mmu is enabled or not, replacing th e upper three bits of an address in this area with 0s creates the addr ess in the corresponding physical address space. 4. p4 area the p4 area is mapped to the on-chip i/o of this lsi. this area cannot be accessed via the cache and cannot be address-translated by the tlb . figure 5.4 shows the configuration of the p4 area.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 185 of 950 rej09b0079-0200 h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 h'ffff ffff area p0 cacheable address translation possible area u0 cacheable address translation possible area uxy * area p1 cacheable address translation not possible area p2 non-cacheable address translation not possible area p3 cacheable address translation possible area p4 non-cacheable address translation not possible address error address error h'0000 0000 h'8000 0000 h'a500 0000 h'a5ff ffff h'ffff ffff h'0000 0000 privileged mode user mode area 0 area 1 area 2 area 3 area 4 area 5 area 7 area 6 external address space * : only exists when sr.dsp = 1 256 256 figure 5.2 virtual add ress space (mmucr.at = 1)
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 186 of 950 rej09b0079-0200 h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 h'ffff ffff area p0 cacheable area u0 cacheable area uxy * area p1 cacheable area p2 non-cacheable area p3 cacheable area p4 non-cacheable address error address error h'0000 0000 h'8000 0000 h'a500 0000 h'a5ff ffff h'ffff ffff h'0000 0000 privileged mode user mode area 0 area 1 area 2 area 3 area 4 area 5 area 7 area 6 external address space * : only exists when sr.dsp = 1 figure 5.3 virtual add ress space (mmucr.at = 0)
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 187 of 950 rej09b0079-0200 h'f000 0000 h'f100 0000 h'f200 0000 h'f300 0000 h'f400 0000 h'ffff ffff h'fc00 0000 reserved area reserved area cache address array cache data array tlb address array tlb data array h'e000 0000 control register area figure 5.4 p4 area the area from h'f000 0000 to h'f0ff ffff is fo r direct access to the cache address array. for more information, see section 6.4, memory-mapped cache. the area from h'f100 0000 to h'f1ff ffff is for direct access to the cache data array. for more information, see section 6.4, memory-mapped cache. the area from h'f200 0000 to h'f2ff ffff is for direct access to the tlb address array. for more information, see section 5.6, memory-mapped tlb. the area from h'f300 0000 to h'f3ff ffff is fo r direct access to the tlb data array. for more information, see section 5.6, memory-mapped tlb. the area from h'fc00 0000 to h'ffff ffff is reserved for registers of the on-chip peripheral modules. for more information, see section 24, list of registers. 5. uxy area the uxy area is mapped to the on-chip memory of this lsi. this area is made usable in user mode when the dsp bit in the sr register is se t to 1. in user mode, accessing this area when the dsp bit is 0 will result in an address error. this area cannot be accessed via the cache and cannot be address-translated by the tlb. for more information on the uxy area, see section 7, x/y memory.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 188 of 950 rej09b0079-0200 physical address space: this lsi supports a 29-bit physical address space. as shown in figure 5.5, the physical address space is divided into eight areas. area 1 is mapped to the on-chip module control register area and on-chip memory area. area 7 is reserved. for details on physical address space, refer to section 12, bus state controller (bsc). h'0400 0000 h'0800 0000 h'0c00 0000 h'1000 0000 h'1400 0000 h'1c00 0000 h'1fff ffff h'1800 0000 area 0 area 1 (on-chip module control register and on-chip memories) area 2 area 3 area 4 area 5 area 6 area 7 (reserved area) h'0000 0000 figure 5.5 external memory space address transition: when the mmu is enabled, the virtual address space is divided into units called pages. physical addresses are translated in page units. addres s translation tables in external memory hold information such as the physical address th at corresponds to the virtual address and memory protection codes. when an access to area p1 or p2 occurs, there is no tlb access and the physical address is defined uniquely by hardware. if it belongs to area p0, p3 or u0, the tlb is searched by virtual address and, if that virtual ad dress is registered in th e tlb, the access hits the tlb. the corresponding physical address and the pa ge control information are read from the tlb and the physical addr ess is determined. if the virtual address is not registered in the tlb, a tlb miss exception occurs and processing will shift to the tlb miss handler. in the tlb miss handler, the tlb address translation table in external memory is searched and the correspon ding physical address and the page control information are registered in the tlb. after return ing from the handler, th e instruction that caused the tlb miss is re-executed. when the mmu is enabled, address translation information that
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 189 of 950 rej09b0079-0200 results in a physical address space of h'20000000 to h'ffffffff sh ould not be registered in the tlb. when the mmu is disabled, masking the upper three bits of the virtual address to 0s creates the address in the corr esponding physical address space. since this lsi supports 29-bit address space as physical address space, the uppe r three bits of the virtual addr ess are ignored as shadow areas. for details, refer to section 12, bus state controller (bsc). for example, address h'00001000 in the p0 area, address h'80001000 in the p1 area, address h'a000100 0 in the p2 area, and address h'c0001000 in the p3 area are all mapped to the same physical memory. if these addresses are accessed while the cache is enabled, the upper three bits are always cleared to 0 to guarantee the continuity of addresses stored in the address array of the cache. single virtual memory mode and multiple virtual memory mode: there are two virtual memory modes: single virtual memory mode and multiple virtual memory mode. in single virtual memory mode, multiple processes run in parallel using the virtual address space exclusively and the physical address corresponding to a given virtual address is specified uniquely. in multiple virtual memory mode, multiple processes run in parallel sharing the virtual address space, so a given virtual address may be translated into different physical addresses depending on the process. by the value set to the mmu control register (mmucr), either single or multiple virtual mode is selected. in terms of operation, the only difference between single virtual memory mode and multiple virtual memory mode is in the tlb address comparison method (see section 5.3.3, tlb address comparison). address space identifier (asid): in multiple virtual memory mode , the address space identifier (asid) is used to differentiate between processes running in parallel and sharing virtual address space. the asid is eight bits in length and can be set by software set ting of the asid of the currently running process in page table entry register high (pteh) within the mmu. when the process is switched using the asid, the tlb does not have to be purged. in single virtual memory mode, the asid is used to provide memory protection for processes running simultaneously and using the virtual addr ess space exclusively (see section 5.3.3, tlb address comparison). 5.2 register descriptions there are four registers for mmu processing. these are all peri pheral module registers, so they are located in address space area p4 and can onl y be accessed from privileged mode by specifying the address.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 190 of 950 rej09b0079-0200 the mmu has the following register s. refer the section 24, list of registers, for the addresses and access size for these registers. ? ? ? ? bit bit name initial value r/w description 31 to 10 vpn ? r/w number of virtual page 9, 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 asid ? r/w address space identifier
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 191 of 950 rej09b0079-0200 5.2.2 page table entry register low (ptel) the page table entry register low (ptel) register residing at address h'fffffff4, and used to store the physical page number and page management information to be recorded in the tlb by the ldtlb instruction. the contents of this register are only modified in response to a software command. bit bit name initial value r/w description 31 to 29 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 28 to 10 ppn ? r number of physical page 9 ? 0 r/w 8 v ? 7 ? 0 6, 5 pr ? 4 sz ? 3 c ? 2 d ? 1 sh ? 0 ? 0 page management information for more details, see section 5.3, tlb functions 5.2.3 translation table base register (ttb) the translation table base register (ttb) residing at address h'fffffff8, which points to the base address of the current page table. the hard ware does not set any value in ttb automatically. ttb is available to software for general purposes. the initial value is undefined. 5.2.4 mmu control register (mmucr) the mmu control register (mmucr) residing at address h'ffffffe0, which makes the mmu settings described in figure 5.3. any program that modifies mmucr should reside in the p1 or p2 area.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 192 of 950 rej09b0079-0200 bit bit name initial value r/w description 31 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 sv 0 r/w single virtual memory mode 0: multiple virtual memory mode 1: single virtual memory mode 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5, 4 rc all 0 r/w random counter a 2-bit random counter that is automatically updated by hardware according to the following rules in the event of an mmu exception. when a tlb miss exception occurs, all of tlb entry way corresponding to the virtual address at which the exception occurred are checked. if all ways are valid, 1 is added to rc; if there is one or more invalid way, they are set by priority from way 0, in the order way 0, way 1, wa y 2, way 3. in the event of an mmu exception other than a tlb miss exception, the way which caused the exception is set in rc. 3 ? 0 r reserved these bits are always read as 0. the write value should always be 0. 2 tf 0 r/w tlb flush write 1 to flush the tlb (clear all valid bits of the tlb to 0). when they are read, 0 is always returned. 1 ix 0 r/w index mode 0: vpn bits 16 to 12 are used as the tlb index number. 1: the value obtained by ex-oring asid bits 4 to 0 in pteh and vpn bits 16 to 12 is used as the tlb index number.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 193 of 950 rej09b0079-0200 bit bit name initial value r/w description 0 at 0 r/w address translation enables/disables the mmu. 0: mmu disabled 1: mmu enabled 5.3 tlb functions 5.3.1 configuration of the tlb the tlb caches address translation table informatio n located in the external memory. the address translation table stores the logical page numb er and the corresponding physical number, the address space identif ier, and the control information for the page, which is the unit of address translation. figure 5.6 shows the overall tlb co nfiguration. the tlb is 4-way set associative with 128 entries. there are 32 entries for each way. figure 5.7 shows the configuration of virtual addresses and tlb entries. entry 1 address array data array entry 0 entry 1 entry 31 way 0 to 3 way 0 to 3 vpn(11-10) vpn(31-17) asid(7-0) v entry 0 entry 31 ppn(28-10) pr(1-0) sz c d sh figure 5.6 overall configuration of the tlb
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 194 of 950 rej09b0079-0200 31 9 vpn virtual address (1-kbyte page) virtual address (4-kbyte page) tlb entry offset vpn vpn (31-17) vpn (11-0) asid v pr sz sh ppn c d offset 0 10 31 11 0 (15) (2) (2) (8) (1) (19) (1) (1) (1) (1) 12 legend vpn: virtual page number upper 22 bits of virtual address for a 1-kbyte page, or upper 20 bits of virtual address for a 4-kbyte page. since vpn bits 16 to 12 are used as the index number, they are not stored in the tlb entry. attention must be paid to the synonym problem (see section 5.4.4, avoiding synonym problems). asid: address space identifier indicates the process that can access a virtual page. in single virtual memory mode and user mode, or in multiple virtual memory mode, if the sh bit is 0, the address is compared with the asid in pteh when address comparison is performed. sh: share status bit 0: page not shared between processes 1: page shared between processes sz: page-size bit 0: 1-kbyte page 1: 4-kbyte page v: valid bit indicates whether entry is valid. 0: invalid 1: valid cleared to 0 by a power-on reset. not affected by a manual reset. ppn: physical page number upper 22 bits of physical address. ppn bits 11 to10 are not used in case of a 4-kbyte page. pr: protection key field 2-bit field encoded to define the access rights to the page. 00: reading only is possible in privileged mode. 01: reading/writing is possible in privileged mode. 10: reading only is possible in privileged/user mode. 11: reading/writing is possible in privileged/user mode. c: cacheable bit indicates whether the page is cacheable. 0: non-cacheable 1: cacheable d: dirty bit indicates whether the page has been written to. 0: not written to figure 5.7 virtual address and tlb structure
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 195 of 950 rej09b0079-0200 5.3.2 tlb indexing the tlb uses a 4-way set associative scheme, so en tries must be selected by index. vpn bits 16 to 12 are used as the index number regardless of the page size. the index number can be generated in two different ways depending on the setting of the ix bit in mmucr. 1. when ix = 0, vpn bits 16 to 12 alone are used as the index number 2. when ix = 1, vpn bits 16 to 12 are ex-ored with asid bits 4 to 0 to generate a 5-bit index number the first method is used to prevent lowered tlb efficiency that results when multiple processes run simultaneously in the same virtual addre ss space (multiple virtual memory) and a specific entry is selected by indexing of each process. in single virt ual memory mode (mmucr.sv = 1), ix bit should be set to 0. figures 5.8 and 5.9 show the indexing schemes. 31 16 11 12 17 0 31 0 pteh register virtual address vpn 0 asid 7 10 index asid(4-0) exclusive-or way 0 to 3 vpn(31-17) vpn(11-10) asid(7-0) v 0 31 address array data array ppn(28-10) pr(1-0) sz c d sh figure 5.8 tlb indexing (ix = 1)
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 196 of 950 rej09b0079-0200 31 16 11 12 17 0 virtual address index way 0 to 3 vpn(31-17) vpn(11-10) asid(7-0) v 0 31 address array data array ppn(28-10) pr(1-0) sz c d sh figure 5.9 tlb indexing (ix = 0) 5.3.3 tlb address comparison the results of address co mparison determine whether a specific virtual page number is registered in the tlb. the virtual page number of the vi rtual address that accesses external memory is compared to the virtual page number of the indexed tlb entry. the asid within the pteh is compared to the asid of the indexed tlb entry. all four ways are search ed simultaneously. if the compared values match, and the indexed tlb entry is valid (v bit = = = = =
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 197 of 950 rej09b0079-0200 registered in index mode. when memory is shared by several processings, different pages must be registered in each asid. the object compared varies depending on the page management information (sz, sh) in the tlb entry. it also varies depending on whether the system supports multiple virtual memory or single virtual memory. the page-size information determines whether vpn (11 to 10) is compared. vpn (11 to 10) is compared for 1-kbyte pages (sz = 0) but not for 4-kbyte pages (sz = 1). the sharing information (sh) determines whethe r the pteh.asid and the asid in the tlb entry are compared. asids are comp ared when there is no sh aring between processes (sh = = = = sh = 1 or (sr.md = 1 and mmucr.sv = 1)? sz = 0? sz = 0? no no (4-kbyte) yes yes (1-kbyte) no (4-kbyte) yes (1-kbyte) bits compared: vpn 31 to 17 vpn 11 to 10 bits compared: vpn 31 to 17 bits compared: vpn 31 to 17 vpn 11 to 10 asid 7 to 0 bits compared: vpn 31 to 17 asid 7 to 0 figure 5.10 objects of address comparison
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 198 of 950 rej09b0079-0200 5.3.4 page management information in addition to the sh and sz bits, the page management information of tlb entries also includes d, c, and pr bits. the d bit of a tlb entry indicates whether the page is dirty (i.e., has been written to). if the d bit is 0, an attempt to write to the page results in an initial page write exception. for physical page swapping between secondary memory and main memory, for example, pages are controlled so that a dirty page is paged out of main memory only after that page is written back to secondary memory. to record that there has been a write to a given page in the address translation table in memory, an initial page write exception is used. the c bit in the entry indicates whether the re ferenced page resides in a cacheable or non- cacheable area of memory. when th e control registers and on-chip memory in area 1 are mapped, set the c bit to 0. the pr field specifies the access rights for the pa ge in privileged and user modes and is used to protect memo ry. attempts at non-permitted accesses result in tlb protection violation exceptions. access states designated by the d, c, and pr bits are shown in table 5.1.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 199 of 950 rej09b0079-0200 table 5.1 access states designat ed by d, c, and pr bits privileged mode user mode reading writing reading writing d bit 0 permitted initial page write exception permitted initial page write exception 1 permitted permitted permitted permitted c bit 0 permitted (no caching) permitted (no caching) permitted (no caching) permitted (no caching) 1 permitted (with caching) permitted (with caching) permitted (with caching) permitted (with caching) pr bit 00 permitted tlb protection violation exception tlb protection violation exception tlb protection violation exception 01 permitted permitted tlb protection violation exception tlb protection violation exception 10 permitted tlb protection violation exception permitted tlb protection violation exception 11 permitted permitted permitted permitted
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 200 of 950 rej09b0079-0200 5.4 mmu functions 5.4.1 mmu hardware management there are two kinds of mmu hardware management as follows. 1. the mmu decodes the virtual address accessed by a process and perform s address translation by controlling the tlb in accordance with the mmucr settings. 2. in address translation, the mmu receives pa ge management informat ion from the tlb, and determines the mmu exception and whether the cache is to be accessed (using the c bit). for details of the determination method and the hardware processing, see section 5.5, mmu exceptions. 5.4.2 mmu software management there are three kinds of mmu software management, as follows. 1. mmu register setting mmucr setting, in particular, should be perfor med in areas p1 and p2 for which address translation is not performed. also, since sv and ix bit changes constitute address translation system changes, in this case, tlb flushing should be performed by simultaneously writing 1 to the tf bit also. since mmu excep tions are not generated in the mmu disabled state with the at bit cleared to 0, use in the disabled state mu st be avoided with software that does not use the mmu. 2. tlb entry recording, deletion, and reading tlb entry recording can be done in two ways by using the ldtlb instruction, or by writing directly to the memory-mapped tlb. for tlb entry deletion and reading, the memory allocation tlb can be accessed. see section 5.4. 3, mmu instruction (ldtlb), for details of the ldtlb instruction, and section 5.6, memory-mapped tlb, for details of the memory- mapped tlb. 3. mmu exception processing when an mmu exception is generated, it is handled on the basis of information set from the hardware side. see section 5.5, mmu exceptions, for details. when single virtual memory mode is used, it is possible to create a state in which physical memory access is enabled in the privileged mode only by clearing the share stat us bit (sh) to 0 to specify recording of all tlb en tries. this strengthens inter- process memory protection, and enables special access levels to be cr eated in the privileged mode only.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 201 of 950 rej09b0079-0200 recording a 1- or 4- kbyte page tlb entry may result in a synonym problem. see section 5.4.4, avoiding synonym problems. 5.4.3 mmu instruction (ldtlb) the load tlb instruction (ldtlb) is used to record tlb entries. when the ix bit in mmucr is 0, the ldtlb instruction changes the tlb entry in the way specified by the rc bit in mmucr to the value specified by pteh and ptel, using vpn bits 16 to 12 speci fied in pteh as the index number. when the ix bit in mmucr is 1, the ex-or of vpn bits 16 to 12 specified in pteh and asid bits 4 to 0 in pteh are used as the index number. figure 5.11 shows the case where the ix bit in mmucr is 0. when an mmu exception occurs, the virtual page number of the virtual address that caused the exception is set in pteh by hardware. the way is set in the rc bit of mmucr for each exception according to the rules (see section 5.2.4, mmu control register (mmucr)). consequently, if the ldtlb instruction is issued after setting only ptel in the mmu exception processing routine, tlb entry recording is possible. any tlb entry can be updated by software rewriting of pteh and the rc bits in mmucr. as the ldtlb instruction changes address translatio n information, there is a risk of destroying address translation information if this instruction is issued in the p0, u0, or p3 area. make sure, therefore, that this instruction is issued in the p1 or p2 area. also, an instru ction associated with an access to the p0, u0, or p3 area (such as the rte instruction) should be issued at least two instructions after the ldtlb instruction.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 202 of 950 rej09b0079-0200 vpn(31-17) vpn(11-10) asid(7-0) v vpn 0 asid vpn 0sv00rc0tfixat ppn 0 0 v 0 pr sz c d sh 0 write ppn(28-10) pr(1-0) sz c d sh write data array address array way selection way 0 to 3 31 9 0 mmucr index 31 17 12 10 8 0 pteh register 31 29 28 10 0 ptel register 0 31 0 0 figure 5.11 operation of ldtlb instruction 5.4.4 avoiding synonym problems when a 1- or 4-kbyte page is recorded in a tlb entry, a synonym problem may arise. if a number of virtual addresses are mapped onto a single physi cal address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity. the reason that this problem occurs is explained below with reference to figure 5.12. the relationship between bit n of the virtual address and cache size is shown in the following table. cache size bit n of virtual address 16 kbytes 11 32 kbytes 12 to achieve high-speed operation of this lsi?s cach e, an index number is created using virtual address [n:4]. when a 1-kbyte page is used, virtual address [n:10] is subject to address translation and when a 4-kbyte page is used, a virtual address [n:12] is subject to address translation. therefore, the physical address [n:10] may not be the same as the virtual address [n:10]. for example, assume that, with 1-kbyte page tlb entries, tlb entries for which the following translation has been performed are recorded in two tlbs:
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 203 of 950 rej09b0079-0200 virtual address 1 h'00000000
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 204 of 950 rej09b0079-0200 when using a 4-kbyte page virtual address 31 vpn 0 12 13 11 10 offset physical address 28 ppn 0 offset virtual address 12 to 4 physical address 28 to 10 cache when using a 1-kbyte page virtual address 31 vpn 0 10 11 12 13 offset physical address 28 ppn 0 10 11 12 13 offset virtual address 12 to 4 physical address 28 to 10 cache 12 13 11 10 figure 5.12 synonym problem (32-kbyte cache)
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 205 of 950 rej09b0079-0200 5.5 mmu exceptions when the address translation unit of the mmu is enabled, occurrence of the mmu exception is checked following the cpu address error check. there are four mmu exceptions: tlb miss, tlb protection violation, tlb invalid, and initial page write, and these mmu exceptions are checked in this order. 5.5.1 tlb miss exception a tlb miss results when the virtual address and th e address array of the selected tlb entry are compared and no match is found. tlb miss exception processing includes both hardware and software operations. hardware operations: in a tlb miss, this hard ware executes a set of prescribed operations, as follows: 1. the vpn field of the virtual address causing the exception is written to the pteh register. 2. the virtual address causing the exception is written to the tea register. 3. either exception code h'040 for a load access, or h'060 for a store access, is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written to the save program counter (spc). if the exception occurred in a delay slot, the pc value indicating the address of the related dela yed branch instruction is written to the spc. 5. the contents of the status register (sr) at the time of the exception are written to the save status register (ssr). 6. the md bit in sr is set to 1 to place the privileged mode. 7. the bl bit in sr is set to 1 to mask any further exception requests. 8. the rb bit in sr is set to 1. 9. the rc field in the mmu control register (mmucr) is incremented by 1 when all entries indexed are valid. when some entries indexed are invalid, the smallest way number of them is set in rc. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000400 to invoke the user-written tlb miss exception handler. software (tlb miss handler) operations: the software searches the page tables in external memory and allocates the required page table entry. upon retrieving the required page table entry, software must execute th e following operations:
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 206 of 950 rej09b0079-0200 1. write the value of the physical page number (ppn) field and the protection key (pr), page size (sz), cacheable (c), dirty (d), share status (sh), and valid (v) bits of the page table entry recorded in the address translation table in the external memory into the ptel register. 2. if using software for way sel ection for entry replacement, write the desired value to the rc field in mmucr. 3. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 4. issue the return from exception handler (rte) instruction to terminate the handler routine and return to the instruction stream. 5.5.2 tlb protection violation exception a tlb protection violation exception results when the virtual address and the address array of the selected tlb entry are compared an d a valid entry is found to matc h, but the type of access is not permitted by the access rights specified in the pr field. tlb protec tion violation exception processing includes both hardware and software operations. hardware operations: in a tlb protection violation exception, this hardware executes a set of prescribed operations, as follows: 1. the vpn field of the virtual address causing the exception is written to the pteh register. 2. the virtual address causing the exce ption is written to the tea register. 3. either exception code h'0a0 fo r a load access, or h'0c0 for a store access, is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written into spc (if the exception occurred in a de lay slot, the pc value indicating the address of the related delayed branch instruction is written into spc). 5. the contents of sr at the time of the exception are written to ssr. 6. the md bit in sr is set to 1 to place the privileged mode. 7. the bl bit in sr is set to 1 to mask any further exception requests. 8. the rb bit in sr is set to 1. 9. the way that generated the exception is set in the rc field in mmucr. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000100 to invoke the tlb protection violation exception handler. software (tlb protection viol ation handler) operations: software resolves the tlb protection violation and issues the rte (return from exception handler) instruction to terminate the handler and return to the instruction stream. issue the rte instruction after issuing two instructions from the ldtlb instruction.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 207 of 950 rej09b0079-0200 5.5.3 tlb invalid exception a tlb invalid exception results when the virtual address is compared to a selected tlb entry address array and a match is found but the entry is not valid (the v bit is 0). tlb invalid exception processing includes both hardware and software operations. hardware operations: in a tlb invalid exception, this hardware executes a set of prescribed operations, as follows: 1. the vpn number of the virtua l address causing the exception is written to the pteh register. 2. the virtual address causing the exception is written to the tea register. 3. either exception code h'040 fo r a load access, or h'060 for a store access, is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written to the spc. if the exception occurred in a delay slot, the pc value indicating the address of the delayed branch in struction is written to the spc. 5. the contents of sr at the time of the exception are written into ssr. 6. the mode (md) bit in sr is set to 1 to place the privileged mode. 7. the block (bl) bit in sr is set to 1 to mask any further exception requests. 8. the rb bit in sr is set to 1. 9. the way number causing the exception is written to rc in mmucr. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000100, and the tlb protection violation exception handler starts. software (tlb invalid exce ption handler) operations: the software searches the page tables in external memory and assigns the required page table entry. upon retrieving the required page table entry, software must execute the following operations: 1. write the values of the physical page number (ppn) field and the values of the protection key (pr), page size (sz), cacheable (c), dirty (d), shar e status (sh), and valid (v) bits of the page table entry recorded in the extern al memory to the ptel register. 2. if using software for way sel ection for entry replacement, write the desired value to the rc field in mmucr. 3. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 4. issue the rte instruction to terminate the ha ndler and return to the instruction stream. the rte instruction should be issued after two ldtlb instructions.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 208 of 950 rej09b0079-0200 5.5.4 initial page write exception an initial page write exception results in a write access when the virtual address and the address array of the selected tlb entry are compared an d a valid entry with th e appropriate access rights is found to match, but the d (dirty) bit of the entr y is 0 (the page has not been written to). initial page write exception processing includes both hardware and software operations. hardware operations: in an initial page write exception, this hardware executes a set of prescribed operations, as follows: 1. the vpn field of the virtual address causing the exception is written to the pteh register. 2. the virtual address causing the exce ption is written to the tea register. 3. exception code h'080 is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written to the spc. if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written to the spc. 5. the contents of sr at the time of the exception are written to ssr. 6. the md bit in sr is set to 1 to place the privileged mode. 7. the bl bit in sr is set to 1 to mask any further exception requests. 8. the rb bit in sr is set to 1. 9. the way that caused the exception is set in the rc field in mmucr. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000100 to invoke the user-written initial page write exception handler. software (initial page write handler) operations: the software must execute the following operations: 1. retrieve the required page table entry from external memory. 2. set the d bit of the page table entry in the external memory to 1. 3. write the value of the ppn field and the pr, sz, c, d, sh, and v bits of the page table entry in the external memory to the ptel register. 4. if using software for way sel ection for entry replacement, write the desired value to the rc field in mmucr. 5. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 6. issue the rte instruction to terminate the ha ndler and return to the instruction stream. the rte instruction must be issued after two ldtlb instructions.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 209 of 950 rej09b0079-0200 5.5.5 mmu exception in repeat loop if a cpu address error or mmu exception occurs in a specific instruction in the repeat loop, the spc may indicate an illegal address or the repeat loop cannot be reexecuted correctly even if the spc is correct. accordingly, if a cpu addres s error or mmu exception occurs in a specific instruction in the repeat loop, this lsi generate s a specific exception code to set the expevt to h?070 for a tlb miss exception, tlb invalid exception, initial page write exception, and cpu address error and to h?0d0 for a tlb protection violation exception. in additi on, a vector offset for tlb miss exception is h?100. for details, refer to section 4.4.3,exception in repeat control period.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 210 of 950 rej09b0079-0200 start sh = 0 and (mmucr.sv = 0 or sr.md = 0)? vpns and asids match? v=1? user or privileged? d=1? c=1? memory access cache access initial page write exception tlb protection violation exception pr? tlb protection violation exception r/w? r/w? r/w? r/w? pr? tlb invalid exception tlb miss exception cpu address error vpns match? no no no no (non-cacheable) yes (cacheable) yes yes yes yes yes no address error? yes no no user mode privileged mode 01/11 00/10 00/01 10 11 wwww r rr r figure 5.13 mmu exception generation flowchart
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 211 of 950 rej09b0079-0200 5.6 memory-mapped tlb in order for tlb operations to be managed by software, tlb contents can be read or written to in the privileged mode using the mov instruction. the tlb is assigned to the p4 area in the virtual address space. the tlb address array (vpn, v b it, and asid) is assigned to h'f2000000 to h'f2ffffff, and the data array (ppn, pr, sz, c, d, and sh bits) to h'f3000000 to h'f3ffffff. the v bit in the ad dress array can also be accesse d from the data array. only longword access is possible for both the address array and the data array. however, the instruction data cannot be fetched from both arrays. 5.6.1 address array the address array is assigned to h'f2000000 to h'f2ffffff. to access an address array, the 32- bit address field (for read/write operations) and 32-bit data field (for write operations) must be specified. the address field specifi es information for se lecting the entry to be accessed; the data field specifies the vpn, v bit and asid to be written to the address array (figure 5.14 (1)). in the address field, specify th e entry address for selecting th e entry (bits 16 to 12), w for selecting the way (bits 9 to 8) and h'f2 to indicat e address array access (bits 31 to 24). the ix bit in mmucr indicates whether an ex-or is taken of the entry address and asid. the following two operations can be used on the address array: 1. address array read vpn, v, and asid are read from the tlb entr y corresponding to the entry address and way set in the address field. 2. tlb address array write the data specified in the data field are written to the tlb entry corresponding to the entry address and way set in the address field. 5.6.2 data array the data array is assigned to h'f3000000 to h'f3ffffff. to access a data array, the 32-bit address field (for read/write op erations), and 32-bit data field (for write operations) must be specified. the address section speci fies information for selecting th e entry to be accessed; the data section specifies the longword data to be written to the data array (figure 5.14 (2)). in the address section, specify the entry address for selecting the entry (bits 16 to 12), w for selecting the way (bits 9 to 8), and h'f3 to indicat e data array access (bits 31 to 24). the ix bit in mmucr indicates whether an ex-or is taken of the entry address and asid.
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 212 of 950 rej09b0079-0200 both reading and writing use the longword of the data array specified by the entry address and way number. the access size of the da ta array is fixed at longword. 1 1 1 1 0 0 1 0 9 vpn: virtual page number v: valid bit w: way (00: way 0, 01: way 1, 10: way 2, 11: way 3) asid: address space identifier * : don?t care bit address field data field address field data field address field data field 31 24 23 17 16 12 1110 9 8 7 0 31 17 16 12 1110 9 8 7 0 31 24 23 17 16 12 11 11 10 9 8 7 0 31 17 16 12 10 9 8 7 0 31 24 23 29 28 17 16 12 1110 9 8 7 0 1 2 31 10 8 7 0 6 654321 0 0 0 vpn 1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 1 (1) tlb address array access read access write access (2) tlb data array access read/write access 6 * . . . . . . . . . . . . * vpn w 0 ** * . . . . . . . . . * vpn 0 . . . . . . . 0 vpn 0 v asid * . . . . . . . . . . . . * vpn * . . . . . . . * w0 * . . . . . . . . . * * * vpn v * asid * . . . . . . . . . . . . * vpn w * . . . . . . . . . . . * * * ppn xvx pr sz cd sh x ppn: physical page number pr: protection key field c: cacheable bit sh: share status bit vpn: virtual page number x: 0 for read, don?t care bit for write w: way (00: way 0, 01: way 1, 10: way 2, 11: way 3) v: valid bit sz: page-size bit d: dirty bit * : don?t care bit 00 1 2 00 1 2 00 figure 5.14 specifying address a nd data for memory-mapped tlb access
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 213 of 950 rej09b0079-0200 5.6.3 usage examples invalidating specific entries: specific tlb entries can be invalidat ed by writing 0 to the entry?s v bit. r0 specifies the write data and r1 specifies the address. ; r0=h'1547 381c r1=h'f201 3000 ; mmucr.ix=0 ; the v bit of way 0 of the entry selected by the vpn(16?12)=b'1 0011 ; index is cleared to0,achieving invalidation. mov.l r0,@r1 reading the data of a specific entry: this example reads the data section of a specific tlb entry. the bit order indicated in the data field in figure 5.14 (2) is read. r0 specifies the address and the data section of a selected entry is read to r1. ; r0 = h'f300 4300 vpn(16-12)=b'00100 way 3 ; mov.l @r0,r1 5.7 usage note the following operations should be performed in the p1 or p2 areas. in addition, when the p0, p3, or u0 areas are accessed consecutively (this access in cludes instruction fetc hing), the instruction code should be placed at least two instructions after the instruction that executes the following operations. 1. modification of sr.md or sr.bl 2. execution of the ldtlb instruction 3. write to the memory-mapped tlb 4. modification of mmucr 5. modification of pteh.asid
section 5 memory management unit (mmu) rev. 2.00 dec. 07, 2005 page 214 of 950 rej09b0079-0200
section 6 cache rev. 2.00 dec. 07, 2005 page 215 of 950 rej09b0079-0200 section 6 cache 6.1 features ? ? ? ? ? ? ? 24 (1 + 1 + 22) bits 128 (32 4) bits 6 bits lw0 to lw3: longword data 0 to 3 entry 0 entry 1 entry 511 0 1 511 0 1 511 v u tag address lw0 lw1 lw2 lw3 address array (ways 0 to 3) data array (ways 0 to 3) lru . . . . . . . . . . . . . . . . . . figure 6.1 cache structure
section 6 cache rev. 2.00 dec. 07, 2005 page 216 of 950 rej09b0079-0200 address array: the v bit indicates whether the entry data is valid. when the v bit is 1, data is valid; when 0, data is not valid. the u bit indicates whether the entry has been written to in write- back mode. when the u bit is 1, the entry has been written to; when 0, it has not. the tag address holds the physical address used in the external me mory access. it is composed of 22 bits (address bits 31?10) used for comparison during cache searches. in this lsi, the top three of 32 physical address bits are used as shadow bits (see section 12, bus state controller (bsc)), and theref ore the top three bits of the tag address are cleared to 0. the v and u bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. the tag address is not initialized by either a power-on or manual reset. data array: holds a 16-byte instruction or data. entries are registered in the cache in line units (16 bytes). the data array is not initia lized by a power-on or manual reset. lru: with the 4-way set associative system, up to fo ur instructions or data with the same entry address can be registered in the cache. when an entry is register ed, lru shows which of the four ways it is recorded in. there are six lru bits , controlled by hardware. a least-recently-used (lru) algorithm is used to select the way. six lru bits indicate the way to be replaced, when a cache miss occurs. table 6.1 shows the relationship between the lru bits and the way to be replaced when the cache locking mechanism is disabled. (for the relationship when the cache locking mechanism is enabled, refer to section 6.2.2, cache control register 2 (ccr2).) if a bit pattern other than those listed in table 6.1 is set in the lru bits by software, the cache will not function correctly. when modifying the lru bits by software, set one of the patterns listed in table 6.1. the lru bits are initialized to 000000 by a power-on reset, but are not initialized by a manual reset. table 6.1 lru and way replacement (when cache locking mechanism is disabled) lru (bits 5 to 0) way to be replaced 000000, 000100, 010100, 100000, 110000, 110100 3 000001, 000011, 001011, 100001, 101001, 101011 2 000110, 000111, 001111, 010110, 011110, 011111 1 111000, 111001, 111011, 111100, 111110, 111111 0
section 6 cache rev. 2.00 dec. 07, 2005 page 217 of 950 rej09b0079-0200 6.2 register descriptions the cache has the following registers. for details on register addresses and register states during each process, refer to sectio n 24, list of registers. ? ? ? bit bit name initial value r/w description 31 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 cf 0 r/w cache flush writing 1 flushes all cache entries (clears the v, u, and lru bits of all cache entries to 0). this bit is always read as 0. write-back to external memory is not performed when the cache is flushed. 2 cb 0 r/w write-back indicates the cache?s operating mode for space p1. 0: write-through mode 1: write-back mode 1 wt 0 r/w write-through indicates the cache?s operating mode for spaces p0, u0, and p3. 0: write-back mode 1: write-through mode
section 6 cache rev. 2.00 dec. 07, 2005 page 218 of 950 rej09b0079-0200 bit bit name initial value r/w description 0 ce 0 r/w cache enable indicates whether the cache function is used. 0: the cache function is not used. 1: the cache function is used. 6.2.2 cache control register 2 (ccr2) the ccr2 register controls the cache locking me chanism in cache lock mode only. the cpu enters the cache lock mode when the dsp bit (bit 12 ) in the status register (sr) is set to 1 or the lock enable bit (bit 16) in the cache control register 2 (ccr2) is set to 1. the cache locking mechanism is disabled in non- cache lock mode (dsp bit = 0). when a prefetch instruction (pref@rn) is issu ed in cache lock mode and a cache miss occurs, the line of data pointed to by rn will be loaded into the cache, according to the setting of bits 9 and 8 (w3load, w3lock) and bits 1 and 0 (w2load, w2lock in ccr2). table 6.2 shows the relationship between the settings of bits and the way that is to be replaced when the cache is missed by a prefetch instruction. on the other hand, when the cache is hit by a prefetch in struction, new data is not loaded into the cache and the valid entry is held. for example, a prefetch instruction is issued while bits w3load and w3lock are set to 1 and the line of data to which rn points is already in way 0, the cache is hit and new data is not loaded into way 3. in cache lock mode, bits w3lock and w2lock restrict the way that is to be replaced, when instructions other than the prefetch instruction are issued. table 6.3 shows the relationship between the settings of bits in ccr2 and the way that is to be replaced when the cache is missed by instructions other than the prefetch instruction. programs that change the contents of the ccr2 register should be placed in address space that is not cached.
section 6 cache rev. 2.00 dec. 07, 2005 page 219 of 950 rej09b0079-0200 bit bit name initial value r/w description 31 to 17 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 16 le 0 r/w lock enable (le) controls cache lock mode. 0: enters cache lock mode when the dsp bit of the sr register is set to 1. 1: enters cache lock mode regardless of the dsp bit value. 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 w3load w3lock 0 0 r/w r/w way 3 load (w3load) way 3 lock (w3lock) when the cache is missed by a prefetch instruction while in cache lock mode and when bits w3load and w3lock in ccr2 are set to 1, the data is always loaded into way 3. under any other condition, the prefetched data is loaded into the way to which lru points. 7 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 w2load w2lock 0 0 r/w r/w way 2 load (w2load) way 2 lock (w2lock) when the cache is missed by a prefetch instruction while in cache lock mode and when bits w2load and w2lock in ccr2 are set to 1, the data is always loaded into way 2. under any other condition, the prefetched data is loaded into the way to which lru points. note: w2load and w3load should not be set to 1 at the same time.
section 6 cache rev. 2.00 dec. 07, 2005 page 220 of 950 rej09b0079-0200 table 6.2 way replacement when a pref instruction misses the cache dsp bit w3load w3lock w2load w2lock way to be replaced 0 * * * * determined by lru (table 6.1) 1 * 0 * 0 determined by lru (table 6.1) 1 * 0 0 1 determined by lru (table 6.4) 1 0 1 * 0 determined by lru (table 6.5) 1 0 1 0 1 determined by lru (table 6.6) 1 0 * 1 1 way 2 1 1 1 0 * way 3 note: * don't care w3load and w2load should not be set to 1 at the same time. table 6.3 way replacement when instructions other than the pref instruction miss the cache dsp bit w3load w3lock w2load w2lock way to be replaced 0 * * * * determined by lru (table 6.1) 1 * 0 * 0 determined by lru (table 6.1) 1 * 0 * 1 determined by lru (table 6.4) 1 * 1 * 0 determined by lru (table 6.5) 1 * 1 * 1 determined by lru (table 6.6) note: * don't care w3load and w2load should not be set to 1 at the same time. table 6.4 lru and way replacement (when w2lock = 1 and w3lock =0) lru (bits 5 to 0) way to be replaced 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 3 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 1 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 0
section 6 cache rev. 2.00 dec. 07, 2005 page 221 of 950 rej09b0079-0200 table 6.5 lru and way replacement (when w2lock = 0 and w3lock =1) lru (bits 5 to 0) way to be replaced 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 2 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 1 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 table 6.6 lru and way replacement (when w2lock = 1 and w3lock =1) lru (bits 5 to 0) way to be replaced 000000, 000001, 000011, 000100, 00 0110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 1 100000, 100001, 101001, 101011, 11 0000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 6.2.3 cache control register 3 (ccr3) the ccr3 register controls the cache size to be us ed. the cache size must be specified according to the lsi to be selected. if the specified cache size exceeds the size of ca che incorporated in the lsi, correct operation cannot be guaranteed. note th at programs that change the contents of the ccr3 register should be placed in un-cached address space. in addition, note that all cache entries must be invalidated by setting the cf bit of the ccr1 to 1 before acce ssing the cache after the ccr3 is modified. bit bit name initial value r/w description 31 to 24 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 23 to 16 csize7 to csize0 h?01 r/w cache size specify the cache size as shown below. 0000 0001: 16-kbyte cache 0000 0010: 32-kbyte cache settings other than above are prohibited. 15 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 6 cache rev. 2.00 dec. 07, 2005 page 222 of 950 rej09b0079-0200 6.3 operation 6.3.1 searching the cache if the cache is enabled (the ce bit in ccr1 = 1), whenever instructions or data in spaces p0, p1, p3, and u0 are accessed the cache will be searched to see if the desired instruction or data is in the cache. figure 6.2 illustrates the me thod by which the cache is s earched. the cache is a physical cache and holds physical addresses in its address section. entries are selected using bits 12 to 4 of the address (virtual) of the access to memory and the tag address of that entry is read. the virtual address (bits 31 to 10) of the access to memory and the physical address (tag address) read from the ad dress array are compared. the address comparison uses all four ways. when the comparison shows a match and the selected entry is valid (v = 1), a cache hit occurs. when the comparison does not show a match or the selected entry is not valid (v = 0), a cache miss occurs. figure 6.2 shows a hit on way 1.
section 6 cache rev. 2.00 dec. 07, 2005 page 223 of 950 rej09b0079-0200 0 1 511 v u tag address lw0 lw1 lw2 lw3 ways 0 to 3 ways 0 to 3 31 13 12 4 3 2 1 0 virtual address cmp0 cmp1 cmp2 cmp3 physical address cmp0: comparison circuit 0 cmp1: comparison circuit 1 cmp2: comparison circuit 2 cmp3: comparison circuit 3 hit signal 1 entry selection longword (lw) selection mmu figure 6.2 cache search scheme 6.3.2 read access read hit: in a read access, instructions and data are transferred from the cache to the cpu. the lru i s updated to indicate that the hit way is the most recently hit way. read miss: an external bus cycle starts and the entry is updated. the way to be replaced is shown in table 6.3. entries are updated in 16-byte units. when the desired instruct ion or data that caused the miss is loaded from external memory to the cache, th e instruction or data is transferred to the cpu in parallel with being loaded to the cache. when it is loaded to the cach e, the u bit is cleared to 0 and the v bit is set to 1 to indicate that the hit way is the most recently hit way. when the u bit for the entry which is to be replaced by en try updating in write-back mode is 1, the cache- update cycle starts after the entry is transferred to the write-back buffer . after the cache completes its update cycle, the write-back buffer writes the en try back to the memory. transfer is in 16-byte units.
section 6 cache rev. 2.00 dec. 07, 2005 page 224 of 950 rej09b0079-0200 6.3.3 prefetch operation prefetch hit: the lru is updated to indicate that the hit way is the most recently hit way. the other contents of the cache are not changed. instructions and data are not transferred from the cache to the cpu. prefetch miss: instructions and data are not transferred from the cache to the cpu. the way that is to be replaced is shown in table 6.2. the other operations are the same as those for a read miss. 6.3.4 write access write hit: in a write access in write-back mode, the data is written to the cache and no external memory write cycle is issued. the u bit of the entry that has been written to is set to 1, and the lru is updated to indicate that the hit way is th e most recently hit way. in write-through mode, the data is written to the cache and an external memory write cycle is issued. the u bit of the entry that has been written to is not updated, and the lru is updated to indicate that the hit way is the most recently hit way. write miss: in write-back mode, an external write cycl e starts when a write miss occurs, and the entry is updated. the way to be replaced is shown in table 6.3. when the u bit of the entry which is to be replaced by entry updating is 1, the cache-update cycle starts after the entry has been transferred to the write-back buffer. data is written to the cache an d the u bit and the v bit are set to 1. the lru is updated to indicate that the repl aced way is the most recently updated way. after the cache has completed its update cycle, the wr ite-back buffer writes th e entry back to the memory. transfer is in 16-byte un its. in write-through mode, no wr ite to cache occurs in a write miss; the write is only to the external memory. 6.3.5 write-back buffer when the u bit of the entry to be replaced in write-back mode is 1, the entry must be written back to the external memory. to increas e performance, the entry to be re placed is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. after the fetching of new entrie s to the cache completes, the write-back buffer writes the entry back to the ex ternal memory. during the write- back cycles, the cache can be accessed. the write-back buffer can hold one line of cache data (16 bytes) and its physical address. figure 6.3 shows the configuration of the write-back buffer.
section 6 cache rev. 2.00 dec. 07, 2005 page 225 of 950 rej09b0079-0200 longword 0 longword 1 longword 2 longword 3 pa (31 to 4) pa (31 to 4): longword 0 to 3: physical address written to external memory one line of cache data to be written to external memory figure 6.3 write-back buffer configuration 6.3.6 coherency of cach e and external memory use software to ensure coherency between the cache and the external memory. when memory shared by this lsi and another device is placed in an address space to which caching applies, use the memory-mapped cache to make the data invalid and written back, as required. memory that is shared by this lsi?s cpu and dmac should also be handled in this way.
section 6 cache rev. 2.00 dec. 07, 2005 page 226 of 950 rej09b0079-0200 6.4 memory-mapped cache to allow software management of the cache, cache contents can be read an d written by means of mov instructions in pr ivileged mode. the cache is mapped ont o the p4 area in virtual address space. the address array is mapped onto addre sses h'f0000000 to h'f0ffffff, and the data array onto addresses h'f1000000 to h'f1ffffff. on ly longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 6.4.1 address array the address array is mapped onto h'f0000000 to h'f0ffffff. to access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. the address field specifi es information for se lecting the entry to be accessed; the data field specifies the tag address, v bit, u bit, an d lru bits to be written to the address array. in the address field, specify the entry address for selecting the entry, w for selecting the way, a for enabling or disabling the a ssociative operation, and h'f0 for indicating address array access. as for w, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3). in the data field, specify the tag address, lru bits, u bit, and v bit. figures 6.4 and 6.5 show the address and data formats. the following three op erations are available in the address array. address-array read: read the tag address, lru bits, u bit, and v bit for the entry that corresponds to the en try address and way specified by the address field of the read instruction. in reading, the associative operation is not performe d, regardless of whether the associa tive bit (a bit) specified in the address is 1 or 0. address-array write (non-associative operation): write the tag address, lru bits, u bit, and v bit, specified by the data field of the write instruction, to the entry that corresponds to the entry address and way as specified by the address field of the write instruction. ensure that the associative bit (a bit) in the address field is set to 0. when writing to a cache line for which the u bit = 1 and the v bit =1, write the contents of the cache line back to memory, then write the tag address, lru bits, u bit, and v b it specified by the data field of the write instruction. when 0 is written to the v bit, 0 must also be written to the u bit for that entry. address-array write (associative operation): when writing with the associative bit (a bit) of the address = 1, the addresses in the four ways for the entry specified by the address field of the write instruction are compared with the tag address that is specified by the data field of the write instruction. if the mmu is enabled in this case, a logical address specified by data is translated into a physical address via the tlb before comparison. write the u bit and the v bit specified by the data field of the write instruction to the entry of the way that has a hit. however, the tag
section 6 cache rev. 2.00 dec. 07, 2005 page 227 of 950 rej09b0079-0200 address and lru bits remain unch anged. when there is no way th at receives a hit, nothing is written and there is no operation. this function is used to invalida te a specific entry in the cache. when the u bit of the entry that has received a h it is 1 at this point, writing back should be performed. however, when 0 is written to the v bit, 0 must also be written to the u bit of that entry. 6.4.2 data array the data array is mapped onto h'f1000000 to h'f1ffffff. to access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write acce sses) must be specified. the address field specifies info rmation for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. in the address field, specify the entry address for selecting the entry, l for indicating the longword position within the (16-byte) line, w for selecting the way, and h'f1 for indicating data array access. as for l, 00 indicates longword 0, 01 indi cates longword 1, 10 in dicates longword 2, and 11 indicates longword 3. as for w, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3. since access size of the data array is fixed at longwo rd, bits 1 and 0 of the address field should be set to 00. figures 6.4 and 6.5 show the address and data formats. the following two operations on the data array ar e available. the information in the address array is not affected by these operations. data-array read: read the data specified by l of the address filed, from the entry that corresponds to th e entry address and the way that is specified by the address filed. data-array write: write the longword data specified by the data filed, to the position specified by l of the address field, in th e entry that corresponds to the en try address and the way specified by the address field.
section 6 cache rev. 2.00 dec. 07, 2005 page 228 of 950 rej09b0079-0200 (1) address array access (a) address specification read access write access (b) data specification (both read and write accesses) (2) data array access (both read and write accesses) (a) address specification 31 24 23 14 13 12 11 4 3 0 1111 0000 * -------- * w entry address 31 24 23 14 13 12 11 4 3 0 1111 0000 * -------- * w entry address 2 a 31 10 4 3 0 lru 2 xx 9 tag address (31 to 10) u v 1 31 24 23 14 13 12 11 4 3 0 1111 0001 * -------- * w entry address 1 2 l (b) data specification 31 0 longword * : don?t care bit x: 0 for read, don?t care for write 0 * 0 0 * 0 0 2 00 figure 6.4 specifying address and data for memory-m apped cache access (16 kbytes mode)
section 6 cache rev. 2.00 dec. 07, 2005 page 229 of 950 rej09b0079-0200 (1) address array access (a) address specification read access write access (b) data specification (both read and write accesses) (2) data array access (both read and write accesses) (a) address specification 31 24 23 15 14 13 12 4 3 0 1111 0000 * -------- * w entry address 31 24 23 15 14 13 12 4 3 0 1111 0000 * -------- * w entry address 2 a 31 10 4 3 0 lru 2 xx 9 tag address (28 to 10) u v 1 31 24 23 15 14 13 12 4 3 0 1111 0001 * -------- * w entry address 1 2 l (b) data specification 31 0 longword * : don?t care bit x: 0 for read, don?t care for write 0 * 0 0 * 0 0 2 0 0 30 29 28 0 0 0 figure 6.5 specifying address and data for memory-m apped cache access (32 kbytes mode)
section 6 cache rev. 2.00 dec. 07, 2005 page 230 of 950 rej09b0079-0200 6.4.3 usage examples invalidating specific entries: specific cache entries can be invalidated by writing 0 to the entry?s v bit in the me mory-mapped cache access. when the a b it is 1, the tag address specified by the write data is compared to the tag address within the cache se lected by the entry address, and a match is found, the entry is written back if the entry?s u bit is 1 and the v bit and u bit specified by the write data are written. if no match is fo und, there is no operation. in the example shown below, r0 specifies the write data and r1 specifies the address. ; r0 = h'01100010; vpn = b'0000 0001 0001 0000 0000 00, u = 0, v = 0 ; r1 = h'f0000088; address array access, entry = b'00001000, a = 1 ; mov.l r0,@r1 reading the data of a specific entry: to read the data field of a specific entry is enabled by the memory-mapped cache access. the long word indicated in the data fiel d of the data array in figure 6.4 or 6.5 is read into the register. in the exam ple shown below, r0 specifies the address and r1 shows what is read. ; r0 = h'f100 004c; data array access, entry = b'00000100 ; way = 0, longword address = 3 ; mov.l @r0,r1 ; longword 3 is read.
section 7 x/y memory rev. 2.00 dec. 07, 2005 page 231 of 950 rej09b0079-0200 section 7 x/y memory this lsi has on-chip x-memory and y-memory which can be used to store instructions or data. 7.1 features ? ? memory size (total four pages) page 16 kbytes page 0 of x memory h a5007000 to h a5007fff page 1 of x memory h a5008000 to h a5008fff page 0 of y memory h a5017000 to h a5017fff page 1 of y memory h a5018000 to h a5018fff on the other hand, this memory is located in a part of area 1 in the physical addr ess space. when this memory is accessed from the physical address space, addresses in which the upper three bits are 0 in addresses shown in table 7.1 are used. in the x-bus and y-bus addr ess spaces, addresses in which the upper 16 bits are ignored in addresses of x memory and y memory shown in table 7.1 are used. ?
section 7 x/y memory rev. 2.00 dec. 07, 2005 page 232 of 950 rej09b0079-0200 ? > > > >
section 7 x/y memory rev. 2.00 dec. 07, 2005 page 233 of 950 rej09b0079-0200 privileged dsp mode (sr. md = 1 and sr.dsp = 1): the x/y memory can be accessed by the dsp directly from space p2. the mmu can be used to map the logical addresses in spaces p0 and p3 to this memory. user dsp mode (sr.md = 0 and sr.dsp = 1): the x/y memory can be accessed by the dsp directly from space uxy. the mmu can be used to map the logical addresses in sp ace u0 to this memory. 7.2.3 access from dmac, e-dmac, and ipsec the x/y memory is always accessed by the dmac, e-dmac, and ipsec via the i bus, which is a physical address bus. addresses in which the upper three bits are 0 in addresses shown in table 7.1 must be used. 7.3 usage notes 7.3.1 page conflict in the event of simultaneous accesses to the same page from different buses, the conflict on the pages occurs. although each access is completed corr ectly, this kind of co nflict tends to lower x/y memory accessibility. therefore it is advisable to provide software measures to prevent such conflict as far as possible. for example, conflict will not arise if different memory or different pages are accessed by each bus. 7.3.2 bus conflict the i bus is shared by several bus master mo dules. when the x/y memo ry is accessed via the i bus, a conflict between the other i-bus master modules may occur on the i bus. this kind of conflict tends to lower x/y memo ry accessibility. therefore it is ad visable to provide software measures to prevent such conflic t as far as possible. for exampl e, by accessing the x/y memory by the cpu not via the i bus but directly from space p2 or uxy, conflict on the i bus can be prevented. 7.3.3 mmu and cache settings when the x/y memory is accessed via the i bus using the cache from the cpu and dsp, correct operation cannot be guaranteed. if the x/y me mory is accessed while the cache is enabled (ccr1.ce = 1), it is advisable to access the x/y me mory via the l bus from space p2 or uxy. if the x/y memory is accessed from space p0, p3, or u0, it is advi sable to access the x/y memory
section 7 x/y memory rev. 2.00 dec. 07, 2005 page 234 of 950 rej09b0079-0200 via the i bus, which does not use the cache, with mmu setting enabled (mmucr.at = 1) and cache disabled (c bit = 0) as page attributes. since access using the mmu occurs via the i bus, several cycles are necessary (the number of necessary cycles varies according to the ratio between the internal clock (i setting logical address space and access enabled or disabled ccr1.ce mmucr.at p0, u0 p1 p2, uxy p3 0 0 b b a b 0 1 b b a b 1 0 x x a x 1 1 c x a c [legend] a: accessible (recommended) b: accessible c: accessible (note that mmu page attribut e must be specified as cache disabled by clearing the c bit to 0.) x: not accessible 7.3.4 sleep mode in sleep mode, i bus master modules such as the dmac, e-dmac and ipsec cannot access the x/y memory. 7.3.5 address error if writing that may causes an addr ess error is performed on the x/ y memory, the contents of the x/y memory are not guaranteed.
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 235 of 950 rej09b0079-0200 section 8 interrupt controller (intc) the interrupt controller (intc) ascertains the prior ity of interrupt sources and controls interrupt requests to the cpu. the intc registers set the order of priority of each interrupt, allowing the user to process interr upt requests according to the user-set priority. 8.1 features the intc has the following features: ? ? ? ? irqout pin) the bus mastership can be requested by notifying the external bus master that the external interrupt and on-chip peripheral module interrupt requests have been generated. 8.1.1 block diagram figure 8.1 shows a block diagram of the intc.
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 236 of 950 rej09b0079-0200 dmac scif0/1 e-dmac ipsec siof0/1 tmu rtc wdt ref h-udi 8 input/output control priority identifier com- parator interrupt request sr cpu bus interface internal bus interrupt controller i3 i2 i1 i0 (interrupt request) icrn irrn irq5 to irq0 nmi irqout iprn [legend] dmac: scif0/1: e-dmac: ipsec: siof0/1: tmu: rtc: wdt: ref: h-udi: icrn: iprn: irrn: sr: direct memory access controller serial communication interface with fifo direct memory access controller for ethernet controller ip security accelerator serial i/o with fifo timer unit realtime clock unit watchdog timer refresh request in bus state controller user-debugging interface interrupt control registers 0, 1 interrupt priority registers a to i interrupt request registers 0 to 5, 7 and 8 status register irl3 to irl0 4 (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) figure 8.1 block diagram of intc
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 237 of 950 rej09b0079-0200 8.2 input/output pins table 8.1 shows the intc pin configuration. table 8.1 pin configuration name abbreviation i/o description nonmaskable interrupt input pin nmi input input of interrupt request signal, not maskable by the interrupt mask bits in sr interrupt input pins irq5 to irq0 irl3 to irl0 * 1 input input of interrupt request signals bus mastership request output pin * 2 irqout output notifies that an interrupt request has generated notes: 1. the irl3 to irl0 pins and the irq3 to irq0 cannot be used simultaneously because these pins are multiplexed with the irq3 to irq0 pins. 2. when the nmi or h-udi interrupt requests are generated and the response time of the cpu is short, this pin may not be asserted. 8.3 interrupt sources there are four types of interrupt sources: nmi, irq, irl, and on-chip peripheral modules. each interrupt has a priority level (0 to 16), with 1 th e lowest and 16 the highest. priority level 0 masks an interrupt, so the interrupt request is ignored. 8.3.1 nmi interrupt the nmi interrupt has the highest priority leve l of 16. when the blmsk bit in the interrupt control register 1 (icr1) is set to 1 or the bl bit in the status register (sr) is 0 and the mai bit in icr1 is 0, nmi interrupts are accepted. nmi inte rrupts are edge-detected . in sleep or standby mode, the interrupt is accepted re gardless of the bl setting. the nmi edge select bit (nmie) in the interrupt control register 0 (icr0) is used to select either rising or falling edge detection. when using edge-input detection for nmi interrupts, a pulse width of at least two p
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 238 of 950 rej09b0079-0200 8.3.2 irq interrupts irq interrupts are input by level or edge from pins irq0 to irq5. the priority level can be set by interrupt priority registers c and d (iprc and iprd) in a range from 0 to 15. when using edge-sensing for irq interrupts, clear the interrupt source by having software read 1 from the corresponding bit in irr0, then write 0 to the bit. when icr1 is rewritten, irq interrupts may be mistakenly detected, depending on the irq pin states. to prevent this, rewrite th e register while interrupts are ma sked, then release the mask after clearing the illegal interrupt by writing 0 to interrupt request register 0 (irr0). edge input interrupt detection requires input of a pulse width of more than two cycles on a p clock basis. when using level-sensing for irq interrupts, the pin levels must be retained until the cpu samples the pins. therefore, the interrupt source must be cleared by the interrupt handler. the interrupt mask bits (i3 to i0) in the status register (sr) are not affected by irq interrupt handling. irq interrupts can be used for recovering from standby when the corresponding interrupt level is higher than that of bits i3 to i0 in sr. (however, only when the rtc is used, recovering from standby by using the clock for the rtc is enabled.) 8.3.3 irl interrupts irl interrupts are input by the irl3 to irl0 pins as level. the priority level is the higher level that is indicated by the irl3 to irl0 pins. when the values of the irl3 to irl0 pins are 0 (b irl pins and interrupt level. irl interrupts are included with a noise canceler f unction and detected when the sampled levels of each peripheral module clock keep the same value fo r 2 cycles. this prevents sampling error level in irl pin changing. in standby mode, a noise canceler is handled by the rtc clock (32 khz) because the peripheral module clocks are halted. th erefore, when the rtc is not used, recovering from standby by irl interrupts cannot be executed in standby mode. the priority level of irl interrupts should be kept until an interrupt is accepted and its handling is started. however, changing to higher level is enabled.
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 239 of 950 rej09b0079-0200 the interrupt mask bits (i3 to i0) in the status re gister (sr) are not affect ed by the irl interrupt handling. priority encoder interrupt request irl3 to irl0 irl3 to irl0 4 sh7710 figure 8.2 example of irl interrupt connection 8.3.4 on-chip peripheral module interrupts on-chip peripheral module interrupts are generated by the following 14 modules: ? ? ? ? ? ? ? ? ? ?
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 240 of 950 rej09b0079-0200 the interrupt mask bits (i3 to i0) in the status register are not affected by on-chip peripheral module interrupt handling. 8.3.5 interrupt exceptio n handling and priority there are four types of interrup t sources: nmi, irq, irl, and on-chip peripheral modules. the priority of each interrupt source is set within prio rity levels 0 to 16; level 16 is the highest and level 1 is the lowest. when the priority is set to level 0, that interrupt is masked and the interrupt request is ignored. tables 8.2 and 8.3 list the codes for the interrupt event registers (intevt and intevt2) and the order of interrupt priority. each interrupt source is assigned a unique code by intevt or intevt2. the start address of the interrupt service routine is common for each interrupt source. this is why, for instance, the value of intevt or intevt2 is used as an offset at the start of the interrupt service routine and branched to in order to identify the interrupt source. irq interrupt and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each module by setting interrupt priority regi sters a to i (ipra to ipri). a reset assigns priority level 0 to irq and on-chip peripheral module interrupts. if the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in tables 8.2 and 8.3. table 8.2 interrupt except ion handling sources an d priority (irq mode) interrupt source interrupt code * 1 interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h 1c0 * 2 16 ? ? high h-udi h 5e0 * 2 15 ? ? irq0 h 600 * 3 0 to 15 (0) iprc (3 to 0) ? irq1 h 620 * 3 0 to 15 (0) iprc (7 to 4) ? irq2 h 640 * 3 0 to 15 (0) iprc (11 to 8) ? irq3 h 660 * 3 0 to 15 (0) iprc (15 to 12) ? irq4 h 680 * 3 0 to 15 (0) iprd (3 to 0) ? irq irq5 h 6a0 * 3 0 to 15 (0) iprd (7 to 4) ? low
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 241 of 950 rej09b0079-0200 interrupt source interrupt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority dei0 h 800 * 3 0 to 15 (0) high high dei1 h 820 * 3 0 to 15 (0) dei2 h 840 * 3 0 to 15 (0) dmac (1) dei3 h 860 * 3 0 to 15 (0) ipre (15 to12) low eri0 h 880 * 3 high rxi0 h 8a0 * 3 bri0 h 8c0 * 3 scif0 txi0 h 8e0 * 3 0 to 15 (0) ipre (11 to 8) low eri1 h 900 * 3 high rxi1 h 920 * 3 bri1 h 940 * 3 scif1 txi1 h 960 * 3 0 to 15 (0) ipre (7 to 4) low dei4 h b80 * 3 high dmac (2) dei5 h ba0 * 3 0 to 15 (0) iprf (11 to 8) low ipsec ipseci h be0 * 3 0 to 15 (0) iprf (15 to 12) ? eint0 h c00 * 3 0 to 15 (0) iprg (15 to 12) ? eint1 h c20 * 3 0 to 15 (0) iprg (11 to 8) ? e-dmac eint2 h c40 * 3 0 to 15 (0) iprg (7 to 4) ? eri0 h e00 * 3 high txi0 h e20 * 3 rxi0 h e40 * 3 siof0 cci0 h e60 * 3 0 to 15 (0) iprh (3 to 0) low eri1 h e80 * 3 high txi1 h ea0 * 3 rxi1 h ec0 * 3 siof1 cci1 h ee0 * 3 0 to 15 (0) ipri (7 to 4) low tmu0 tuni0 h 400 * 2 0 to 15 (0) ipra (15 to 12) ? tmu1 tuni1 h 420 * 2 0 to 15 (0) ipra (11 to 8) ? tmu2 tuni2 h 440 * 2 0 to 15 (0) ipra (7 to 4) ? low
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 242 of 950 rej09b0079-0200 interrupt source interrupt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority ati h 480 * 2 pri h 4a0 * 2 rtc cui h 4c0 * 2 0 to 15 (0) ipra (3 to 0) high low wdt iti h 560 * 2 0 to 15 (0) iprb (15 to 12) ? ref rcmi h 580 * 2 0 to 15 (0) iprb (11 to 8) ? high low notes: 1. intevt2 code 2. the code set in intevt is as same as intevt2. 3. the code that indica tes the interrupt level (h 200 to h 3c0) is set in intevt. for details on correspondence between the interrupt level and intevt, see table 8.4.
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 243 of 950 rej09b0079-0200 table 8.3 interrupt exce ption handling sources an d priority (irl mode) interrupt source interrupt code * 1 interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h 1c0 * 2 16 ? ? high h-udi h 5e0 * 2 15 ? ? irl irl[3:0] = b 0000 h 200 * 3 15 ? ? irl[3:0] = b 0001 h 220 * 3 14 ? ? irl[3:0] = b 0010 h 240 * 3 13 ? ? irl[3:0] = b 0011 h 260 * 3 12 ? ? irl[3:0] = b 0100 h 280 * 3 11 ? ? irl[3:0] = b 0101 h 2a0 * 3 10 ? ? irl[3:0] = b 0110 h 2c0 * 3 9 ? ? irl[3:0] = b 0111 h 2e0 * 3 8 ? ? irl[3:0] = b 1000 h 300 * 3 7 ? ? irl[3:0] = b 1001 h 320 * 3 6 ? ? irl[3:0] = b 1010 h 340 * 3 5 ? ? irl[3:0] = b 1011 h 360 * 3 4 ? ? irl[3:0] = b 1100 h 380 * 3 3 ? ? irl[3:0] = b 1101 h 3a0 * 3 2 ? ? irl[3:0] = b 1110 h 3c0 * 3 1 ? ? irq4 h 680 * 3 0 to 15 (0) iprd (3 to 0) ? irq irq5 h 6a0 * 3 0 to 15 (0) iprd (7 to 4) ? low
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 244 of 950 rej09b0079-0200 interrupt source interrupt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority dei0 h 800 * 3 0 to 15 (0) high high dei1 h 820 * 3 0 to 15 (0) dei2 h 840 * 3 0 to 15 (0) dmac (1) dei3 h 860 * 3 0 to 15 (0) ipre (15 to12) low eri0 h 880 * 3 high rxi0 h 8a0 * 3 bri0 h 8c0 * 3 scif0 txi0 h 8e0 * 3 0 to 15 (0) ipre (11 to 8) low eri1 h 900 * 3 high rxi1 h 920 * 3 bri1 h 940 * 3 scif1 txi1 h 960 * 3 0 to 15 (0) ipre (7 to 4) low dei4 h b80 * 3 high dmac (2) dei5 h ba0 * 3 0 to 15 (0) iprf (11 to 8) low ipsec ipseci h be0 * 3 0 to 15 (0) iprf (15 to 12) ? eint0 h c00 * 3 0 to 15 (0) iprg (15 to 12) ? eint1 h c20 * 3 0 to 15 (0) iprg (11 to 8) ? e-dmac eint2 h c40 * 3 0 to 15 (0) iprg (7 to 4) ? eri0 h e00 * 3 high txi0 h e20 * 3 rxi0 h e40 * 3 siof0 cci0 h e60 * 3 0 to 15 (0) iprh (3 to 0) low eri1 h e80 * 3 high txi1 h ea0 * 3 rxi1 h ec0 * 3 siof1 cci1 h ee0 * 3 0 to 15 (0) ipri (7 to 4) low tmu0 tuni0 h 400 * 2 0 to 15 (0) ipra (15 to 12) ? tmu1 tuni1 h 420 * 2 0 to 15 (0) ipra (11 to 8) ? tmu2 tuni2 h 440 * 2 0 to 15 (0) ipra (7 to 4) ? low
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 245 of 950 rej09b0079-0200 interrupt source interrupt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority ati h 480 * 2 high high pri h 4a0 * 2 rtc cui h 4c0 * 2 0 to 15 (0) ipra (3 to 0) low wdt iti h 560 * 2 0 to 15 (0) iprb (15 to 12) ? ref rcmi h 580 * 2 0 to 15 (0) iprb (11 to 8) ? low notes: 1. intevt2 code 2. the code set in intevt is as same as intevt2. 3. the code that indica tes the interrupt level (h 200 to h 3c0) is set in intevt. for details on correspondence between the interrupt level and intevt, see table 8.4. table 8.4 interrupt le vel and intevt code interrupt level intevt code 15 h 200 14 h 220 13 h 240 12 h 260 11 h 280 10 h 2a0 9 h 2c0 8 h 2e0 7 h 300 6 h 320 5 h 340 4 h 360 3 h 380 2 h 3a0 1 h 3c0
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 246 of 950 rej09b0079-0200 8.4 register descriptions the intc has the following regist ers. for details on register addresses and register access size, refer to section 24, list of registers. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 247 of 950 rej09b0079-0200 bit bit name initial value r/w description 15 14 13 12 ? ? ? ? 0 0 0 0 r/w r/w r/w r/w 11 10 9 8 ? ? ? ? 0 0 0 0 r/w r/w r/w r/w these bits set the priority level for each interrupt source in 4-bit units. for details, see table 8.5, interrupt sources and ipra to ipri. 7 6 5 4 ? ? ? ? 0 0 0 0 r/w r/w r/w r/w 3 2 1 0 ? ? ? ? 0 0 0 0 r/w r/w r/w r/w table 8.5 interrupt sources and ipra to ipri register bits 15 to 12 bits 11 to 8 bits 7 to 4 bits 3 to 0 ipra tmu0 tmu1 tmu2 rtc iprb wdt ref reserved * reserved * iprc irq3 irq2 irq1 irq0 iprd reserved * reserved * irq5 irq4 ipre dmac (1) scif0 scif1 reserved * iprf ipsec dmac (2) reserved * reserved * iprg e-dmac (1) e-dmac (2) e-dmac (3) reserved * iprh reserved * reserved * reserved * siof0 ipri reserved * reserved * siof1 reserved * note: * always read as 0. the write value should always be 0.
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 248 of 950 rej09b0079-0200 as shown in table 8.5, on-chip peripheral module or irq interrupts are assigned to four 4-bit groups in each register. these 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from h'0 (0000) to h'f (1111). setting h'0 means priority level 0 (masking is requested); h'f means priority level 15 (the highest level). 8.4.2 interrupt contro l register 0 (icr0) icr0 is a register that sets the input signal detec tion mode of external interrupt input pin nmi, and indicates the input signal level at the nmi pin. this register is initialized to h'0000 or h'8000 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 15 nmil 0/1 * r nmi input level sets the level of the signa l input at the nmi pin. this bit can be read from to determine the nmi pin level. this bit cannot be modified. 0: nmi input level is low 1: nmi input level is high 14 13 12 11 10 9 ? ? ? ? ? ? 0 0 0 0 0 0 r r r r r r reserved these bits are always read as 0. the write value should always be 0. 8 nmie 0 r/w nmi edge select selects whether the falling or rising edge of the interrupt request signal at the nmi pin is detected. 0: interrupt request is detected on falling edge of nmi pin input 1: interrupt request is detected on rising edge of nmi pin input
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 249 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 r r r r r r r r reserved these bits are always read as 0. the write value should always be 0. note: * when nmi input is high, 0 when nmi input is low. 8.4.3 interrupt contro l register 1 (icr1) icr1 is a 16-bit register that specifies the detection mode for external interrupt input pins irq0 to irq5 individually: rising edge, falling edge, high level, or low level. this register is initialized to h bit bit name initial value r/w description 15 mai 0 r/w all interrupt mask when this bit is set to 1, all interrupt requests are masked while low level is input to the nmi pin. in standby mode, an nmi interrupt is masked. 0: when the nmi pin is low, all interrupt requests are not masked 1: when the nmi pin is low, all interrupt requests are masked 14 irqlvl 1 r/w interrupt request level detection enables or disables the use of pins irq3 to irq0 as four independent interrupt pins. the irq4 and irq5 pins are not affected. 0: use of pins irq3 to irq0 as four independent interrupt pins enabled 1: use of pins irl3 to irl0 as encoded 15 level interrupt pins
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 250 of 950 rej09b0079-0200 bit bit name initial value r/w description 13 blmsk 0 r/w bl bit mask when the bl bit in sr is set to 1, this bit specifies whether an nmi interrupt is masked or not. 0: when the bl bit is set to 1, an nmi interrupt is masked 1: an nmi interrupt is accepted regardless of the bl bit setting 12 ? 0 r reserved this bit is always read as 0. the write value should always be 0. irqn sense select these bits select whether interrupt request signals corresponding to pins irq5 to irq0 are detected by a rising edge, falling edge, high level, or low level. bit 2n+1 bit 2n irqn1s irqn0s 0 0 interrupt request is detected on falling edge of irqn input 0 1 interrupt request is detected on rising edge of irqn input 1 0 interrupt request is detected on low level of irqn input 1 1 interrupt request is detected on high level of irqn input 11 10 9 8 7 6 5 4 3 2 1 0 irq51s irq50s irq41s irq40s irq31s irq30s irq21s irq20s irq11s irq10s irq01s irq00s 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w legend n=0 to 5
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 251 of 950 rej09b0079-0200 8.4.4 interrupt requ est register 0 (irr0) irr0 is an 8-bit register that indicates interrupt requests from external input pins irq5 to irq0. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 6 ? ? 0 0 r r reserved these bit are always read as 0. the write value should always be 0. 5 4 3 2 1 0 irq5r irq4r irq3r irq2r irq1r irq0r 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w irqn interrupt request indicates whether there is interrupt request input to the irqn pin. when edge-detection mode is set for irqn, an interrupt request is cleared by writing 0 to the irqnr bit after reading irqnr = 1. when level-detection mode is set for irqn, an interrupt request is set/cleared by only 1/0 input to the irqn pin. irqnr 0: no interrupt request input to irqn pin 1: interrupt request input to irqn pin legend: n = 0 to 5 8.4.5 interrupt requ est register 1 (irr1) irr1 is an 8-bit register that indicates whethe r interrupt requests from the dmac and the scif0 are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 txi0r 0 r txi0 interrupt request indicates whether the txi0 (scif0) interrupt request is generated. 0: txi0 interrupt request is not generated 1: txi0 interrupt request is generated
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 252 of 950 rej09b0079-0200 bit bit name initial value r/w description 6 bri0r 0 r bri0 interrupt request indicates whether the bri0 (scif0) interrupt request is generated. 0: bri0 interrupt request is not generated 1: bri0 interrupt request is generated 5 rxi0r 0 r rxi0 interrupt request indicates whether the rxi0 (scif0) interrupt request is generated. 0: rxi0 interrupt request is not generated 1: rxi0 interrupt request is generated 4 eri0r 0 r eri0 interrupt request indicates whether the eri0 (scif0) interrupt request is generated. 0: eri0 interrupt request is not generated 1: eri0 interrupt request is generated 3 dei3r 0 r dei3 interrupt request indicates whether the dei3 (dmac) interrupt request is generated. 0: dei3 interrupt request is not generated 1: dei3 interrupt request is generated 2 dei2r 0 r dei2 interrupt request indicates whether the dei2 (dmac) interrupt request is generated. 0: dei2 interrupt request is not generated 1: dei2 interrupt request is generated 1 dei1r 0 r dei1 interrupt request indicates whether the dei1 (dmac) interrupt request is generated. 0: dei1 interrupt request is not generated 1: dei1 interrupt request is generated 0 dei0r 0 r dei0 interrupt request indicates whether the dei0 (dmac) interrupt request is generated. 0: dei0 interrupt request is not generated 1: dei0 interrupt request is generated
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 253 of 950 rej09b0079-0200 8.4.6 interrupt requ est register 2 (irr2) irr2 is an 8-bit register that indicates whether interrupt requests from the scif1 are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 txi1r 0 r txi1 interrupt request indicates whether the txi1 (scif1) interrupt request is generated. 0: txi1 interrupt request is not generated 1: txi1 interrupt request is generated 2 bri1r 0 r bri1 interrupt request indicates whether the bri1 (scif1) interrupt request is generated. 0: bri1 interrupt request is not generated 1: bri1 interrupt request is generated 1 rxi1r 0 r rxi1 interrupt request indicates whether the rxi1 (scif1) interrupt request is generated. 0: rxi1 interrupt request is not generated 1: rxi1 interrupt request is generated 0 eri1r 0 r eri1 interrupt request indicates whether the eri1 (scif1) interrupt request is generated. 0: eri1 interrupt request is not generated 1: eri1 interrupt request is generated
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 254 of 950 rej09b0079-0200 8.4.7 interrupt requ est register 3 (irr3) irr3 is an 8-bit register that indicates whethe r interrupt requests from the rtc are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 cuir 0 r cui interrupt request indicates whether the cui (rtc) interrupt request is generated. 0: cui interrupt request is not generated 1: cui interrupt request is generated 1 prir 0 r pri interrupt request indicates whether the pri (rtc) interrupt request is generated. 0: pri interrupt request is not generated 1: pri interrupt request is generated 0 atir 0 r ati interrupt request indicates whether the ati (rtc) interrupt request is generated. 0: ati interrupt request is not generated 1: ati interrupt request is generated
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 255 of 950 rej09b0079-0200 8.4.8 interrupt requ est register 4 (irr4) irr4 is an 8-bit register that indicates whethe r interrupt requests from the tmu2, tmu1, tmu0, wdt, and ref are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 ? 0 r reserved this bit always read as 0. the write value should always be 0. 6 tuni2r 0 r tuni2 interrupt request indicates whether the tuni2 (tmu2) interrupt request is generated. 0: tuni2 interrupt requ est is not generated 1: tuni2 interrupt request is generated 5 tuni1r 0 r tuni1i nterrupt request indicates whether the tuni1 (tmu1) interrupt request is generated. 0: tuni1 interrupt requ est is not generated 1: tuni1 interrupt request is generated 4 tuni0r 0 r tuni0 interrupt request indicates whether the tuni0 (tmu0) interrupt request is generated. 0: tuni0 interrupt requ est is not generated 1: tuni0 interrupt request is generated 3 itir 0 r iti interrupt request indicates whether the iti (wdt) interrupt request is generated. 0: iti interrupt request is not generated 1: iti interrupt request is generated 2 1 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0.
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 256 of 950 rej09b0079-0200 bit bit name initial value r/w description 0 rcmir 0 r rcmi interrupt request indicates whether the rcmi (ref) interrupt request is generated. 0: rcmi interrupt request is not generated 1: rcmi interrupt request is generated 8.4.9 interrupt requ est register 5 (irr5) irr5 is an 8-bit register that indicates whethe r interrupt requests from the ipsec, dmac, and e- dmac are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 ipsecir 0 r ipseci interrupt request indicates whether the ipseci (ipsec) interrupt request is generated. 0: ipseci interrupt requ est is not generated 1: ipseci interrupt request is generated 6 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 5 dei5r 0 r dei5 interrupt request indicates whether the dei5 (dmac) interrupt request is generated. 0: dei5 interrupt request is not generated 1: dei5 interrupt request is generated 4 dei4r 0 r dei4 interrupt request indicates whether the dei4 (dmac) interrupt request is generated. 0: dei4 interrupt request is not generated 1: dei4 interrupt request is generated 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 257 of 950 rej09b0079-0200 bit bit name initial value r/w description 2 eint2r 0 r eint2 interrupt request indicates whether the eint2 (e-dmac) interrupt request is generated. 0: eint2 interrupt requ est is not generated 1: eint2 interrupt request is generated 1 eint1r 0 r eint1 interrupt request indicates whether the eint1 (e-dmac) interrupt request is generated. 0: eint1 interrupt requ est is not generated 1: eint1 interrupt request is generated 0 eint0r 0 r eint0 interrupt request indicates whether the eint0 (e-dmac) interrupt request is generated. 0: eint0 interrupt requ est is not generated 1: eint0 interrupt request is generated 8.4.10 interrupt requ est register 7 (irr7) irr7 is an 8-bit register that indicates whether an interrupt request from the siof0 is generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 cci0r 0 r cci0 interrupt request indicates whether the cci0 (siof0) interrupt request is generated. 0: cci0 interrupt request is not generated 1: cci0 interrupt request is generated 6 rxi0r 0 r rxi0 interrupt request indicates whether the rxi0 (siof0) interrupt request is generated. 0: rxi0 interrupt request is not generated 1: rxi0 interrupt request is generated
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 258 of 950 rej09b0079-0200 bit bit name initial value r/w description 5 txi0r 0 r txi0 interrupt request indicates whether the txi0 (siof0) interrupt request is generated. 0: txi0 interrupt request is not generated 1: txi0 interrupt request is generated 4 eri0r 0 r eri0 interrupt request indicates whether the eri0 (siof0) interrupt request is generated. 0: eri0 interrupt request is not generated 1: eri0 interrupt request is generated 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8.4.11 interrupt requ est register 8 (irr8) irr8 is an 8-bit register that indicates whether interrupt requests from the siof1 are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 cci1r 0 r cci1 interrupt request indicates whether the cci1 (siof1) interrupt request is generated. 0: cci1 interrupt request is not generated 1: cci1 interrupt request is generated 6 rxi1r 0 r rxi1 interrupt request indicates whether the rxi1 (siof1) interrupt request is generated. 0: rxi1 interrupt request is not generated 1: rxi1 interrupt request is generated
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 259 of 950 rej09b0079-0200 bit bit name initial value r/w description 5 txi1r 0 r txi1 interrupt request indicates whether the txi1 (siof1) interrupt request is generated. 0: txi1 interrupt request is not generated 1: txi1 interrupt request is generated 4 eri1r 0 r eri1 interrupt request indicates whether the eri1 (siof1) interrupt request is generated. 0: eri1 interrupt request is not generated 1: eri1 interrupt request is generated 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 260 of 950 rej09b0079-0200 8.5 operation 8.5.1 interrupt sequence the sequence of interrupt operations is described below. figure 8.3 is a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest-prio rity interrupt from the interrupt requests sent, following the priority levels set in the interrupt priority registers a to i (ipra to ipri). lower priority interrupts are held pending. if two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest priority is selected, according to tables 8.2 and 8.3, interrupt exception handling sources and priority. 3. the priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (i3 to i0) in the status register (sr) of the cpu. if the request priority level is higher than the level in bits i3 to i0, th e interrupt controller accept s the interrupt and sends an interrupt request signal to the cpu. 4. detection timing: the intc operates, and notifies the cpu of interrupt requests, in synchronization with the peripheral clock (p
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 261 of 950 rej09b0079-0200 i3 to i0: interrupt mask bits in status register (sr) program execution state interrupt generated? sr.bl=0 or sleep mode? yes yes yes yes yes yes yes yes yes no no no no no no no no no nmi? level 15 interrupt? set interrupt source in intevt, intevt2 save sr to ssr; save pc to spc set bl/md/rb bit in sr to 1 branch to exception handler i3 to i0 level 14 or lower? level 14 interrupt? i3 to i0 level 13 or lower? level 1 interrupt? i3 to i0 level 0? figure 8.3 interrupt operation flowchart
section 8 interrupt controller (intc) rev. 2.00 dec. 07, 2005 page 262 of 950 rej09b0079-0200 8.5.2 multiple interrupts when handling multiple interrupts, an interrupt handler should include the following procedures: 1. branch to a specific interrupt handler corresponding to a code set in intevt or intevt2. the code in intevt or intevt2 can be used as an offset for bran ching to the specific handler. 2. clear the interrupt source in each specific handler. 3. save ssr and spc to memory. 4. clear the bl bit in sr, and set the accepted inte rrupt level in the interr upt mask bits in sr. 5. handle the interrupt. 6. execute the rte instruction. when these procedures are followed in order, an interrupt of high er priority than the one being handled can be accepted after clearin g the bl bit in step 4. see fi gure 8.3 on a sa mple interrupt operation flowchart.
section 9 user break controller ubcs300b_000020020900 rev. 2.00 dec. 07, 2005 page 263 of 950 rej09b0079-0200 section 9 user break controller the user break controller (ubc) provides functions that simplify program debugging. these functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. break conditions that can be set in the ubc are instruction fetch or data read/write access, data si ze, data contents, address value, and stop timing in the case of instruction fetch. 9.1 features the ubc has the following features: 1. the following break comparison conditions can be set. number of break channels: two channels (channels a and b) user break can be requested as either the independent or sequential condition on channels a and b (sequential break setting: channel a and then channel b match with break conditions, but not in the same bus cycle). ? ? ? ? ?
section 9 user break controller rev. 2.00 dec. 07, 2005 page 264 of 950 rej09b0079-0200 3. in an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. ? ?
section 9 user break controller rev. 2.00 dec. 07, 2005 page 265 of 950 rej09b0079-0200 figure 9.1 shows a block diagram of the ubc. bbra bara bamra cpu state signals xab/yab iab lab mdb access comparator address comparator channel a access comparator address comparator data comparator pc trace control channel b bbrb betr basra basrb barb bamrb bdrb bdmrb brsr brdr brcr user break request ubc location ccn location ldb/idb/ xdb/ydb [legend] bbra: break bus cycle register a bara: break address register a bamra: break address mask register a basra: break asid register a bbrb: break bus cycle register b barb: break address register b bamrb: break address mask register b basrb: break asid register b bdrb: break data register b bdmrb: break data mask register b betr: execution times break register brsr: branch source register brdr: branch destination register brcr: break control register access control asid comparator asid comparator asid figure 9.1 block diagram of user break controller
section 9 user break controller rev. 2.00 dec. 07, 2005 page 266 of 950 rej09b0079-0200 9.2 register descriptions the user break controller has the following regist ers. for details on register addresses and access sizes, refer to section 24, list of registers. ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit bit name initial value r/w description 31 to 0 baa31 to baa 0 all 0 r/w break address a store the address on the la b or iab specifying break conditions of channel a.
section 9 user break controller rev. 2.00 dec. 07, 2005 page 267 of 950 rej09b0079-0200 9.2.2 break address ma sk register a (bamra) bamra is a 32-bit readable/writable register. bamr a specifies bits masked in the break address specified by bara. bit bit name initial value r/w description 31 to 0 bama31 to bama 0 all 0 r/w break address mask a specify bits masked in the channel a break address bits specified by bara (baa31?baa0). 0: break address bit baan of channel a is included in the break condition 1: break address bit baan of channel a is masked and is not included in the break condition note: n = 31 to 0 9.2.3 break bus cycl e register a (bbra) bbra is a 16-bit readable/writable register, which specifies (1) l bus cycle or i bus cycle, (2) instruction fetch or data access, (3) read or write , and (4) operand size in the break conditions of channel a. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 cda1 cda0 0 0 r/w r/w l bus cycle/i bus cycle select a select the l bus cycle or i bus cycle as the bus cycle of the channel a break condition. 00: condition comparison is not performed 01: the break condition is the l bus cycle 10: the break condition is the i bus cycle 11: the break condition is the l bus cycle
section 9 user break controller rev. 2.00 dec. 07, 2005 page 268 of 950 rej09b0079-0200 bit bit name initial value r/w description 5 4 ida1 ida0 0 0 r/w r/w instruction fetch/data access select a select the instruction fetch cycle or data access cycle as the bus cycle of the c hannel a break condition. 00: condition comparison is not performed 01: the break condition is the instruction fetch cycle 10: the break condition is the data access cycle 11: the break condition is the instruction fetch cycle or data access cycle 3 2 rwa1 rwa0 0 0 r/w r/w read/write select a select the read cycle or write cycle as the bus cycle of the channel a break condition. 00: condition comparison is not performed 01: the break condition is the read cycle 10: the break condition is the write cycle 11: the break condition is the read cycle or write cycle 1 0 sza1 sza0 0 0 r/w r/w operand size select a select the operand size of the bus cycle for the channel a break condition. 00: the break condition does not include operand size 01: the break condition is byte access 10: the break condition is word access 11: the break condition is longword access
section 9 user break controller rev. 2.00 dec. 07, 2005 page 269 of 950 rej09b0079-0200 9.2.4 break address register b (barb) barb is a 32-bit readable/writable register. barb sp ecifies the address used as a break condition in channel b. control bits cdb1, cdb0, xye, and xys in bbrb select one of the four address buses for break condition b. bit bit name initial value r/w description 31 to 0 bab31 to bab 0 all 0 r/w break address b stores an address which specifies a break condition in channel b. if the i bus or l bus is selected in bbrb, an iab or lab address is set in bab31 to bab0. if the x memory is selected in bbrb, the values in bits 15 to 1 in xab are set in bab31 to bab17. in this case, the values in bab16 to bab0 are arbitrary. if the y memory is selected in bbrb, the values in bits 15 to 1 in yab are set in bab15 to bab1. in this case, the values in bab31 to bab16, and babo are arbitrary. table 9.1 specifying break address register bus selection in bbrb bab31 to bab17 bab16 bab15 to bab1 bab0 l bus lab31 to lab0 i bus iab31 to iab0 x bus xab15 to xab1 don't care don't care don't care y bus don't care don't care yab15 to yab1 don't care
section 9 user break controller rev. 2.00 dec. 07, 2005 page 270 of 950 rej09b0079-0200 9.2.5 break address ma sk register b (bamrb) bamrb is a 32-bit readable/writable register. bam rb specifies bits masked in the break address specified by barb. bit bit name initial value r/w description 31 to 0 bamb31 to bamb 0 all 0 r/w break address mask b specifies bits masked in the break address of channel b specified by barb (bab31 to bab0). 0: break address babn of channel b is included in the break condition 1: break address babn of channel b is masked and is not included in the break condition note: n = 31 to 0 9.2.6 break data register b (bdrb) bdrb is a 32-bit readable/writable register. the control bits cdb1, cdb0, xye, and xys in bbrb select one of the four data buses for break condition b. bit bit name initial value r/w description 31 to 0 bdb31 to bdb0 all 0 r/w break data bit b stores data which specifies a break condition in channel b. if the i bus is selected in bbrb, the break data on idb is set in bdb31 to bdb0. if the l bus is selected in bbrb, the break data on ldb is set in bdb31 to bdb0. if the x memory is selected in bbrb, the break data in bits 15 to 0 in xdb is set in bdb31 to bdb16. in this case, the values in bdb15 to bdb0 are arbitrary. if the y memory is selected in bbrb, the break data in bits 15 to 0 in ydb are set in bdb15 to bdb0. in this case, the values in bdb31 to bdb16 are arbitrary.
section 9 user break controller rev. 2.00 dec. 07, 2005 page 271 of 950 rej09b0079-0200 table 9.2 specifying break data register bus selection in bbrb bdb31 to bdb16 bdb15 to bdb0 l bus ldb31 to ldb0 i bus idb31 to idb0 x bus xdb15 to xdb0 don't care y bus don't care ydb15 to ydb0 notes: 1. specify an operand size when including t he value of the data bus in the break condition. 2. when the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in bdrb as the break data. 3. set the data in bits 31 to 16 when includ ing the value of the data bus as an l-bus break condition for the movs.w @-as, ds, movs.w @as, ds, movs.w @as+, ds, or movs.w @as+ix, ds instruction. 9.2.7 break data mask register b (bdmrb) bdmrb is a 32-bit readable/writable register. bdmrb specifies bits masked in the break data specified by bdrb. bit bit name initial value r/w description 31 to 0 bdmb31 to bdmb 0 all 0 r/w break data mask b specifies bits masked in the break data of channel b specified by bdrb (bdb31 to bdb0). 0: break data bdbn of channel b is included in the break condition 1: break data bdbn of channel b is masked and is not included in the break condition note: n = 31 to 0 notes: 1. specify an operand size when including t he value of the data bus in the break condition. 2. when the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in bdrb as the break mask data in bdmrb. 3. set the mask data in bits 31 to 16 when including the value of the data bus as an l- bus break condition for the movs.w @-as, ds, movs.w @as, ds, movs.w @as+, ds, or movs.w @as+ix, ds instruction.
section 9 user break controller rev. 2.00 dec. 07, 2005 page 272 of 950 rej09b0079-0200 9.2.8 break bus cycle register b (bbrb) bbrb is a 16-bit readable/writable register, which specifies (1) x bus or y bus, (2) l bus cycle or i bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel b. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 xye 0 r/w selects the x memory bus or y memory bus as the channel b break condition. note that this bit setting is enabled only when the l bus is selected with the cdb1 and cdb0 bits. selection between the x memory bus and y memory bus is done by the xys bit. 0: selects l bus for the channel b break condition 1: selects x/y memory bus for the channel b break condition 8 xys 0 r/w selects the x bus or the y bus as the bus of the channel b break condition. 0: selects the x bus for the channel b break condition 1: selects the y bus for the channel b break condition 7 6 cdb1 cdb0 0 0 r/w r/w l bus cycle/i bus cycle select b select the l bus cycle or i bus cycle as the bus cycle of the channel b break condition. 00: condition comparison is not performed 01: the break condition is the l bus cycle 10: the break condition is the i bus cycle 11: the break condition is the l bus cycle
section 9 user break controller rev. 2.00 dec. 07, 2005 page 273 of 950 rej09b0079-0200 bit bit name initial value r/w description 5 4 idb1 idb0 0 0 r/w r/w instruction fetch/data access select b select the instruction fetch cycle or data access cycle as the bus cycle of the c hannel b break condition. 00: condition comparison is not performed 01: the break condition is the instruction fetch cycle 10: the break condition is the data access cycle 11: the break condition is the instruction fetch cycle or data access cycle 3 2 rwb1 rwb0 0 0 r/w r/w read/write select b select the read cycle or write cycle as the bus cycle of the channel b break condition. 00: condition comparison is not performed 01: the break condition is the read cycle 10: the break condition is the write cycle 11: the break condition is the read cycle or write cycle 1 0 szb1 szb0 0 0 r/w r/w operand size select b select the operand size of the bus cycle for the channel b break condition. 00: the break condition does not include operand size 01: the break condition is byte access 10: the break condition is word access 11: the break condition is longword access
section 9 user break controller rev. 2.00 dec. 07, 2005 page 274 of 950 rej09b0079-0200 9.2.9 break control register (brcr) brcr sets the following conditions: 1. channels a and b are used in two independent channel conditions or under the sequential condition. 2. a break is set before or after instruction execution. 3. specify whether to include the number of execu tion times on channel b in comparison conditions. 4. determine whether to include data bus on channel b in comparison conditions. 5. enable pc trace. 6. enable asid check. brcr is a 32-bit readable/writable register that has break conditions match flags and bits for setting a variety of break conditions. bit bit name initial value r/w description 31 to 22 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 21 basma 0 r/w break asid mask a specifies whether bits in channel a break asid7 to asid0 (basa7 to basa0) which are set in basra are masked or not. 0: all basra bits are included in the break conditions and the asid is checked 1: all basra bits are not included in the break conditions and the asid is not checked 20 basmb 0 r/w break asid mask b specifies whether bits in channel b break asid7 to asid0 (basb7 to basb0) which are set in basrb are masked or not. 0: all basrb bits are included in the break conditions and the asid is checked 1: all basrb bits are not included in the break conditions and the asid is not checked
section 9 user break controller rev. 2.00 dec. 07, 2005 page 275 of 950 rej09b0079-0200 bit bit name initial value r/w description 19 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 scmfca 0 r/w l bus cycle condition match flag a when the l bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1 (not cleared to 0). in order to clea r this flag, write 0 into this bit. 0: the l bus cycle conditio n for channel a does not match 1: the l bus cycle conditio n for channel a matches 14 scmfcb 0 r/w l bus cycle condition match flag b when the l bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1 (not cleared to 0). in order to clea r this flag, write 0 into this bit. 0: the l bus cycle conditio n for channel b does not match 1: the l bus cycle conditio n for channel b matches 13 scmfda 0 r/w i bus cycle condition match flag a when the i bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1 (not cleared to 0). in order to clea r this flag, write 0 into this bit. 0: the i bus cycle condition for channel a does not match 1: the i bus cycle condition for channel a matches 12 scmfdb 0 r/w i bus cycle condition match flag b when the i bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1 (not cleared to 0). in order to clea r this flag, write 0 into this bit. 0: the i bus cycle condition for channel b does not match 1: the i bus cycle condition for channel b matches
section 9 user break controller rev. 2.00 dec. 07, 2005 page 276 of 950 rej09b0079-0200 bit bit name initial value r/w description 11 pcte 0 r/w pc trace enable 0: disables pc trace 1: enables pc trace 10 pcba 0 r/w pc break select a selects the break timing of th e instruction fetch cycle for channel a as before or after instruction execution. 0: pc break of channel a is set before instruction execution 1: pc break of channel a is set after instruction execution 9 8 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0. 7 dbeb 0 r/w data break enable b selects whether or not the data bus condition is included in the break condition of channel b. 0: no data bus condition is included in the condition of channel b 1: the data bus condition is included in the condition of channel b 6 pcbb 0 r/w pc break select b selects the break timing of th e instruction fetch cycle for channel b as before or after instruction execution. 0: pc break of channel b is set before instruction execution 1: pc break of channel b is set after instruction execution 5 4 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0.
section 9 user break controller rev. 2.00 dec. 07, 2005 page 277 of 950 rej09b0079-0200 bit bit name initial value r/w description 3 seq 0 r/w sequence condition select selects two conditions of channels a and b as independent or sequential conditions. 0: channels a and b are compared under independent conditions 1: channels a and b are compared under sequential conditions (channel a, then channel b) 2 1 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0. 0 etbe 0 r/w number of execution times break enable enables the execution-times break condition only on channel b. if this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution ti mes that is specified by betr. 0: the execution-times break condition is disabled on channel b 1: the execution-times break condition is enabled on channel b
section 9 user break controller rev. 2.00 dec. 07, 2005 page 278 of 950 rej09b0079-0200 9.2.10 execution times break register (betr) betr is a 16-bit readable/writable register. when the execution-times break condition of channel b is enabled, this register specifies the numb er of execution times to make the break. the maximum number is 2 12 ? 1 times. when a break condition is satisfied, it decreases betr. a break is issued when the break condition is satisfied after betr becomes h'0001. bit bit name initial value r/w description 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 bet11 to bet0 all 0 r/w number of execution times note: when the instruction fetch cycle is specified as the break condition of the channel b, and its break condition is triggered by the following instructions, the betr is decremented by the following value (not by one). instruction decrement value instruction decrement value rte dmuls.l rm,rn dmulu.l rm,rn mac.l @rm+,@rn mac.w @rm+,@rn mul.l rm,rn and.b #imm,@(r0,gbr) or.b #imm,@(r0,gbr) tas.b @rn tst.b #imm,@(r0,gbr) xor.b #imm,@(r0,gbr) ldc rm,sr ldc rm,gbr ldc rm,vbr ldc rm,ssr ldc rm,spc ldc rm,r0_bank ldc rm,r1_bank ldc rm,r2_bank ldc rm,r3_bank ldc rm,r4_bank ldc rm,r5_bank ldc rm,r6_bank ldc rm,r7_bank 4 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 ldc.l @rm+,sr ldc.l @rm+,gbr ldc.l @rm+,vbr ldc.l @rm+,ssr ldc.l @rm+,spc ldc.l @rm+,r0_bank ldc.l @rm+,r1_bank ldc.l @rm+,r2_bank ldc.l @rm+,r3_bank ldc.l @rm+,r4_bank ldc.l @rm+,r5_bank ldc.l @rm+,r6_bank ldc.l @rm+,r7_bank ldc.l @rn+,mod ldc.l @rn+,rs ldc.l @rn+,re ldc rn,mod ldc rn,rs ldc rn,re bsr label bsrf rm jsr @rm 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 2
section 9 user break controller rev. 2.00 dec. 07, 2005 page 279 of 950 rej09b0079-0200 9.2.11 branch source register (brsr) brsr is a 32-bit read-only register. brsr stores bits 27 to 0 in the address of the branch source instruction. brsr has the flag bit that is set to 1 when a branch occurs. this flag bit is cleared to 0 when brsr is read, the setting to enable pc trace is made, or brsr is initialized by a power-on reset. other bits are not initialized by a power-o n reset. the eight brsr registers have a queue structure and a stored register is shifted at every branch. bit bit name initial value r/w description 31 svf 0 r brsr valid flag indicates whether the branch source address is stored. when a branch source address is fetched, this flag is set to 1. this flag is cleared to 0 by reading from brsr. 0: the value of brsr register is invalid 1: the value of brsr register is valid 30 to 28 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 27 to 0 bsa27 to bsa0 ? r branch source address store bits 27 to 0 of the branch source address.
section 9 user break controller rev. 2.00 dec. 07, 2005 page 280 of 950 rej09b0079-0200 9.2.12 branch destination register (brdr) brdr is a 32-bit read-only register. brdr stores bits 27 to 0 in the address of the branch destination instruction. brdr has the flag bit that is set to 1 when a branch occurs. this flag bit is cleared to 0 when brdr is read, the setting to enab le pc trace is made, or brdr is initialized by a power-on reset. other bits are not initialized by a power-on reset. the eight brdr registers have a queue structure and a stored register is shifted at every branch. bit bit name initial value r/w description 31 dvf 0 r brdr valid flag indicates whether a branch destination address is stored. when a branch destin ation address is fetched, this flag is set to 1. this flag is cleared to 0 by reading brdr. 0: the value of brdr register is invalid 1: the value of brdr register is valid 30 to 28 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 27 to 0 bda27 to bda0 ? r branch destination address store bits 27 to 0 of the branch destination address. 9.2.13 break asid register a (basra) basra is an 8-bit readable/writable register that specifies asid wh ich becomes the break condition for channel a. basra is in ccn. bit bit name initial value r/w description 7 to 0 basa7 to basa0 ? r/w break asid a store asid (bits 7 to 0) which is the break condition for channel a.
section 9 user break controller rev. 2.00 dec. 07, 2005 page 281 of 950 rej09b0079-0200 9.2.14 break asid register b (basrb) basrb is an 8-bit readable/wr itable register that specifies asid which becomes the break condition for channel b. basrb is in ccn. bit bit name initial value r/w description 7 to 0 basb7 to basb0 ? r/w break asid b store asid (bits 7 to 0) which is the break condition for channel b. 9.3 operation 9.3.1 flow of the user break operation the flow from setting of break conditions to user break exception processing is described below: 1. the break addresses and corresponding asid are set in the break address registers (bara or barb) and break asid registers (basra or ba srb in ccn). the masked addresses are set in the break address mask regi sters (bamra or bamrb). the break data is set in the break data register (bdrb). the masked data is set in the break data mask register (bdmrb). the bus break conditions are set in the break bus cycle registers (bbra or bbrb). three groups of bbra or bbrb (l bus cycle/i bus cycle select, instruction fetch/data access select, and read/write select) are each set. no user break w ill be generated if even one of these groups is set with 00. the respective conditions are set in the bits of the break control register (brcr). make sure to set all registers related to breaks before setting bbra or bbrb. 2. when the break conditions are satisfied, the ubc sends a user break request to the cpu and sets the l bus condition match flag (scmfca or scmfcb) and the i bus condition match flag (scmfda or scmfdb) for the appropriat e channel. when the x/y memory bus is specified for channel b, scmfcb is used for the condition match flag. 3. the appropriate condition match flags (scmfca, scmfda, scmfcb, and scmfdb) can be used to check if the set conditions match or not. the matching of the conditions sets flags, but they are not reset. 0 must first be written to them before they can be used again. 4. there is a chance that the break set in channe l a and the break set in channel b occur around the same time. in this case, there will be onl y one break request to the cpu, but these two break channel match flags could be both set. 5. when selecting the i bus as the break condition, note the following:
section 9 user break controller rev. 2.00 dec. 07, 2005 page 282 of 950 rej09b0079-0200 ? ? ? ? ? ? ? ?
section 9 user break controller rev. 2.00 dec. 07, 2005 page 283 of 950 rej09b0079-0200 9.3.2 break on inst ruction fetch cycle 1. when l bus/instruction fetch/read/word or lo ngword is set in the break bus cycle register (bbra or bbrb), the break condition becomes the l bus instruction fetch cycle. whether it breaks before or after the execution of the inst ruction can then be sel ected with the pcba or pcbb bit of the break control regi ster (brcr) for the appropriate channel. if an instruction fetch cycle is set as a break condition, clear lsb in the break address register (bara or barb) to 0. a break cannot be generated as long as this bit is set to 1. 2. an instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. this means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). when this kind of break is set for the delay slot of a delayed branch instruction, the break is generated prior to execution of the delayed branch instruction. note: if a branch does not occur at a delay condition branch instruction, the subsequent instruction is not recognized as a delay slot. 3. when the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. as with pre-execution breaks, this cannot be used with overrun fetch instructions. when this kind of break is set for a delayed branch instruction and its delay slot, a break is not generated until the first instruction at the branch destination. 4. when an instruction fetch cycle is set for channel b, the break data register b (bdrb) is ignored. therefore, break data cannot be set for the break of the instruction fetch cycle. 5. if the i bus is set for a break of an instructi on fetch cycle, the condition is determined for the instruction fetch cycles on the i bus. for details, see 5 in section 9.3.1, flow of the user break operation. 9.3.3 break on data access cycle 1. if the l bus is specified as a break condition for data access br eak, condition comparison is performed for the logical addresses (and data ) accessed by the executed instructions, and a break occurs if the condition is satisfied. if the i bus is specified as a break condition, condition comparison is performed for the physical addresses (and data) of the data access cycles that are issued on the i bus by all bus masters including the cpu, and a break occurs if the condition is satisfied. for details on the cpu bus cycles issued on the i bus, see 5 in section 9.3.1, flow of the user break operation. 2. the relationship between the data access cycle address and the comparison condition for each operand size is listed in table 9.3.
section 9 user break controller rev. 2.00 dec. 07, 2005 page 284 of 950 rej09b0079-0200 table 9.3 data access cycle addresses and operand size comparison conditions access size address compared longword compares break address register bits 31 to 2 to address bus bits 31 to 2 word compares break address register bits 31 to 1 to address bus bits 31 to 1 byte compares break address register bits 31 to 0 to address bus bits 31 to 0 this means that when address h'00001003 is set in the break address register (bara or barb), for example, the bus cycle in which th e break condition is satisfied is as follows (where other conditions are met). longword access at h'00001000 word access at h'00001002 byte access at h'00001003 3. when the data value is included in the break condition s on channel b: when the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle register b (bbrb). when data values are included in break conditions, a break is generated when the address conditions and data conditions both match. to specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register b (bdrb) and break data mask register b (bdmrb). when word or byte is set, bits 31 to 16 of bdrb and bdmrb are ignored. set the word data in bits 31 to 16 in bdrb and bdmrb when including the value of the data bus as a break condition for the movs.w @-as, ds, movs.w @as, ds, movs.w @as+, ds, or movs.w @as+ix, ds instruction (bits 15 to 0 are ignored). 4. access by a pref instruction is handled as read access in long word units without access data. therefore, if including the value of the data bus when a pref instruction is specified as a break condition, a break will not occur. 5. if the l bus is selected, a break occurs on en ding execution of the instruction that matches the break condition, and immediately before the next instruction is executed. however, when data is also specified as the break condition, the break may occur on ending execution of the instruction following the instruction that matche s the break condition. if the i bus is selected, the instruction at which the break will occur cannot be determined. when this kind of break occurs at a delayed branch inst ruction or its delay slot, the break may not actually take place until the first instruction at the branch destination.
section 9 user break controller rev. 2.00 dec. 07, 2005 page 285 of 950 rej09b0079-0200 9.3.4 break on x/y-memory bus cycle 1. the break condition on an x/y-memory bus cycl e is specified only in channel b. if the xye bit in bbrb is set to 1, the break address and br eak data on x/y-memory bus are selected. at this time, select the x-memory bus or y-memo ry bus by specifying th e xys bit in bbrb. the break condition cannot include both x-memory and y-memory at the same time. the break condition is applied to an x/ y-memory bus cycle by specify ing l bus/data access/read or write/word or no specified operand size in bits 7 to 0 in the break bus cycle register b (bbrb). 2. when an x-memory address is selected as the break condition, specify an x-memory address in the upper 16 bits in barb and bamrb. when a y-memory address is selected, specify a y-memory address in the lower 16 bits. specif ication of x/y-memory data is the same for bdrb and bdmrb. 3. the timing of a data access break for the x memory or y memory bus to occur is the same as a data access break of the l bus. for details, see 5 in section 9.3.3, break on data access cycle. 9.3.5 sequential break 1. by setting the seq bit in brcr to 1, the sequential break is issued when a channel b break condition matches after a channel a break conditio n matches. a user break is not generated even if a channel b break condition matches before a channel a break condition matches. when channels a and b conditions match at the same time, the sequential break is not issued. to clear the channel a condition match when a channel a condition match has occurred but a channel b condition match has not yet occurred in a sequential break specification, clear the seq bit in brcr to 0. 2. in sequential break specification, the l/i/x/ y bus can be selected and the execution times break condition can be also specified. for example, when the execution times break condition is specified, the break condition is satisfied when a channel b condition matches with betr = h'0001 after a channel a condition has matched.
section 9 user break controller rev. 2.00 dec. 07, 2005 page 286 of 950 rej09b0079-0200 9.3.6 value of saved program counter when a break occurs, the address of the instruction from where execution is to be resumed is saved in the spc, and the exception handling state is entered. if the l bus is specified as a break condition, the instruction at which the break should occur can be clearly determined (except for when data is included in the break condition). if the i bus is specified as a break condition, the instruction at which the break should occur cannot be clearly determined. 1. when instruction fetch (before instruction execution) is specified as a break condition: the address of the instruction that matched the break condition is saved in the spc. the instruction that matched the condition is not executed, and the break occurs before it. however when a delay slot instruction matches the condition, the address of the delayed branch instruction is saved in the spc. 2. when instruction fetch (after instruction ex ecution) is specified as a break condition: the address of the instruction following the in struction that matched the break condition is saved in the spc. the instruction that matches the condition is executed , and the break occurs before the next instruction is executed. however when a delayed branch instruction or delay slot matches the condition, these instructions ar e executed, and the branch destination address is saved in the spc. 3. when data access (address only) is specified as a break condition: the address of the instruction immediately after the instruction that matched the break condition is saved in the spc. the instruction that matches the condition is executed, and the break occurs before the next instruction is executed. however when a delay slot instruction matches the condition, the branch destination address is saved in the spc. 4. when data access (address + data) is specified as a break condition: when a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matc hed the break condition is saved in the spc. at which instruction the break occurs cannot be determined accurately. when a delay slot instruction matches the condition, the branch destination address is saved in the spc. if the instruction following the instru ction that matches the break condition is a branch instruction, the break may occur after the branch instruction or delay slot has finished. in this case, the branch destina tion address is saved in the spc.
section 9 user break controller rev. 2.00 dec. 07, 2005 page 287 of 950 rej09b0079-0200 9.3.7 pc trace 1. setting pcte in brcr to 1 enables pc traces. when branch (branch instruction, and interrupt exception) is generated, the bran ch source address and branch de stination address are stored in brsr and brdr, respectively. 2. the values stored in brsr and brdr are as given below due to the kind of branch. ? ? ?
section 9 user break controller rev. 2.00 dec. 07, 2005 page 288 of 950 rej09b0079-0200 bus cycle: l bus/instruction fe tch (before instruction executi on)/read (operand size is not included in the condition) the asid check is not included. a user break occurs after an instruction of address h'00000404 is executed or before instructions of addresses h'00008010 to h'00008016 are executed. ? ?
section 9 user break controller rev. 2.00 dec. 07, 2005 page 289 of 950 rej09b0079-0200 on channel a, no user break occurs since instru ction fetch is not a write cycle. on channel b, no user break occurs since instruction fetch is performed for an even address. ? ?
section 9 user break controller rev. 2.00 dec. 07, 2005 page 290 of 950 rej09b0079-0200 ? ?
section 9 user break controller rev. 2.00 dec. 07, 2005 page 291 of 950 rej09b0079-0200 ? ?
section 9 user break controller rev. 2.00 dec. 07, 2005 page 292 of 950 rej09b0079-0200 9.4 usage notes 1. the cpu can read from or wr ite to the ubc registers via the i bus. accordingly, during the period from executing an instruction to rewrite the ubc register till the new value is actually rewritten, the desired break may not occur. in or der to know the timing when the ubc register is changed, read from the last written register. instructions after then are valid for the newly written register value. 2. ubc cannot monitor access to the l bu s and i bus in the same channel. 3. note on specification of sequential break: a condition match occurs when a b-channel match occurs in a bus cycle after an a-channel match occurs in another bus cycle in sequential break setting. therefore, no break occurs even if a bus cycle, in which an a-channel match and a channel b match occur simultaneously, is set. 4. when a user break and another exception occu r at the same instruction, which has higher priority is determined according to the priority levels defined in table 4.1 in section 4, exception handling. if an exception with higher priority occurs, the user break is not generated. ? ? ?
section 9 user break controller rev. 2.00 dec. 07, 2005 page 293 of 950 rej09b0079-0200 6. note the following when a break occurs in a delay slot. if a pre-execution break is set at the delay slot instruction of the rte instruction, the break does not occur until the branch destination of the rte instruction. 7. user breaks are disabled during ubc module standby mode. do not read from or write to the ubc registers during ubc module standby mode; the values are not guaranteed. 8. when the repeat loop of the dsp extended function is used, even though a break condition is satisfied during execution of the entire repeat loop or several instructions in the repeat loop, the break may be held. for details, see section 4, exception handling.
section 9 user break controller rev. 2.00 dec. 07, 2005 page 294 of 950 rej09b0079-0200
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 295 of 950 rej09b0079-0200 section 10 power-down modes with the power-down modes, the operation of the cpu and same of on-chip peripheral modules are halted to reduce power consum ption. the power-down modes ar e canceled by interrupts or a reset. 10.1 overview 10.1.1 power-down modes this lsi has the following power-down modes and function: 1. sleep mode 2. software standby mode 3. module standby function table 10.1 shows the transition conditions for entering the modes from the program execution state, as well as the cpu and peripheral module states in each mode and the procedures for canceling each mode.
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 296 of 950 rej09b0079-0200 table 10.1 states of power-down modes state mode transition conditions cpg etherc e-dmac cpu cpu reg- ister on- chip memory on-chip periphera l modules pins external memory canceling procedure sleep mode execute sleep instruction with stby bit cleared to 0 in stbcr run halt held held run held refreshe d 1. interrupt 2. reset software standby mode execute sleep instruction with stby bit set to 1 in stbcr halt halt held held halt * 1 held self- refreshed 1. interrupt 2. reset module standby function set mstp bit to 1 in stbcr, stbcr2, and stbcr3 run run held held specified module halts * 2 refreshe d 1. clear mstp bit to 0 2. power- on reset notes: 1. the rtc runs when the start bit in rcr2 is set to 1. for details, see section 15, realtime clock (rtc). 2. depends on the on-chip peripheral modules. for details, see section 1, overview and pin function. 10.1.2 reset a reset is used at power-on or to re-execute from the initial state. this lsi supports two types of reset: power-on reset and manual reset. in power-on reset, any processing to be currently executed is terminated and any events not executed are cancel ed to execute reset pro cessing immediately. in manual reset, processing required to maintain external memory contents is continued. the following shows the conditions in which power-on reset or manual reset occurs. ? resetp pin. 2. the wdt counter overflows if the wdt starts counting while the wt/ it and rsts bits in wtcsr are set to 1 and cleared to 0, respectively. 3. an h-udi reset occurs. (for details on the h-udi reset, refer to section 23, user debugging interface (h-udi).)
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 297 of 950 rej09b0079-0200 ? resetm pin. 2. the wdt counter overflows if wdt starts counting while the wt/ it and rsts bits of the wtcsr are set to 1. note: immediately after a power-on reset or manu al reset, be sure to execute the following routine: mov.l #h'ffffff40, r1 mov.l #h'80000005, r0 mov.l #h'a4fc0008, r2 nop nop testcr2_set nop mov.b r0, @r1 mov.b r0, @r1 mov.l r0, @r2 nop nop nop mov.l @r2, r3 cmp/eq r3, r0 bf testcr2_set nop nop
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 298 of 950 rej09b0079-0200 10.1.3 input/output pins table 10.2 lists the pins used for the power-down modes. table 10.2 pin configuration pin name symbol i/o description processing state 1 status1 processing state 0 status0 o indicates the operating state of the processor. hh: reset hl: sleep mode lh: standby mode ll: normal operation power-on reset resetp i inputting low level signal to this pin cause a transition to power-on reset processing. manual reset resetm i inputting low level signal to this pin cause a transition to manual reset processing. note: h and l indicate high and low levels, respectively. the status1 and status0 pins indicate the pin status in this order. 10.2 register descriptions the following registers are used fo r the power-down modes. refer to section 24, list of registers, for the addresses and access size for these registers. ? ? ?
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 299 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 stby 0 r/w software standby specifies transition to software standby mode. 0: executing sleep instruct ion puts chip into sleep mode 1: executing sleep instru ction puts chip into software standby mode 6 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 mstp2 0 r/w module stop bit 2 when the mstp2 bit is set to 1, the supply of the clock to the tmu is halted. 0: tmu runs 1: clock supply to tmu halted 1 mstp1 0 r/w module stop bit 1 when the mstp1 bit is set to 1, the supply of the clock to the rtc is halted. 0: rtc runs 1: clock supply to rtc halted 0 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 300 of 950 rej09b0079-0200 10.2.2 standby control register 2 (stbcr2) stbcr2 is an 8-bit readable/writable register that controls the operation of modules in the power- down mode. this register is initialized to h bit bit name initial value r/w description 7 mstp10 0 r/w module stop bit 10 when the mstp10 bit is set to 1, the supply of the clock to the h-udi is halted. 0: h-udi runs 1: clock supply to h-udi halted 6 mstp9 0 r/w module stop bit 9 when the mstp9 bit is set to 1, the supply of the clock to the ubc is halted. 0: ubc runs 1: clock supply to ubc halted 5 mstp8 0 r/w module stop bit 8 when the mstp8 bit is set to 1, the supply of the clock to the dmac is halted. 0: dmac runs 1: clock supply to dmac halted 4 mstp7 0 r/w module stop bit 7 when the mstp7 bit is set to 1, the supply of the clock to the dsp is halted. 0: dsp runs 1: clock supply to dsp halted 3 mstp6 0 r/w module stop bit 6 when the mstp6 bit is set to 1, the supply of the clock to the tlb is halted. 0: tlb runs 1: clock supply to tlb halted
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 301 of 950 rej09b0079-0200 bit bit name initial value r/w description 2 mstp5 0 r/w module stop bit 5 when the mstp5 bit is set to 1, the supply of the clock to the cache memory is halted. 0: the cache memory runs 1: clock supply to the cache memory halted 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 mstp3 0 r/w module stop bit 3 when the mstp3 bit is set to 1, the supply of the clock to the x/y memory is halted. 0: the x/y memory runs 1: clock supply to the x/y memory halted 10.2.3 standby control register 3 (stbcr3) stbcr3 is an 8-bit readable/writable register that controls the operation of the peripheral modules in the power-down mode. this register is initialized to h bit bit name initial value r/w description 7 mstp37 0 r/w module stop bit 37 when the mstp37 bit is set to 1, the supply of the clock to the ipsec is halted. 0: ipsec runs 1: clock supply to ipsec halted 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 mstp33 0 r/w module stop bit 33 when the mstp33 bit is set to 1, the supply of the clock to the siof1 is halted. 0: siof1 runs 1: clock supply to siof1 halted
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 302 of 950 rej09b0079-0200 bit bit name initial value r/w description 2 mstp32 0 r/w module stop bit 32 when the mstp32 bit is set to 1, the supply of the clock to the siof0 is halted. 0: siof0 runs 1: clock supply to siof0 halted 1 mstp31 0 r/w module stop bit 31 when the mstp31 bit is set to 1, the supply of the clock to the scif1 is halted. 0: the scif1 runs 1: clock supply to the scif1 halted 0 mstp30 0 r/w module stop bit 30 when the mstp30 bit is set to 1, the supply of the clock to the scif0 is halted. 0: the scif0 runs 1: clock supply to the scif0 halted 10.3 operation 10.3.1 sleep mode transition to sleep mode: executing the sleep instruction wh en the stby bit in stbcr is 0 causes a transition from the prog ram execution state to sleep mode. although the cpu halts immediately after executing the s leep instruction, the contents of its internal registers remain unchanged. the on-chip peripheral modules continue to run in sleep mode and the clock continues to be output to the ckio pin. in sleep mode, a high signal and low signal are output from the status1 and status0 pins, respectively. canceling sleep mode: sleep mode is canceled by an interrupt (nmi, irq, irl, or on-chip peripheral module) or reset. interrupts are accepted in sleep mode even when the bl bit in sr is 1. if necessary, save spc and ssr to the stack before executing the sleep instruction. ?
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 303 of 950 rej09b0079-0200 ? module registers initialized registers retaining data interrupt controller (intc) ? all registers on-chip oscillation circuits ? all registers user break controller (ubc) ? all registers bus state controller (bsc) ? all registers timer unit (tmu) tstr registers other than tstr ipsec ? all registers i/o ports ? all registers h-udi ? all registers scif0/1 ? all registers siof0/1 ? all registers etherc, e-dmac ? all registers dmac ? all registers
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 304 of 950 rej09b0079-0200 the procedure for switching to software standby mode is as follows: 1. clear the tme bit in the wdt?s timer contro l register (wtcsr) to 0 to stop the wdt. 2. set the wdt?s timer counter (wtcnt) to 0 and the cks2 to cks0 bits in wtcsr to appropriate values to secure the specified oscillation settling time. 3. after the stby bit in stbcr is set to 1, a sleep instruction is executed. 4. software standby mode is entered and the cl ocks within the chip are halted. the status1 and status0 pins output low and high, respectively. canceling software standby mode: software standby mode is canceled by an interrupt (nmi, irq, irl, or rtc) or a reset. ?
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 305 of 950 rej09b0079-0200 wtcnt value h'ff h'80 time interrupt request wdt overflow and branch to interrupt handling routine crystal resonator settling time and pll synchronization time clear bit stbcr.stby before wtcnt reaches h'80. when stbcr. stby is cleared, wtcnt halts automatically. figure 10.1 canceling sta ndby mode with stbcr.stby ? resetp or resetm pin low until the clock oscillation settles. the internal clock will continue to be output to the ckio pin. 10.3.3 module standby function transition to module standby function: setting each mstp bit in the standby control registers to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. this function can be used to reduce the power consumption in normal or sleep mode. before a transition is made, the module should be disabled. in the module standby state, the functions of the external pins of the on-chip peripheral modules change depending on the on-chip peripheral module. for details, see section 1, overview and pin function. all of the register stat es are the same as those in standby mode. for details, see table 10.3. canceling module standby function: the module standby function can be canceled by clearing the mstp bits to 0, or by a power-on reset. to cancel the module standby function by clearing the corresponding mstp bit to 0, read the mstp bit to check the mstp bit was cleared correctly.
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 306 of 950 rej09b0079-0200 10.3.4 status pin change timings the status1 and status0 pin change timings are shown below. reset: ? ckio status pll setting time * 1 reset : hh (status1 = high, status0 = high) * 2 normal : ll (status1 = low, status0 = low) * 3 bcyc : bus clock cycle notes: * 2 * 2 * 1 0 to 30 bcyc * 3 0 to 5 bcyc normal reset normal * 3 resetp ckio2 figure 10.2 status output at power-on reset
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 307 of 950 rej09b0079-0200 ? ckio status * 1 : in manual reset, status = hh (reset) after the current bus cycle is completed and then internal reset is initiated. * 2 : reset: hh (status1 = high, status0 = high) * 3 : normal: ll (status1 = low, status0 = low) * 4 : bcyc: bus clock cycle notes * 3 * 3 * 2 0 to 30 bcyc * 4 0bcyc~ normal reset normal * 1, * 4 resetm ckio2 figure 10.3 status output at manual reset software standby mode: ? ckio status wdt count interrupt request oscillation stops wdt overflow * 1 standby : lh (status1 = low, status0 = high) * 2 normal : ll (status1 = low, status0 = low) notes: * 2 * 2 * 1 normal standby normal ckio2 figure 10.4 status output when softwa re standby mode is canceled by interrupt
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 308 of 950 rej09b0079-0200 ? ckio status * 1 if a standby mode is canceled by a power on reset, the wdt stops counting. resetp must be kept low for the pll oscillation stabilization time. * 2 reset : hh (status1 = high, status0 = high) * 3 standby : lh (status1 = low, status0 = high) * 4 normal : ll (status1 = low, status0 = low) * 5 bcyc : bus clock cycle notes: undefined * 4 * 4 * 1 * 2 0 to 30 bcyc * 5 0 to 10 bcyc normal * 3 standby reset normal * 5 resetp ckio2 oscillation stops reset figure 10.5 status output when software st andby mode is canceled by power-on reset ? ckio status * 1 * 2 * 3 * 4 * 5 if a standby mode is canceled by a power on reset, the wdt stops counting. resetm must be kept low for the pll oscillation stabilization time. reset : hh (status1 = high, status0 = high) standby : lh (status1 = low, status0 = high) normal : ll (status1 = low, status0 = low) bcyc : bus clock cycle oscillation stops reset notes: * 2 * 4 * 3 normal standby reset * 1 0 to 20 bcyc * 5 * 4 normal resetm ckio2 figure 10.6 status output when software standby mode is canceled by manual reset
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 309 of 950 rej09b0079-0200 sleep mode: ? ckio status * 1 sleep : hl (status1 = high, status0 = low) * 2 normal : ll (status1 = low, status0 = low) notes: * 2 * 2 * 1 normal sleep normal interrupt request ckio2 figure 10.7 status output when sl eep mode is cancel ed by interrupt ? ckio resetp status * 1 if pll1 multiplication rate changed by a power-on reset, resetp must be kept low for the oscillation stabilization time. * 2 reset : hh (status1 = high, status0 = high) * 3 sleep : hl (status1= high, status0= low) * 4 normal : ll (status1 = low, status0 = low) * 5 bcyc : bus clock cycle notes: undefined * 4 * 4 * 1 * 2 0 to 30 bcyc * 5 0 to 10 bcyc normal * 3 sleep reset normal * 5 reset ckio2 figure 10.8 status output when sleep mode is canceled by power-on reset
section 10 power-down modes rev. 2.00 dec. 07, 2005 page 310 of 950 rej09b0079-0200 ? ckio status * 1 resetm must be kept low until status = reset. * 2 reset:hh (status1 = high, status0 = high) * 3 sleep:hl(status1= high, status0= low) * 4 normal:ll (status1 = low, status0 = low) * 5 bcyc:bus clock cycle notes: * 4 * 4 * 1 * 2 0 to 30 bcyc * 5 0 to 80 bcyc normal * 3 sleep reset normal * 5 reset resetm ckio2 figure 10.9 status output when sl eep mode is canceled by manual reset
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 311 of 950 rej09b0079-0200 section 11 on-chip oscillation circuits 11.1 overview the oscillator consists of a clock pulse generator (cpg) block and a watchdog timer (wdt) block. the cpg generates clocks supplied to this lsi and controls the power-down modes. the wdt is a single-channel timer that counts the clock settling time and is used when clearing standby mode and temporary standbys, such as fr equency changes. it can also be used as an ordinary watchdog timer or interval timer. 11.1.1 features the cpg has the following features: ? ? = ? ? ? ? ?
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 312 of 950 rej09b0079-0200 ? ?
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 313 of 950 rej09b0079-0200 11.2 overview of cpg 11.2.1 cpg block diagram a block diagram of the on-chip clock pulse generator is shown in figure 11.1. ckio ckio2 xtal crystal oscillator pll circuit 1 ( 1, 2, 3) pll circuit 2 ( 1, 2, 4) clock pulse generator clock frequency control circuit standby control circuit stbcr bus interface internal bus frqcr: frequency control register stbcr: standby control register stbcr2: standby control register 2 stbcr3: standby control register 3 [legend] peripheral cloc k (p ) extal cpg control unit 1 1/2 1/3 1/4 1/6 internal clock (i ) divider 1 bus clock (b =ckio) stbcr3 stbcr2 frqcr figure 11.1 block diagram of cpg
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 314 of 950 rej09b0079-0200 the clock pulse generator blocks function as follows: 1. pll circuit 1: pll circuit 1 doubles, triples, or leaves unchanged the input clock frequency from the ckio terminal. the multiplication rate is set by the frequency control register. when this is done, the phase of the rising edge of the internal clock is controlled so that it will synchronize with the ph ase of the rising edge of the ckio pin. 2. pll circuit 2: pll circuit 2 doubles, quadruples, or leaves unchanged the input clock frequency from the crystal oscillator or extal pin. the multiplication ratio is fixed by the clock operating modes. the clock operating modes is set by pins md0, md1, and md2. see table 11.2 for more information on clock operating modes. 3. crystal oscillator: this oscillator is used wh en a crystal resonator is connected to the xtal and extal pins. this crystal oscillator operates according to the clock operating mode setting. 4. divider 1: divider 1 generates a clock at the operating frequency used by the internal or peripheral clock. the operating frequency of the internal clock (i
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 315 of 950 rej09b0079-0200 11.2.2 input/output pins table 11.1 lists the cpg pins and their functions. table 11.1 pin configuration pin name abbreviation i/o description mode control pins md0 i set the clock operating mode. md1 i set the clock operating mode. md2 i set the clock operating mode. xtal o connects a crystal oscillator. crystal oscillator pins (clock input pins) extal i connects a crystal oscillator. also used to input an external clock. clock i/o pin ckio io inputs or outputs an external clock. clock output pin ckio2 o outputs an external clock. note: to prevent device malfunction, the value of the mode control pin is sampled only by a power-on reset. 11.3 clock operating modes table 11.2 shows the relationship between the mode control pins (md2 to md0) combinations and the clock modes. table 11.3 shows the available combinations of the values of the clock modes and frequency control register (frqcr). table 11.2 clock operating modes pin values clock i/o mode md2 md1 md0 source output pll2 on/off pll1 on/off ckio frequency 0 0 0 0 extal ckio ckio2 on (x 1) on (x 1, 2, 3) (extal) 1 0 0 1 extal ckio ckio2 on (x 4) on (x 1, 2, 3) (extal) x 4 2 0 1 0 crystal resonator ckio ckio2 on (x 4) on (x 1, 2, 3) (crystal) x 4 4 1 0 0 crystal resonator ckio ckio2 on (x 1) on (x 1, 2, 3) (crystal)
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 316 of 950 rej09b0079-0200 pin values clock i/o mode md2 md1 md0 source output pll2 on/off pll1 on/off ckio frequency 5 1 0 1 extal ckio ckio2 on (x 2) on (x 1, 2, 3) (extal) x 2 6 1 1 0 crystal resonator ckio ckio2 on (x 2) on (x 1, 2, 3) (crystal) x 2 7 1 1 1 ckio ? off on (x 1, 2, 3) (ckio) mode 0: an external clock is input from the extal pin and undergoes waveform shaping by pll circuit 2 before being supplied inside this lsi. an input clock frequency of 33.3 mhz to 66.67 mhz can be used, and the ckio frequency range is 33.3 mhz to 66.67 mhz. mode 1: an external clock is input from the extal pin and its frequency is multiplied by 4 by pll circuit 2 before being supplied inside this lsi, allowing a low-frequency external clock to be used. an input clock frequency of 10.00 mhz to 16.67 mhz can be used, and the ckio frequency range is 40.00 mhz to 66.67 mhz. mode 2: the on-chip crystal oscillator operates, wit h the oscillation frequency being multiplied by 4 by pll circuit 2 before being supplied inside this lsi, allowing a low-frequency external clock to be used. a crystal oscillation frequency of 10.00 mhz to 16.67 mhz can be used, and the ckio frequency range is 40.00 mhz to 66.67 mhz. mode 4: the on-chip crystal oscillator operates and undergoes waveform shaping by pll circuit 2 before being supplied inside this lsi. a crystal oscillation frequency of 33.34 mhz to 48.00 mhz can be used, and the ckio frequen cy range is 33.34 mhz to 48.00 mhz. mode 5: an external clock is input from the extal pin and its frequency is multiplied by 2 by pll circuit 2 before being supplied inside this lsi, allowing a low-frequency external clock to be used. an input clock frequency of 16.67 mhz to 33.34 mhz can be used, and the ckio frequency range is 33.34 mhz to 66.67 mhz. mode 6: the on-chip crystal oscillator operates, wit h the oscillation frequency being multiplied by 2 by pll circuit 2 before being supplied inside this lsi, allowing a low-frequency clock to be used. a crystal oscillation frequency of 10.00 mhz to 16.67 mhz can be used, and the ckio frequency range is 40.00 mhz to 66.67 mhz mode 7: in this mode, the ckio pin is an input, an external clock is input to this pin, and undergoes waveform shaping and also frequency multiplication according to the setting, by pll circuit 1 before being supplied to this lsi. as pll circuit 1 compensates for fluctuations in the ckio pin load, this m ode is suitable for connection of synchronous dram.
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 317 of 950 rej09b0079-0200 table 11.3 possible combination of clock mode and frqcr values mode frqcr value pll circuit 1 pll circuit 2 clock ratio * (i:b:p) frequency range of input clock and crystal resonator frequency range of ckio pin 1001 on (x1) on (x1) 1:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1002 on (x1) on (x1) 1:1:1/3 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1003 on (x1) on (x1) 1:1:1/4 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1103 on (x2) on (x1) 2:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1104 on (x2) on (x1) 2:1:1/3 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 0 1204 on (x3) on (x1) 3:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1001 on (x1) on (x4) 4:4:2 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz 1002 on (x1) on (x4) 4:4:4/3 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz 1003 on (x1) on (x4) 4:4:1 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz 1103 on (x2) on (x4) 8:4:2 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz 1104 on (x2) on (x4) 8:4:4/3 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz 1, 2 1204 on (x3) on (x4) 12:4:2 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz 1001 on (x1) on (x1) 1:1:1/2 33.34 mhz to 48.00 mhz 33.34 mhz to 48.00 mhz 1002 on (x1) on (x1) 1:1:1/3 33.34 mhz to 48.00 mhz 33.34 mhz to 48.00 mhz 1003 on (x1) on (x1) 1:1:1/4 33.34 mhz to 48.00 mhz 33.34 mhz to 48.00 mhz 4 1103 on (x2) on (x1) 2:1:1/2 33.34 mhz to 48.00 mhz 33.34 mhz to 48.00 mhz
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 318 of 950 rej09b0079-0200 mode frqcr value pll circuit 1 pll circuit 2 clock ratio * (i:b:p) frequency range of input clock and crystal resonator frequency range of ckio pin 1104 on (x2) on (x1) 2:1:1/3 33.34 mhz to 48.00 mhz 33.34 mhz to 48.00 mhz 4 1204 on (x3) on (x1) 3:1:1/2 33.34 mhz to 48.00 mhz 33.34 mhz to 48.00 mhz 1001 on (x1) on (x2) 2:2:1 16.67 mhz to 33.34 mhz 33.34 mhz to 66.67 mhz 1002 on (x1) on (x2) 2:2:2/3 16.67 mhz to 33.34 mhz 33.34 mhz to 66.67 mhz 1003 on (x1) on (x2) 2:2:1/2 16.67 mhz to 33.34 mhz 33.34 mhz to 66.67 mhz 1103 on (x2) on (x2) 4:2:1 16.67 mhz to 33.34 mhz 33.34 mhz to 66.67 mhz 1104 on (x2) on (x2) 4:2:2/3 16.67 mhz to 33.34 mhz 33.34 mhz to 66.67 mhz 5 1204 on (x3) on (x2) 6:2:1 16.67 mhz to 33.34 mhz 33.34 mhz to 66.67 mhz 1001 on (x1) on (x2) 2:2:1 16.67 mhz to 33.34 mhz 33.34 mhz to 66.67 mhz 1002 on (x1) on (x2) 2:2:2/3 16.67 mhz to 33.34 mhz 33.34 mhz to 66.67 mhz 1003 on (x1) on (x2) 2:2:1/2 16.67 mhz to 33.34 mhz 33.34 mhz to 66.67 mhz 1103 on (x2) on (x2) 4:2:1 16.67 mhz to 33.34 mhz 33.34 mhz to 66.67 mhz 1104 on (x2) on (x2) 4:2:2/3 16.67 mhz to 33.34 mhz 33.34 mhz to 66.67 mhz 6 1204 on (x3) on (x2) 6:2:1 16.67 mhz to 33.34 mhz 33.34 mhz to 66.67 mhz 1001 on (x1) off 1:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1002 on (x1) off 1:1:1/3 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 7 1003 on (x1) off 1:1:1/4 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 319 of 950 rej09b0079-0200 mode frqcr value pll circuit 1 pll circuit 2 clock ratio * (i:b:p) frequency range of input clock and crystal resonator frequency range of ckio pin 1103 on (x2) off 2:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1104 on (x2) off 2:1:1/3 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 7 1204 on (x3) off 3:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz notes: * the input clock is 1. maximum frequency: i = 200.00 mhz, b (ckio) = 66.67 mhz, p = 33.34 mhz 1. use the ckio frequency within 33.34 mhz ckio 66.67 mhz. 2. the input to divider 1 is the output of pll circuit 1. 3. use the internal clock frequency within 33.34 mhz i 200.00 mhz. the internal clock frequency is the produc t of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1 selected by the stc bit in frqcr, and the division ratio selected by the ifc bit in frqcr. do not set the internal clock frequency lower than the ckio pin frequency. 4. use the peripheral clock frequency within 8.34 mhz p 33.34 mhz. the peripheral clock frequency is the produc t of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1 selected by the stc bit in frqcr, and the division ratio selected by the pfc bit in frqcr. do not set the peripheral clock frequency hi gher than the frequency of the ckio pin. 5. 1, 2, or 3 can be used as the multiplication ratio of pll circuit 1. 1, 1/2, or 1/3 can be selected as the division ratio of an internal clock. 1/2, 1/3, 1/4, or 1/6 can be selected as the division ratio of a peripheral clock. set the rate in frqcr. 6. the output frequency of pll circuit 1 is the product of the ckio frequency and the multiplication ratio of pll circuit 1. use the output frequency under 200.00 mhz.
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 320 of 950 rej09b0079-0200 11.4 register description the cpg has the following register . for details on register addre sses and register access size, refer to section 24, list of registers. ? bit bit name initial value r/w description 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 ckoen 1 r/w clock output enable ckoen specifies whether a clock is output from the ckio pin or the ckio pin is placed in the level-fixed state in the standby mode, ckio pin is fixed at low during status 1 = l, and statuso = h, when ckoen is set to 0. therefore, the malfunction of an external circuit because of an unstable ckio clock in releasing the standby mode can be prevented. the ckio pin becomes to input pin regardless of the value of the ckoen bit in clock operating mode 7. 0: ckio pin goes to low level state in standby mode. 1: clock is output from ckio pin 11 10 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0.
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 321 of 950 rej09b0079-0200 bit bit name initial value r/w description 9 8 stc1 stc0 0 0 r/w r/w frequency multiplication ratio of pll circuit 1 00: 1 time 01: 2 times 10: 3 times 11: reserved (setting prohibited) 7 6 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0. 5 4 ifc1 ifc0 0 0 r/w r/w internal clock frequency division ratio these bits specify the frequency division ratio of the internal clock (i ) with respect to the output frequency of pll circuit 1. 00: 1 time 01: 1/2 time 10: 1/3 time 11: reserved (setting prohibited) 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 1 0 pfc2 pfc1 pfc0 0 1 1 r/w r/w r/w peripheral clock frequency division ratio these bits specify the division ratio of the peripheral clock (p ) frequency with respect to the output frequency of pll circuit 1. 001: 1/2 time 010: 1/3 time 011: 1/4 time 100: 1/6 time other than above: reserved (setting prohibited)
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 322 of 950 rej09b0079-0200 11.5 changing frequency the frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of pll circuit 1 or by changing the division rates of divider 1. all of these are controlled by software through frqcr. the methods are described below. 11.5.1 changing multiplication rate a pll settling time is required when the multiplicati on rate of pll circuit 1 is changed. the on- chip wdt counts the settling time. 1. in the initial state, the multiplication rate of pll circuit 1 is 1. 2. set a value that will become the specified oscillation settling time in the wdt and stop the wdt. the following must be set: tme bit in wtcsr = = =
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 323 of 950 rej09b0079-0200 11.6 overview of wdt 11.6.1 block diagram of wdt figure 11.2 shows a block diagram of the wdt. wtcsr standby control bus interface wtcnt divider clock selector clock peripheral bus standby mode peripheral clock standby cancellation reset control clock selection wdt overflow internal reset request interrupt control interrupt request wtcsr: wtcnt: watchdog timer control/status register watchdog timer counter [legend] figure 11.2 block diagram of wdt
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 324 of 950 rej09b0079-0200 11.7 register descriptions of wdt the wdt has the following two registers that se lect the clock, switch the timer mode, and perform other functions. for details on register ad dresses and register access size, refer to section 24, list of registers. ? ? resetp pin. use a word access to write to wtcnt, with h'5a in th e upper byte. use a byte access to read wtcnt. note: wtcnt differs from other registers in that it is more difficult to write to. see section 11.7.3, notes on register access, for details. 11.7.2 watchdog timer contro l/status register (wtcsr) wtcsr is an 8-bit readable/writable register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. wtcsr is initialized to h'00 only by a power-on reset through the resetp pin. when a wdt overflow causes an internal reset, wtcsr retains its value. when used to count the clock settling time for canceling a standby, it retains its value after counter overflow. use a word access to write to wt csr, with h'a5 in the upper byte. use a byte access to read wtcsr. note: wtcsr differs from other registers in that it is more difficult to write to. see section 11.7.3, notes on register access, for details.
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 325 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 tme 0 r/w timer enable starts and stops timer operation. clear this bit to 0 when using the wdt in standby mode or when changing the clock frequency. 0: timer disabled: count-up stops and wtcnt value is retained 1: timer enabled 6 wt/ it 0 r/w timer mode select selects whether to use the wdt as a watchdog timer or an interval timer. 0: use as interval timer 1: use as watchdog timer note: if wt/ it is modified when the wdt is running, the up-count may not be performed correctly. 5 rsts 0 r/w reset select selects the type of reset when the wtcnt overflows in watchdog timer mode. in interval timer mode, this setting is ignored. 0: power-on reset 1: manual reset 4 wovf 0 r/w watchdog timer overflow indicates that the wtcnt has overflowed in watchdog timer mode. this bit is not set in interval timer mode. 0: no overflow 1: wtcnt has overflowed in watchdog timer mode 3 iovf 0 r/w interval timer overflow indicates that the wtcnt has overflowed in interval timer mode. this bit is not set in watchdog timer mode. 0: no overflow 1: wtcnt has overflowed in interval timer mode
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 326 of 950 rej09b0079-0200 bit bit name initial value r/w description 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select the clock to be used for the wtcnt count from the eight types obtainable by dividing the peripheral clock. the overfl ow period in the table is the value when the peripheral clock (p ) is 15 mhz. clock clock overflow period select division ratio (when p =15mhz) 000 1 17 s 001 1/4 68 s 010 1/16 273 s 011 1/32 546 s 100 1/64 1.09 ms 101 1/256 4.36 ms 110 1/1024 17.48 ms 111 1/4096 69.91 ms note: if bits cks2 to c ks0 are modified when the wdt is running, the up-count may not be performed correctly. ensure that these bits are modified only when the wdt is not running. 11.7.3 notes on register access the watchdog timer counter (wtcnt) and watchdog timer control/status register (wtcsr) are more difficult to write to than other registers. the procedure for writing to these registers are given below. writing to wtcnt and wtcsr: these registers must be written by a word transfer instruction. they cannot be written by a by te or longword transfer instruction. when writing to wtcnt, set the upper byte to h'5a and transfer the lower byte as the write data, as shown in figure 11.3. when writing to wtcs r, set the upper byte to h'a5 and transfer the lower byte as the write data. this transfer pr ocedure writes the lower byte data to wtcnt or wtcsr.
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 327 of 950 rej09b0079-0200 15 8 7 0 h'5a write data address: h'a415ff84 wtcnt write 15 8 7 0 h'a5 write data address: h'a415ff86 wtcsr write figure 11.3 writing to wtcnt and wtcsr 11.8 using wdt 11.8.1 canceling standbys the wdt can be used to cancel stan dby mode with an interrupt such as an nmi. the procedure is described below. (the wdt does not run when resets are used for canceling, so keep the resetp or resetm pin low until the clock stabilizes.) 1. before transitioning to standby mode, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2 to cks0 bits in wtcsr and the initial values for the counter in wtcnt. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. move to standby mode by executing a sleep instruction to stop the clock. 4. the wdt starts counting by detecti ng the edge change of the nmi signal. 5. when the wdt count overflows, the cpg st arts supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set at this time. 6. since the wdt continues counting from h'00, clear the stby bit in stbcr to 0 in the interrupt processing program and this will stop the wdt. when the stby bit remains 1, the lsi again enters the standby mode when the wdt has counted up to h'80. this standby mode can be canceled by power-on resets.
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 328 of 950 rej09b0079-0200 11.8.2 changing frequency to change the frequency used by the pll, use the wdt. when changing the frequency only by switching the divider, do not use the wdt. 1. before changing the frequency, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2 to cks0 bits in wtcsr and the initial values for the counter in wtcnt. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. when the frequency control register (frqcr) is written, the processor stop temporarily. the wdt starts counting. 4. when the wdt count overflows, the cpg re sumes supplying the cl ock and the processor resumes operation. the wovf flag in wtcsr is not set at this time. 5. the counter stops at the values h'00. 6. before changing the wtcnt after the executi on of the frequency change instruction, always confirm that the value of the wtcn t is h'00 by reading the wtcnt. 11.8.3 using watchdog timer mode 1. set the wt/ it bit in wtcsr to 1, set the reset type in the rsts bit, set the type of count clock in the cks2 to cks0 bits, and set the initial value of the counter in wtcnt. 2. set the tme bit in wtcsr to 1 to start the count in watchdog timer mode. 3. while operating in watchdog timer mode, rewrit e the counter periodically to h'00 to prevent the counter from overflowing. 4. when the counter overflows, the wdt sets th e wovf flag in wtcsr to 1 and generates the type of reset specified by the rsts bit. the counter then resumes counting. 11.8.4 using interval timer mode when operating in interval timer mode, interval ti mer interrupts are generated at every overflow of the counter. this enables interrupts to be generated at set periods. 1. clear the wt/ it bit in wtcsr to 0, set the type of count clock in the cks2 to cks0 bits, and set the initial value of the counter in wtcnt. 2. set the tme bit in wtcsr to 1 to start the count in interval timer mode. 3. when the counter overflows, the wdt sets th e iovf flag in wtcsr to 1 and an interval timer interrupt request is sent to in tc. the counter then resumes counting.
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 329 of 950 rej09b0079-0200 11.9 notes on board design when using an external crystal resonator: place the crystal resonator, capacitors cl1 and cl2, and damping resistor r close to the extal and xtal pins. to prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components. note: the values for cl1, cl2, and the damping resistance should be determined after consultation with the crystal manufacturer. xtal extal this lsi r cl2 cl1 avoid crossing signal lines figure 11.4 points for attention when using crystal resonator bypass capacitors: insert a laminated ceramic capacitor as a bypass capacitor for each vss/vssq and vcc/vccq pair. mount the bypass capacitors to the power supply pins, and use components with a frequency characteristic suitable for the opera ting frequency of the lsi, as well as a suitable capacitance value. pin assignments of hqfp2828-256 (fp-256g/gv) vss/vssq and vcc/vccq pair of digital circuitry 3 and 4, 13 and 14, 15 and 16, 25 and 26, 35 and 36, 43 and 44, 49 and 50, 57 and 58, 72 and 73, 81 and 82, 83 and 84, 92 and 93, 99 and 100, 107 and 108, 113 and 114, 121 and 122, 136 and 137, 146 and 147, 148 and 149, 158 and 159, 167 and 168, 176 and 177, 185 and 186, 191 and 192, 206 and 207, 208 and 209, 221 and 222, 227 and 228, 235 and 236, 241 and 242 vss/vssq and vcc/vccq pair of the on-chip oscillator 193 and 196, 251 and 252, 253 and 254
section 11 on-chip oscillation circuits rev. 2.00 dec. 07, 2005 page 330 of 950 rej09b0079-0200 pin assignments of p-lfbga1717-256 (bp-256h/hv) vss/vssq and vcc/vccq pair of digital circuitry d2-b1, e1-f4, g2-g3, j2-j4, l3-l2, n3-n2, r4-p2, u2-w1, v4-y4, y6-u7, w8-v8, v10- w10, v11-w11, v13-w13, u15-w14, w17-y19, u18-u20, p17-n19, n18-p20, l17-l20, j18-j19, e20-f17, d19-b20, c19-a20, d15-b14, c14-a15, b11-d11, c10-b10, c8-b8, d6- b7 vss/vssq and vcc/vccq pair of the on-chip oscillator b19-a19, c3-b5, and c5-c4 when using a pll oscillator circuit: keep the wiring from the pll vcc and pll vss connection pattern to the power supply pins short, and make the pattern width large, to minimize the inductance component. connect the extal pin to vccq or vssq and make the xtal pin open in clock mode 7. the analog power supply system of the pll is sensitive to a noise. therefore the system malfunction may occur by the intervention with other power supply. do not supply the analog power supply with the same resource as the digital power supply of vcc and vccq. vcc(pll2) vss(pll2) vcc(pll1) vss(pll1) avoid crossing signal lines power supply vcc vss figure 11.5 points for attentio n when using pll oscillator circuit
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 331 of 950 rej09b0079-0200 section 12 bus state controller (bsc) the bus state controller (bsc) outputs control si gnals for various types of memory that is connected to the external addre ss space and external devices. the bsc functions enable this lsi to connect directly with sram, sdram, and other memory storage devices, and external devices. 12.1 features the bsc has the following features: 1. external address space ? a maximum 32 or 64 mbytes for each of the eight areas, cs0, cs2 to cs4, cs5a, cs5b, cs6a and cs6b, totally 384 mbytes (divided into eight areas). ? a maximum 64 mbytes for each of the six areas , cs0, cs2 to cs4, cs5, and cs6, totally a total of 384 mbytes (divided into six areas). ? can specify the normal space interface, byte-se lection sram, burst rom (clock synchronous or asynchronous), sdram, pcmc ia for each address space. ? can select the data bus width (8, 16, or 32 bits) for each address space. ? controls the insertion of the wa it state for each address space. ? controls the insertion of the wait stat e for each read access and write access. ? can set the independent idling cycle in the c ontinuous access for five cases: read-write (in same space/different space) , read-read (in same space/different space), or the first cycle is a write access. 2. normal space interface ? supports the interface that can di rectly connect to the sram. 3. burst rom (clock asynchronous) interface ? high-speed access to the rom that has the page mode function. 4. sdram interface ? can set the sdram in up to 2 areas. ? multiplex output for row address/column address. ? efficient access by single read/single write. ? high-speed access by bank-active mode. ? supports an auto-refresh and self-refresh.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 332 of 950 rej09b0079-0200 5. byte-selection sram interface ? can connect directly to a byte-selection sram. 6. pcmcia direct interface ? supports ic memory cards and i/o card interf aces defined in the jeid a specifications ver 4.2 (pcmcia2.1 rev 2.1). ? controls the insertion of the wait state using software. ? supports the bus sizing function of the i/o bus width (only in little endian mode). 7. burst rom (clock synchronous) interface ? can connect directly to a burst rom of the clock synchronous type. 8. bus arbitration ? shares all of the resources with other cpu and outputs the bus enable after receiving the bus request from external devices. 9. refresh function ? supports the auto-refresh and self-refresh functions. ? specifies the refresh interval using th e refresh counter an d clock selection. ? can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8). 10. interval timer using refresh counter ? generates an interrupt request by a compare match. the block diagram of the bsc is shown in figure 12.1.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 333 of 950 rej09b0079-0200 cmncr cs0wcr cs6bwcr cs0bcr cs6bbcr sdcr rtcsr rtcnt rtcor comparator bus mastership controller wait controller area controller internal master module internal slave module internal bus memory controller refresh controller interrupt controller [legend] module bus bsc cs0 , cs2 , cs3 , cs4 , cs5a , cs5b , cs6a , cs6b wait md5 to md3 iois16 a25 to a0, d31 to d0 refout back breq bs , rd/ wr , rd , we3(be3) to we0(be0) , ras , cas , cke, dqmxx, ce2a , ce2b cmncr: csnwcr: csnbcr: sdcr: rtcsr: rtcnt: rtcor: common control register csn space wait control register (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) csn space bus control register (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) sdram control register refresh timer control/status register refresh timer counter refresh time constant register . . . . . . . . . . . . . . . figure 12.1 block diagram of bsc
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 334 of 950 rej09b0079-0200 12.2 input/output pins the configuration of pins in this module is shown in table 12.1. table 12.1 pin configuration name i/o function a25 to a0 o address bus d31 to d0 i/o data bus bs o bus cycle start asserted when a normal space, burst rom (clock synchronous/asynchronous), or pcmcia is accessed. asserted by the same timing as cas in sdram access. cs0 , cs2 to cs4 o chip select cs5a o chip select active only for address map 1 cs5b / ce1a o chip select corresponds to pcmcia card sele ct signals d7 to d0 when the pcmcia is used. ce2a o corresponds to pcmcia card se lect signals d15 to d8 when the pcmcia is used. cs6a o chip select active only for address map 1 cs6b / ce1b o chip select corresponds to pcmcia card sele ct signals d7 to d0 when the pcmcia is used. ce2b o corresponds to pcmcia card se lect signals d15 to d8 when the pcmcia is used. rd/ wr o read/write connects to we pins when sdram or byte-selection sram is connected. rd o read pulse signal (read data output enable signal) a strobe signal to indicate the memory read cycle when the pcmcia is used.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 335 of 950 rej09b0079-0200 name i/o function we3(be3) / iciowr o indicates that d31 to d24 are being written to. connected to the byte select signal when a byte-selection sram is connected. functions as the i/o write strobe si gnal when the pcmcia is used. we2(be2) / iciord o indicates that d23 to d16 are being written to. connected to the byte select signal when a byte-selection sram is connected. functions as the i/o read strobe sig nal when the pcmcia is used. we1(be1) / we o indicates that d15 to d8 are being written to. connected to the byte select signal when a byte-selection sram is connected. functions as the memory write strobe signal when the pcmcia is used. we0(be0) o indicates that d7 to d0 are being written to. connected to the byte select signal when a byte-selection sram is connected. ras o connects to ras pin when sdram is connected. cas o connects to cas pin when sdram is connected. cke o connects to cke pin when sdram is connected. iois16 i pcmcia 16-bit i/o signal valid only in little endian mode. make it into low level at the time of big endian mode. dqmuu dqmul dqmlu dqmll o connected to the dqmxx when the sdram is connected. dqmuu: selects d31 to d24 dqmul: selects d23 to d16 dqmlu: selects d15 to d8 dqmll: selects d7 to d0 wait i external wait input breq i bus request input back o bus acknowledge output md5 to md3 i md5: selects data alignment (big endian or little endian) md4 and md3: specify area 0 bus width (8/16/32 bits) refout o refresh request output when a bus is released
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 336 of 950 rej09b0079-0200 12.3 area overview 12.3.1 area division in the architecture of th is lsi, both logical sp aces and physical spaces have 32-bit address spaces. the upper three bits divide into the p0 to p4 areas, and specify the cache access method. for details see section 6, cache. the remaining 29 bits are used for division of the space into ten areas (address map 1) or eight areas (address map 2) according to the map bit in cmncr setting. the bsc performs control for this 29-bit space. as listed in tables 12.2 and 12.3, this lsi can be connected directly to ei ght areas of memory, and it outputs chip select signals ( cs0 , cs2 to cs4 , cs5a , cs5b , cs6a , and cs6b ) for each of them. cs0 is asserted during area 0 access; cs5a is asserted during area 5a access when address map 1 is selected; and cs5b is asserted when address map 2 is selected. 12.3.2 shadow area areas 0, 2 to 4, 5a, 5b, 6a, and 6b are decoded by physical addresses a28 to a25, which correspond to areas 000 to 111. address bits 31 to 29 are ignore d. this means that the range of area 0 addresses, for example, is h'00000000 to h'03f fffff, and its corresp onding shadow space is the address space in p1 to p3 areas obtained by adding to it h'20000000 n (n = 1 to 6). the address range for area 7 is h'1c000000 to h'1fffffff. the address space h'1c000000 + h'20000000 n to h'1fffffff + h'20000000 n (n = 0 to 6) corresponding to the area 7 shadow space is reserved , so do not use it. area p4 (h'e0000000 to h'efffffff) is an i/o area and is assigned for internal register addresses. therefore, area p4 does not become shadow space.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 337 of 950 rej09b0079-0200 area 0 (cs0) h'00000000 h'20000000 h'40000000 h'60000000 h'80000000 h'a0000000 h'c0000000 h'e0000000 area 1 (internal i/o) area 2 (cs2) area 3 (cs3) area 4 (cs4) area 5a (cs5a) area 6a (cs6a) area 7 (reserved area) physical address space address space p0 p1 p2 p3 p4 area 5b (cs5b) area 6b (cs6b) figure 12.2 address space
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 338 of 950 rej09b0079-0200 12.3.3 address map the external address space has a ca pacity of 384 mbytes and is us ed by dividing 8 partial spaces (address map 1) or 6 partial spaces (address map 2) . the kind of memory to be connected and the data bus width are specified in each partial space. the address map for the external address space is listed below. table 12.2 address space map 1 (cmncr.map = 0) physical address area memory to be connected capacity h 00000000 to h 03ffffff area 0 normal memory * 3 burst rom (asynchronous) burst rom (synchronous) 64 mbytes h 04000000 to h 07ffffff area 1 internal i/o register area * 2 64 mbytes h 08000000 to h 0bffffff area 2 normal memory * 3 byte-selection sram sdram 64 mbytes h 0c000000 to h 0fffffff area 3 normal memory * 3 byte-selection sram sdram 64 mbytes h 10000000 to h 13ffffff area 4 normal memory * 3 byte-selection sram burst rom (asynchronous) 64 mbytes h 14000000 to h 15ffffff area 5a normal memory * 3 32 mbytes h 16000000 to h 17ffffff area 5b normal memory * 3 byte-selection sram 32 mbytes h 18000000 to h 19ffffff area 6a normal memory * 3 32 mbytes h 1a000000 to h 1bffffff area 6b normal memory * 3 byte-selection sram 32 mbytes h 1c000000 to h 1fffffff area 7 reserved area * 1 64 mbytes notes: 1. do not access the reserved area. if t he reserved area is accessed, the correct operation cannot be guaranteed. 2. set the top three bits of the addre ss to 101 to allocate in the p2 space. 3. memory that has an interface such as sram.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 339 of 950 rej09b0079-0200 table 12.3 address space map 2 (cmncr.map = 1) physical address area memory to be connected capacity h 00000000 to h 03ffffff area 0 normal memory * 4 burst rom (asynchronous) burst rom (synchronous) 64 mbytes h 04000000 to h 07ffffff area 1 internal i/o register area * 3 64 mbytes h 08000000 to h 0bffffff area 2 normal memory * 4 byte-selection sram sdram 64 mbytes h 0c000000 to h 0fffffff area 3 normal memory * 4 byte-selection sram sdram 64 mbytes h 10000000 to h 13ffffff area 4 normal memory * 4 byte-selection sram burst rom (asynchronous) 64 mbytes h 14000000 to h 17ffffff area 5 * 2 normal memory * 4 byte-selection sram pcmcia 64 mbytes h 18000000 to h 1bffffff area 6 * 2 normal memory * 4 byte-selection sram pcmcia 64 mbytes h 1c000000 to h 1fffffff area 7 reserved area * 1 64 mbytes notes: 1. do not access the reserved area. if the reserved area is accessed, the correct operation cannot be guaranteed. 2. for area 5, cs5bbcr and cs5bwcr are valid. for area 6, cs6bbcr and cs6bwcr are valid. 3. set the top three bits of the addre ss to 101 to allocate in the p2 space. 4. memory that has an interface such as sram.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 340 of 950 rej09b0079-0200 12.3.4 area 0 memory ty pe and memory bus width the memory bus width in this lsi can be set for eac h area. in area 0, external pins can be used to select byte (8 bits), word (16 bits), or longwo rd (32 bits) on power-on reset. the memory bus width of the other area is set by the register. the correspondence between the memory type, external pins (md3, md4), and bus width is listed in the table below. table 12.4 correspondence betw een external pins (md3 and md4), memory type of cs0, and memory bus width md4 md3 memory type bus width 0 reserved (setting prohibited) 0 1 8 bits * 0 16 bits 1 1 normal memory 32 bits note: * the bus width must not be specified as ei ght bits if the burst rom (clock synchronous) interface is selected. 12.3.5 data alignment this lsi supports the big endian and little endian methods of data alignment. the data alignment is specified using the external pin (md5) at power-on reset as shown in table 12.5. table 12.5 corresponde nce between external pin (md5) and endians md5 endian 0 big endian 1 little endian
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 341 of 950 rej09b0079-0200 12.4 register descriptions the bsc has the following registers. refer to section 24, list of registers, for the addresses and access size for these registers. do not access spaces other than cs0 until the term ination of the setting the memory interface. ? common control register (cmncr) ? bus control register for area 0 (cs0bcr) ? bus control register for area 2 (cs2bcr) ? bus control register for area 3 (cs3bcr) ? bus control register for area 4 (cs4bcr) ? bus control register for area 5a (cs5abcr) ? bus control register for area 5b (cs5bbcr) ? bus control register for area 6a (cs6abcr) ? bus control register for area 6b (cs6bbcr) ? wait control register for area 0 (cs0wcr) ? wait control register for area 2 (cs2wcr) ? wait control register for area 3 (cs3wcr) ? wait control register for area 4 (cs4wcr) ? wait control register for area 5a (cs5awcr) ? wait control register for area 5b (cs5bwcr) ? wait control register for area 6a (cs6awcr) ? wait control register for area 6b (cs6bwcr) ? sdram control register (sdcr) ? refresh timer control/status register (rtcsr)* 1 ? refresh timer counter (rtcnt)* 1 ? refresh time constant register (rtcor)* 1 ? sdram mode register for area 2 (sdmr2)* 2 ? sdram mode register for area 3 (sdmr3)* 2 notes: 1. this register only acce pts 32-bit writing to prevent inco rrect writing. in this case, the upper 16 bits of the data must be h'a55a. otherwise, writing cannot be performed. in reading, the upper 16 b its are read as h'0000. 2. the contents of this register are stor ed in sdram. when this register space is accessed, the corresponding register in sdram is written to. for details, see description of power-on sequence in section 12.5.5, sdram interface.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 342 of 950 rej09b0079-0200 12.4.1 common control register (cmncr) cmncr is a 32-bit register that controls the co mmon items for each area . do not access external memory other than area 0 until the cmncr initialization is complete. bit bit name initial value r/w description 31 to 15 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 14 bsd 0 r/w bus access start timing specification after bus acknowledge specifies the bus access start timing after the external bus acknowledge signal is received. 0: starts the external access at the same timing as the address drive start after the bus acknowledge signal is received. 1: starts the external ac cess one cycle following the address drive start after the bus acknowledge signal is received. 13 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 12 map 0 r/w space specification selects the address map for the external address space. the address maps to be selected are shown in tables 12.2 and 12.3. 0: selects address map 1. 1: selects address map 2. 11 block 0 r/w bus lock bit specifies whether or not the breq signal is received. 0: receives breq . 1: does not receive breq .
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 343 of 950 rej09b0079-0200 bit bit name initial value r/w description 10 9 dprty1 dprty0 0 0 r/w r/w dma burst transfer priority specify the priority for a re fresh request/bus mastership request during dma burst transfer. 00: accepts a refresh request and bus mastership request during dma burst transfer 01: accepts a refresh request but does not accept a bus mastership request during dma burst transfer 10: accepts neither a refresh request nor a bus mastership request during dma burst transfer 11: reserved (setting prohibited) 8 7 6 dmaiw2 dmaiw1 dmaiw0 0 0 0 r/w r/w r/w wait states between access cycles when dma single address is transferred specify the number of idle cycles to be inserted after an access to an external device with dack when dma single address transfer is performed. the method of inserting idle cycles depends on the contents of dmaiwa. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycled inserted 100: 6 idle cycled inserted 101: 8 idle cycle inserted 110: 10 idle cycles inserted 111: 12 idle cycled inserted 5 dmaiwa 0 r/w method of inserting wait states between access cycles when dma single address is transferred specifies the method of inserti ng the idle cycles specified by the dmaiw1 and dmaiw0 bits. clearing this bit will make this lsi insert the idle cycles when another device, which includes this lsi, drives the data bus after an external device with dack drove it. when the external device with dack drives the data bus continuously, idle cycles are not inserted. setting this bit will make this lsi insert the idle cycles even when the continuous accesses to an external device with dack are performed.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 344 of 950 rej09b0079-0200 bit bit name initial value r/w description 4 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 3 endian 0/1 * r endian flag samples the external pin for specifying endian on power-on reset (md5). all address spaces are defined by this bit. this is a read-only bit. 0: the external pin for specifying endian (md5) was low level on power-on reset. this lsi is being operated as big endian. 1: the external pin for specifying endian (md5) was high level on power-on reset. this lsi is being operated as little endian. 2 ck2drv 0 r/w ckio2 drive specifies whether the ckio2 pin outputs a low level signal or clock (b ). 0: outputs a low level signal 1: outputs a clock (b ) 1 hizmem 0 r/w high-z memory control specifies the pin state in standby mode for a25 to a0, bs , csn , rd/ wr , wen ( ben )/dqmxx, and rd . when a bus is released, these pins enter the high-impedance state regardless of the setting of this bit. 0: high impedance in standby mode 1: driven in standby mode 0 hizcnt 0 r/w high-z control specifies the state in stand by mode and bus released for ckio, ckio2, cke, ras , and cas . 0: high impedance in standby mode and bus released for ckio, ckio2, cke, ras , and cas . 1: driven in standby mode and bus released for ckio, ckio2, cke, ras , and cas . note: if one of clock operating modes 4 to 6 is set, ckio, ckio2, cke, ras , and cas should be driven in standby mode and bus released. note: * the external pin (md5) for specifying endian is sampled on power-on reset. when big endian is specified, this bit is read as 0 and when little endian is specified, this bit is read as 1.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 345 of 950 rej09b0079-0200 12.4.2 csn space bus control register (csnbcr) (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) csnbcr specifies the type of me mory connected to each space, da ta-bus width of each space, and the number of wait cycles between access cycles. do not access external memory other than area 0 until the csnbcr initiali zation is completed. bit bit name initial value r/w description 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30 29 28 iww2 iww1 iww0 0 1 1 r/w r/w r/w idle cycles between write-read cycles and write-write cycles these bits specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target access cycles are the write-read cycle and write-write cycle. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 346 of 950 rej09b0079-0200 bit bit name initial value r/w description 27 26 25 iwrwd2 iwrwd1 iwrwd0 0 1 1 r/w r/w r/w idle cycles for another space read-write specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target access cycle is a read-write one in which continuous accesses switch between different spaces. 000: no idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 24 23 22 iwrws2 iwrws1 iwrws0 0 1 1 r/w r/w r/w idle cycles for read-write in same space specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target cycle is a read-write cycle of which continuous accesses are for the same space. 000: no idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 347 of 950 rej09b0079-0200 bit bit name initial value r/w description 21 20 19 iwrrd2 iwrrd1 iwrrd0 0 1 1 r/w r/w r/w idle cycles for read-read in another space specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target cycle is a read-read cycle of which continuous accesses switch between different space. 000: no idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 18 17 16 iwrrs2 iwrrs1 iwrrs0 0 1 1 r/w r/w r/w idle cycles for read-read in same space specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target cycle is a read-read cycle of which continuous accesses are for the same space. 000: no idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 348 of 950 rej09b0079-0200 bit bit name initial value r/w description 15 14 13 12 type3 type2 type1 type0 0 0 0 0 r/w r/w r/w r/w memory type specify the type of memory connected to a space. 0000: normal space 0001: burst rom (clock asynchronous) 0010: reserved (setting prohibited) 0011: byte-selection sram 0100: sdram 0101: pcmcia 0110: reserved (setting prohibited) 0111: burst rom (clock synchronous) * 2 1000: reserved (setting prohibited) 1001: reserved (setting prohibited) 1010: reserved (setting prohibited) 1011: reserved (setting prohibited) 1100: reserved (setting prohibited) 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) note: memory type for area 0 immediately after reset is normal space. the normal space, burst rom (clock asynchronous), or burst rom (clock synchronous) can be selected by these bits. for details on memory type in each area, see tables 12.2 and 12.3. 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 349 of 950 rej09b0079-0200 bit bit name initial value r/w description 10 9 bsz1 bsz0 1 * 1 1 * 1 r/w r/w data bus size specify the data bus sizes of spaces. 00: reserved (setting prohibited) 01: 8-bit size 10: 16-bit size 11: 32-bit size notes: 1. the data bus width for area 0 is specified by the external pin. the bsz1 and bsz0 bit settings in cs0bcr are ignored. 2. if area 5 or area 6 is specified as pcmcia space, the bus width can be specified as either 8 bits or 16 bits. 3. if area 2 or area 3 is specified as sdram space, the bus width can be specified as either 16 bits or 32 bits. 8 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. notes: 1. cs0bcr samples the external pins (md 3 and md4) that specify the bus width at a power-on reset. 2. the burst rom (clock synchronous) mu st be accessed as a cacheable space.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 350 of 950 rej09b0079-0200 12.4.3 csn space wait control register (csnwcr) (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) this register specifies various wait cycles for memory accesses. the bit configuration of this register varies as shown below according to the memory type (type3, type2, type1, or type0) specified by the csn space bus cont rol register (csnbcr). specify csnwcr before accessing the target area. specify cs nbcr first, then specify csnwcr. normal space, byte-selection sram: ? cs0wcr, cs6bwcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 bas 0 r/w byte access select ion for byte-selection sram specifies the wen ( ben ) and rd/ wr signal timing when the byte-selection sram interface is used. 0: asserts the wen ( ben ) signal at the read/write timing and asserts the rd/ wr signal during the write access cycle. 1: asserts the wen ( ben ) signal during the read/write access cycle and asserts the rd/ wr signal at the write timing. 19 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 351 of 950 rej09b0079-0200 bit bit name initial value r/w description 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specifies whether or not the external wait input is valid. the specification by this bi t is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 352 of 950 rej09b0079-0200 bit bit name initial value r/w description 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles ? cs2wcr, cs3wcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 bas 0 r/w byte access select ion for byte-selection sram specifies the wen ( ben ) and rd/ wr signal timing when the byte-selection sram interface is used. 0: asserts the wen ( ben ) signal at the read/write timing and asserts the rd/ wr signal during the write access cycle. 1: asserts the wen ( ben ) signal during the read/write access cycle and asserts the rd/ wr signal at the write timing. 19 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 353 of 950 rej09b0079-0200 bit bit name initial value r/w description 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 354 of 950 rej09b0079-0200 ? cs4wcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 bas 0 r/w byte access select ion for byte-selection sram specifies the wen ( ben ) and rd/ wr signal timing when the byte-selection sram interface is used. 0: asserts the wen ( ben ) signal at the read/write timing and asserts the rd/ wr signal during the write access cycle. 1: asserts the wen ( ben ) signal during the read/write access cycle and asserts the rd/ wr signal at the write timing. 19 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 18 17 16 ww2 ww1 ww0 0 0 0 r/w r/w r/w number of write access wait cycles specify the number of cycles that are necessary for write access. 000: the same cycles as wr3 to wr0 setting (read access wait) 001: 0 cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 355 of 950 rej09b0079-0200 bit bit name initial value r/w description 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specifies whether or not the external wait input is valid. the specification by this bit is valid even when the number of access wait cycles is 0. 0: external wait is valid 1: external wait is ignored
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 356 of 950 rej09b0079-0200 bit bit name initial value r/w description 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles ? cs5awcr bit bit name initial value r/w description 31 to 19 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 18 17 16 ww2 ww1 ww0 0 0 0 r/w r/w r/w number of write access wait cycles specify the number of cycles that are necessary for write access. 000: the same cycles as wr3 to wr0 setting (read access wait) 001: 0 cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 357 of 950 rej09b0079-0200 bit bit name initial value r/w description 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 358 of 950 rej09b0079-0200 bit bit name initial value r/w description 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles ? cs5bwcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 bas 0 r/w byte access selectio n for byte-selection sram specifies the wen ( ben ) and rd/ wr signal timing when the byte-selection sram interface is used. 0: asserts the wen ( ben ) signal at the read/write timing and asserts the rd/ wr signal during the write access cycle. 1: asserts the wen ( ben ) signal during the read/write access cycle and asserts the rd/ wr signal at the write timing. 19 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 359 of 950 rej09b0079-0200 bit bit name initial value r/w description 18 17 16 ww2 ww1 ww0 0 0 0 r/w r/w r/w number of write access wait cycles specify the number of cycles that are necessary for write access. 000: the same cycles as wr3 to wr0 setting (read access wait) 001: 0 cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 360 of 950 rej09b0079-0200 bit bit name initial value r/w description 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycles is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 361 of 950 rej09b0079-0200 ? cs6awcr bit bit name initial value r/w description 31 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 362 of 950 rej09b0079-0200 bit bit name initial value r/w description 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 363 of 950 rej09b0079-0200 burst rom (clock asynchronous): ? cs0wcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 ben 0 r/w burst enable specification enables or disables 8-burst access for a 16-bit bus width or 16-burst access for an 8-bit bus width during 16-byte access. if this bit is set to 1, 2-burst access is performed four times when the bus width is 16 bits and 4-burst access is performed four times when the bus width is 8 bits. to use a device that does not support 8-burst access or 16-burst access, set this bit to 1. 0: enables 8-burst access for a 16-bit bus width and 16- burst access for an 8-bit bus width. 1: disables 8-burst access for a 16-bit bus width and 16- burst access for an 8-bit bus width. 19, 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 16 bw1 bw0 0 0 r/w r/w number of burst wait cycles specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 364 of 950 rej09b0079-0200 bit bit name initial value r/w description 10 9 8 7 w3 w2 w1 w0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cycles to be inserted in the first read/write access cycle. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycles is 0. 0: external wait is valid 1: external wait is ignored 5 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 365 of 950 rej09b0079-0200 ? cs4wcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 ben 0 r/w burst enable specification enables or disables 8-burst access for a 16-bit bus width or 16- burst access for an 8-bit bus width during 16-byte access. if this bit is set to 1, 2-burst access is performed four times when the bus width is 16 bits and 4-burst access is performed four times when the bus width is 8 bits. to use a device that does not support 8-burst access or 16-burst access, set this bit to 1. 0: enables 8-burst access for a 16-bit bus width and 16- burst access for an 8-bit bus width. 1: disables 8-burst access for a 16-bit bus width and 16- burst access for an 8-bit bus width. 19, 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 16 bw1 bw0 0 0 r/w r/w number of burst wait cycles specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 366 of 950 rej09b0079-0200 bit bit name initial value r/w description 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. these bits can be specified only in area 4. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 w3 w2 w1 w0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cycles to be inserted in the first read/write access cycle. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specifies whether or not the external wait input is valid. the specification by this bit is valid even when the number of access wait cycles is 0. 0: external wait is valid 1: external wait is ignored
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 367 of 950 rej09b0079-0200 bit bit name initial value r/w description 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. these bits can be specified only in area 4. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles sdram*: ? cs2wcr bit bit name initial value r/w description 31 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 ? 1 r reserved these bits are always read as 1. the write value should always be 1. 9 ? 0 r reserved these bits are always read as 0. the write value should always be 0. 8 7 a2cl1 a2cl0 1 0 r/w r/w cas latency for area 2 specify the cas latency for area 2. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 368 of 950 rej09b0079-0200 bit bit name initial value r/w description 6 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. ? cs3wcr bit bit name initial value r/w description 31 to 15 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 14 13 trp1 trp0 0 0 r/w r/w number of wait cycles waiting completion of precharge specify the number of minimu m wait cycles to be inserted to wait the completion of precharge. the setting for areas 2 and 3 is common. (1) from starting auto-charge to issuing the actv command for the same bank (2) from issuing the pre/pall command to issuing the actv command for the same bank (3) to transiting to power-down mode/deep power-down mode (4) from issuing the pall command at auto-refresh to issuing the ref command (5) from issuing the pall command at self-refresh to issuing the self command 00: 0 cycle 01: 1 cycles 10: 2 cycles 11: 3 cycles 12 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 369 of 950 rej09b0079-0200 bit bit name initial value r/w description 11 10 trcd1 trcd0 0 1 r/w r/w number of wait cycles from actv command to read (a)/writ (a) command specify the number of minimu m wait cycles from issuing the actv command to issuing the read (a)/writ (a) command. the setting for areas 2 and 3 is common. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 9 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 8 7 a3cl1 a3cl0 1 0 r/w r/w cas latency for area 3. specify the cas latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 370 of 950 rej09b0079-0200 bit bit name initial value r/w description 4 3 trwl1 trwl0 0 0 r/w r/w number of wait cycles waiting start of precharge specify the number of minimu m wait cycles to be inserted to wait the start of precharge . the setting for areas 2 and 3 is common. (1) this lsi is in non-bank active mode from the issue of the writa command to the st art of auto-precharge in sdram, and issues the actv command for the same bank after issuing the writa command. confirm how many cycles are required from the reception of the writa co mmand to the start of auto- precharge in each sdram data sheet. set this bit so that the number of cycles is not above the cycles specified by this bit. (2) this lsi is in bank active mode from issuing the writ command to issuing the pre command, and the access to different row address in the same bank is performed. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 371 of 950 rej09b0079-0200 bit bit name initial value r/w description 1 0 trc1 trc0 0 0 r/w r/w number of idle cycles from ref command/self-refresh release to actv/ref/mrs command specify the number of mini mum idle cycles between the commands in the following cases. the setting for areas 2 and 3 is common. (1) from issuing the ref command to issuing the actv/ref/msr command (2) from releasing self-refresh to issuing the actv/ref/msr command 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles note: * if both areas 2 and 3 are specified as sdram, trp1/0, trcd0/1, trwl1/0, and trc1/0 bit settings are common. if only one area is connected to the sdram, specify area 3. in this case, specify area 2 as normal space or byte-selection sram.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 372 of 950 rej09b0079-0200 pcmcia: ? cs5bwcr, cs6bwcr bit bit name initial value r/w description 31 to 22 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 21 20 sa1 sa0 0 0 r/w r/w space attribute specification specify memory card interface or i/c card interface when the pcmcia interface is selected. sa1 0: specifies memory card interface when a25 = 1 1: specifies i/o card interface when a25 = 1 sa0 0: specifies memory card interface when a25 = 0 1: specifies i/o card interface when a25 = 0 19 to 15 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 373 of 950 rej09b0079-0200 bit bit name initial value r/w description 14 13 12 11 ted3 ted2 ted1 ted0 0 0 0 0 r/w r/w r/w r/w delay from address to rd or we assert specify the delay time from address output to rd or we assert in pcmcia interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 374 of 950 rej09b0079-0200 bit bit name initial value r/w description 10 9 8 7 pcw3 pcw2 pcw1 pcw0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cycles to be inserted. 0000: 3 cycles 0001: 6 cycles 0010: 9 cycles 0011: 12 cycles 0100: 15 cycles 0101: 18 cycles 0110: 22 cycles 0111: 26 cycles 1000: 30 cycles 1001: 33 cycles 1010: 36 cycles 1011: 38 cycles 1100: 52 cycles 1101: 60 cycles 1110: 64 cycles 1111: 80 cycles 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5, 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 375 of 950 rej09b0079-0200 bit bit name initial value r/w description 3 2 1 0 teh3 teh2 teh1 teh0 0 0 0 0 r/w r/w r/w r/w delay from rd or we negate to address specify the address hold time from rd or we negate in the pcmcia interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles burst rom (clock synchronous): ? cs0wcr bit bit name initial value r/w description 31 to 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 16 bw1 bw0 0 0 r/w r/w number of burst wait cycles specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 376 of 950 rej09b0079-0200 bit bit name initial value r/w description 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 7 w3 w2 w1 w0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cycles to be inserted in the first read/write access cycle. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycles is 0. 0: external wait is valid 1: external wait is ignored 5 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 377 of 950 rej09b0079-0200 12.4.4 sdram control register (sdcr) sdcr specifies the method to refresh and acce ss sdram, and the types of sdrams to be connected. bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 19 a2row1 a2row0 0 0 r/w r/w number of bits of row address for area 2 specify the number of bits of row address for area 2. 00: 11 bits 01: 12 bits 10: 13 bits 11: reserved (setting prohibited) 18 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 17 16 a2col1 a2col0 0 0 r/w r/w number of bits of column address for area 2 specify the number of bits of column address for area 2. 00: 8 bits 01: 9 bits 10: 10 bits 11: reserved (setting prohibited) 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 deep 0 r/w deep power-down mode this bit is valid for low-power sdram. if the rmode bit is set to 1 while this bit is set to 1, the deep power-down entry command is issued and the low-power sdram enters the deep power-down mode. 0: self-refresh mode 1: deep power-down mode
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 378 of 950 rej09b0079-0200 bit bit name initial value r/w description 12 slow 0 r/w low-frequency mode specifies the output timing of command, address, and write data for sdram and the latch timing of read data from sdram. setting this bit makes the hold time for command, address, write and read data extended for half cycle (output or read at the falling edge of ckio). when this bit set to 1, the hold time for command, address, and write and read data can be extended. this mode is suitable for sdram with low-frequency clock. 0: command, address, and write data for sdram is output at the rising edge of ckio. read data from sdram is latched at the rising edge of ckio. 1: command, address, and write data for sdram is output at the falling edge of ckio. read data from sdram is latched at the falling edge of ckio. 11 rfsh 0 r/w refresh control specifies whether or not t he refresh operation of the sdram is performed. 0: no refresh 1: refresh 10 rmode 0 r/w refresh control specifies whether to perform auto-refresh or self-refresh when the rfsh bit is 1. when the rfsh bit is 1 and this bit is 1, self-refresh starts immediately. when the rfsh bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in rtcsr, rtcnt, and rtcor. 0: auto-refresh is performed 1: self-refresh is performed 9 pdown 0 r/w power-down mode specify whether sdram is put in power-down mode or not after the access to memory other than sdram is completed. this bit, when set to 1, drives the cke pin low and places sdram in power-down mode by using an access to a memory other than sdram as a trigger. 0: does not place sdram in power-down mode after an access to a memory other than sdram. 1: places sdram in power-down mode after an access to a memory other than sdram.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 379 of 950 rej09b0079-0200 bit bit name initial value r/w description 8 bactv 0 r/w bank active mode specifies to access whether in auto-precharge mode (using reada and writa commands) or in bank active mode (using read and writ commands). 0: auto-precharge mode (using reada and writa commands) 1: bank active mode (using read and writ commands) note: bank active mode can be used only in area 3. in this case, the bus width can be selected as 16 or 32 bits. when both areas 2 and 3 are set to sdram, specify auto-precharge mode. 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 3 a3row1 a3row0 0 0 r/w r/w number of bits of row address for area 3 specify the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: reserved (setting prohibited) 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 0 a3col1 a3col0 0 0 r/w r/w number of bits of column address for area 3 specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: reserved (setting prohibited)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 380 of 950 rej09b0079-0200 12.4.5 refresh timer cont rol/status register (rtcsr) rtcsr specifies various items about refresh for sdram. when rtcsr is written, the upper 16 bits of th e write data must be h?a55a to cancel write protection. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 cmf 0 r/w compare match flag indicates that a compare matc h occurs between the refresh timer counter (rtcnt) and refres h time constant register (rtcor). this bit is set or cleared in the following conditions. 0: clearing condition: when 0 is written in cmf after reading out rtcsr during cmf = 1. 1: setting condition: when the condition rtcnt = rtcor is satisfied. 6 cmie 0 r/w compare match interrupt enable enables or disables a cmf interrupt request when the cmf bit of rtcsr is set to 1. 0: disables the cmf interrupt request 1: enables the cmf interrupt request 5 4 3 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select select the clock input to coun t-up the refresh timer counter (rtcnt). 000: stop the counting-up 001: b /4 010: b /16 011: b /64 100: b /256 101: b /1024 110: b /2048 111: b /4096
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 381 of 950 rej09b0079-0200 bit bit name initial value r/w description 2 1 0 rrc2 rrc1 rrc0 0 0 0 r/w r/w r/w refresh count specify the number of contin uous refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (rtcnt) and the refresh time constant register (rtcor). these bits can make the period of occurrence of refresh long. 000: once 001: twice 010: 4 times 011: 6 times 100: 8 times 101: reserved (setting prohibited) 110: reserved (setting prohibited) 111: reserved (setting prohibited) 12.4.6 refresh time r counter (rtcnt) rtcnt is an 8-bit counter that increments using the clock selected by bi ts cks2 to cks0 in rtcsr. when rtcnt matches rtcor, rtcnt is cl eared to 0. the value in rtcnt returns to 0 after counting up to 255. when the rtcnt is wr itten, the upper 16 bits of the write data must be h?a55a to cancel write protection. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 ? all 0 r/w 8-bit counter
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 382 of 950 rej09b0079-0200 12.4.7 refresh time constant register (rtcor) rtcor is an 8-bit register. when rtcor matche s rtcnt, the cmf bit in rtcsr is set to 1 and rtcnt is cleared to 0. when the rfsh bit in sdcr is 1, a memory refr esh request is issued by this matching signal. this request is maintained until the refresh opera tion is performed. if the request is not processed when the next matching occurs, the previous request is ignored. if the cmie bit of the rtcsr is set to 1, an inte rrupt is requested by this matching signal. this request is maintained until the cmf bit in rtcsr is cleared to 0. clearing the cmf bit in rtcsr affects only interrupts and does not affect refresh requests. this makes it possible to count the number of refresh requests during refresh by interrupts, and to specify the refresh and interval timer interrupts simultaneously. when the rtcor is written, the upper 16 bits of the write data must be h?a55a to cancel write protection. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 ? all 0 r/w 8-bit counter
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 383 of 950 rej09b0079-0200 12.5 operation 12.5.1 endian/access size and data alignment this lsi supports big endian, in which the 0 address is the most significant byte (msbyte) in the byte data and little endian, in which the 0 address is the least significant byte (lsbyte) in the byte data. endian is specified on power-on reset by the external pin (md5). when md5 pin is low level on power-on reset, the endian will become big endian and when md5 pin is high level on power-on reset, the endian will become little endian. three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byte- selection sram. two data bus widths (16 bits and 32 bits) are available for sdram. two data bus widths (8 bits and 16 bits ) are available for pcmcia interf ace. data alignment is performed in accordance with the data bus width of the device and en dian. this also means that when longword data is read from a byte-width device, the read operation must be done four times. in this lsi, data alignment and conversion of da ta length is performed automatically between the respective interfaces. tables 12.6 to 12.11 show the relationship between endian, devi ce data width, and access unit. table 12.6 32-bit extern al device/big e ndian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 data 7 to 0 ? ? ? assert ? ? ? byte access at 1 ? data 7 to 0 ? ? ? assert ? ? byte access at 2 ? ? data 7 to 0 ? ? ? assert ? byte access at 3 ? ? ? data 7 to 0 ? ? ? assert word access at 0 data 15 to 8 data 7 to 0 ? ? assert assert ? ? word access at 2 ? ? data 15 to 8 data 7 to 0 ? ? assert assert longword access at 0 data 31 to 24 data 23 to 16 data 15 to 8 data 7 to 0 assert assert assert assert
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 384 of 950 rej09b0079-0200 table 12.7 16-bit extern al device/big e ndian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? data 7 to 0 ? ? ? assert ? byte access at 1 ? ? ? data 7 to 0 ? ? ? assert byte access at 2 ? ? data 7 to 0 ? ? ? assert ? byte access at 3 ? ? ? data 7 to 0 ? ? ? assert word access at 0 ? ? data 15 to 8 data 7 to 0 ? ? assert assert word access at 2 ? ? data 15 to 8 data 7 to 0 ? ? assert assert 1st time at 0 ? ? data 31 to 24 data 23 to 16 ? ? assert assert longword access at 0 2nd time at 2 ? ? data 15 to 8 data 7 to 0 ? ? assert assert
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 385 of 950 rej09b0079-0200 table 12.8 8-bit external device/big endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? ? data 7 to 0 ? ? ? assert byte access at 1 ? ? ? data 7 to 0 ? ? ? assert byte access at 2 ? ? ? data 7 to 0 ? ? ? assert byte access at 3 ? ? ? data 7 to 0 ? ? ? assert 1st time at 0 ? ? ? data 15 to 8 ? ? ? assert word access at 0 2nd time at 1 ? ? ? data 7 to 0 ? ? ? assert 1st time at 2 ? ? ? data 15 to 8 ? ? ? assert word access at 2 2nd time at 3 ? ? ? data 7 to 0 ? ? ? assert 1st time at 0 ? ? ? data 31 to 24 ? ? ? assert 2nd time at 1 ? ? ? data 23 to 16 ? ? ? assert 3rd time at 2 ? ? ? data 15 to 8 ? ? ? assert longword access at 0 4th time at 3 ? ? ? data 7 to 0 ? ? ? assert
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 386 of 950 rej09b0079-0200 table 12.9 32-bit external device/li ttle endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? ? data 7 to 0 ? ? ? assert byte access at 1 ? ? data 7 to 0 ? ? ? assert ? byte access at 2 ? data 7 to 0 ? ? ? assert ? ? byte access at 3 data 7 to 0 ? ? ? assert ? ? ? word access at 0 ? ? data 15 to 8 data 7 to 0 ? ? assert assert word access at 2 data 15 to 8 data 7 to 0 ? ? assert assert ? ? longword access at 0 data 31 to 24 data 23 to 16 data 15 to 8 data 7 to 0 assert assert assert assert
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 387 of 950 rej09b0079-0200 table 12.10 16-bit external device/li ttle endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? ? data 7 to 0 ? ? ? assert byte access at 1 ? ? data 7 to 0 ? ? ? assert ? byte access at 2 ? ? ? data 7 to 0 ? ? ? assert byte access at 3 ? ? data 7 to 0 ? ? ? assert ? word access at 0 ? ? data 15 to 8 data 7 to 0 ? ? assert assert word access at 2 ? ? data 15 to 8 data 7 to 0 ? ? assert assert 1st time at 0 ? ? data 15 to 8 data 7 to 0 ? ? assert assert longword access at 0 2nd time at 2 ? ? data 31 to 24 data 23 to 16 ? ? assert assert
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 388 of 950 rej09b0079-0200 table 12.11 8-bit external device/little endian a ccess and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? ? data 7 to 0 ? ? ? assert byte access at 1 ? ? ? data 7 to 0 ? ? ? assert byte access at 2 ? ? ? data 7 to 0 ? ? ? assert byte access at 3 ? ? ? data 7 to 0 ? ? ? assert 1st time at 0 ? ? ? data 7 to 0 ? ? ? assert word access at 0 2nd time at 1 ? ? ? data 15 to 8 ? ? ? assert 1st time at 2 ? ? ? data 7 to 0 ? ? ? assert word access at 2 2nd time at 3 ? ? ? data 15 to 8 ? ? ? assert 1st time at 0 ? ? ? data 7 to 0 ? ? ? assert 2nd time at 1 ? ? ? data 15 to 8 ? ? ? assert 3rd time at 2 ? ? ? data 23 to 16 ? ? ? assert longword access at 0 4th time at 3 ? ? ? data 31 to 24 ? ? ? assert
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 389 of 950 rej09b0079-0200 12.5.2 normal space interface basic timing: for access to a normal space, this lsi uses strobe signal output in consideration of the fact that mainly static ram will be directly connected. when using sram with a byte- selection pin, see section 12.5.7, byte-selecti on sram interface. figure 12.3 shows the basic timings of normal space access. a no-wait norm al access is completed in two cycles. the bs signal is asserted for one cycle to indicate the start of a bus cycle. ckio note: * the waveform for dackn is when active low is specified. a25 to a0 rd/ wr rd/ wr d31 to d0 dackn * csn t1 t2 rd wen ( ben ) bs d31 to d0 read write figure 12.3 normal space basi c access timing (access wait 0) there is no access size specification when reading. the correct access start ad dress is output in the least significant bit of the address, but since there is no access size specificati on, 32 bits are always
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 390 of 950 rej09b0079-0200 read in case of a 32-bit device, and 16 bits in case of a 16-bit device. when writing, only the wen ( ben ) signal for the byte to be written is asserted. it is necessary to output the data that has been read using rd when a buffer is established in the data bus. the rd/ wr signal is in a read state (high output ) when no access has been carried out. therefore, care must be taken when controlling th e external data buffer, to avoid collision. figures 12.4 and 12.5 show the basic timings of normal space accesses. if the wm bit of the csnwcr is cleared to 0, a tnop cycle is inserted to evaluate the external wa it (figure 12.4). if the wm bit of the csnwcr is set to 1, external wa its are ignored and no t nop cycle is inserted (figure 12.5).
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 391 of 950 rej09b0079-0200 ckio a25 to a0 rd rd/ wr d15 to d0 wen ( ben ) d15 to d0 dackn bs wait csn t1 t2 tnop t1 t2 read write * note: * the waveform for dackn is when active low is specified. figure 12.4 continuous acce ss for normal space 1, bus width = 16 bits, longword access, csnwcr.wm bit = 0 (access wa it = 0, cycle wait = 0)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 392 of 950 rej09b0079-0200 ckio a25 to a0 rd/ wr d15 to d0 dackn csn t1 t2 t1 t2 rd wen ( ben ) bs wait d15 to d0 read write * note: * the waveform for dackn is when active low is specified. figure 12.5 continuous acce ss for normal space 2, bus width = 16 bits, longword access, csnwcr.wm bit = 1 (access wa it = 0, cycle wait = 0)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 393 of 950 rej09b0079-0200 a16 a0 cs oe i/o7 i/o0 we a18 a2 csn rd d31 d24 we3 ( be3 ) d23 d16 we2 ( be2 ) d15 d8 we1 ( be1 ) d7 d0 we0 ( be0 ) this lsi 128k 8-bit sram a16 a0 cs oe i/o7 i/o0 we a16 a0 cs oe i/o7 i/o0 we a16 a0 cs oe i/o7 i/o0 we figure 12.6 example of 32-bit data-width sram connection
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 394 of 950 rej09b0079-0200 a16 a0 cs oe i/o7 i/o0 we a17 a1 csn rd d15 d8 we1 ( be1 ) d7 d0 we0 ( be0 ) this lsi 128k 8-bit sram a16 a0 cs oe i/o7 i/o0 we figure 12.7 example of 16-bit data-width sram connection this lsi 128 k x 8 bits sram a16 a0 cs oe i/o7 i/o0 we . . . a16 a0 csn rd d7 d0 we0 ( be0 ) . . . . . . . . . figure 12.8 example of 8-bi t data-width sram connection
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 395 of 950 rej09b0079-0200 12.5.3 access wait control wait cycle insertion on a normal space access can be controlled by the settings of bits wr3 to wr0 in csnwcr. it is possible for areas 4, 5a, and 5b to insert wait cycles independently in read access and in write access. the areas other th an 4, 5a, and 5b have common access wait for read cycle and write cycle. the specified number of tw cycles is inserted as wait cycles in a normal space access shown in figure 12.9. t1 ckio a25 to a0 csn rd/ wr rd d31 to d0 d31 to d0 wen ( ben ) bs tw read write t2 dackn * note: * the waveform for dackn is when active low is specified. figure 12.9 wait timing for normal space access (software wait only) when the wm bit in csnwcr is clear ed to 0, the external wait input wait signal is also sampled. wait pin sampling is shown in figure 12.10. a 2-cycle wait is specified as a software wait. the wait signal is sampled on the falling edge of ckio at the transition from the t1 or tw cycle to the t2 cycle.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 396 of 950 rej09b0079-0200 t1 ckio a25 to a0 csn rd/ wr rd d 31 to d0 wen ( ben ) d31 to d0 wait tw tw twx t2 read write bs wait states inserted by wait signal dackn * note: * the waveform for dackn is when active low is specified. figure 12.10 wait state timing for norm al space access (wait state insertion by wait signal)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 397 of 950 rej09b0079-0200 12.5.4 csn assert period expansion the number of cycles from csn assertion to rd and wen ( ben ) assertion can be specified by setting bits sw1 and sw0 in csnwcr. the number of cycles from rd and wen ( ben ) negation to csn negation can be specified by setting bits hw1 and hw0. therefore, a flexible interface to an external device can be obtained. figure 12.11 sh ows an example. a th cycle and a tf cycle are added before and after an ordinary cy cle, respectively. in these cycles, rd and wen ( ben ) are not asserted, while other signals are asserted. the data output is prolonged to the tf cycle, and this prolongation is useful for devices with slow writing operations. t1 ckio a25 to a0 csn rd/ wr rd d31 to d0 d31 to d0 wen ( ben ) bs th read write t2 dackn * tf note: * the waveform for dackn is when active low is specified. figure 12.11 csn assert period expansion
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 398 of 950 rej09b0079-0200 12.5.5 sdram interface sdram direct connection: the sdram that can be connected to this lsi is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the a10 pin for setting precharge mode in read and write command cycles. the control signals for dir ect connection of sdram are ras , cas , rd/ wr , dqmuu, dqmul, dqmlu, dqmll, cke, cs2 , and cs3 . all the signals other than cs2 and cs3 are common to all areas, and signals other than cke are valid when cs2 or cs3 is asserted. sdram can be connected to up to 2 spaces. the data bu s width of the area that is connected to sdram can be set to 32 or 16 bits. burst read/single write (burst length 1) and burst re ad/burst write (burst length 1) are supported as the sdram operating mode. commands for sdram can be specified by ras , cas , rd/ wr , and specific address signals. these commands are shown below. ? nop ? auto-refresh (ref) ? self-refresh (self) ? all banks precharge (pall) ? specified bank precharge (pre) ? bank active (actv) ? read (read) ? read with precharge (reada) ? write (writ) ? write with precharge (writa) ? write mode register (mrs) the byte to be accessed is specified by dq muu, dqmul, dqmlu, and dqmll. reading or writing is performed for a byte whose corresponding dqmxx is low. for details on the relationship between dqmxx and the byte to be accessed, refer to section 12.5.1, endian/access size and data alignment. figures 12.12 and 12.13 show examples of the connection of the sdram with the lsi.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 399 of 950 rej09b0079-0200 a15 a2 cke ckio csn ras cas rd/ wr d31 d16 dqmuu dqmul d15 d0 dqmlu dqmll 64-mbit synchronous sdram (1m x 16 bits x 4 banks) . . . a13 a0 cke clk cs ras cas we i/o15 i/o0 dqmu dqml . . . . . . . . . . . . a13 a0 cke clk cs ras cas we i/o15 i/o0 dqmu dqml . . . . . . this lsi figure 12.12 example of 32-bit data-width sdram connection
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 400 of 950 rej09b0079-0200 a14 a1 cke ckio csn ras cas rd/ wr d15 d0 dqmlu dqmll 64-mbit synchronous sdram (1m x 16 bits x 4 banks) . . . a13 a0 cke clk cs ras cas we i/o15 i/o0 dqmu dqml . . . . . . . . . this lsi figure 12.13 example of 16-bit data-width sdram connection address multiplexing: an address multiplexing is specified so that sdram can be connected without external multiplexing circuitry according to the setting of bits bsz[1:0]in csnbcr, axrow[1:0] and axcol[1:0] in sdcr. tables 12.12 to 12.17 show the relationship between the settings of bits bsz[1:0], axrow[1:0], and axcol[1:0] and the bits output at the address pins. do not specify those bits in the manner other than this table, otherwise the operation of this lsi is not guaranteed. a25 to a18 are not multiplexed an d the original values of address are always output at these pins. when the data bus width is 16 bits (bsz[1:0] =b?10), a0 of sdram specifies a word address. therefore, connect this a0 pin of sdram to the a1 pin of the lsi; the a1 pin of sdram to the a2 pin of the lsi, and so on. when the data bus width is 32 bits (bsz[1:0] =b?11), the a0 pin of sdram specifies a longword addres s. therefore, connect this a0 pin of sdram to the a2 pin of the lsi; the a1 pin of sdram to the a3 pin of the lsi, and so on.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 401 of 950 rej09b0079-0200 table 12.12 relationship between a2/3bs z[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (1)-1 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 00 (11 bits) 00 (8 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a25 a17 a16 a24 a16 a15 a23 a15 unused a14 a22 * 2 a22 * 2 a12 (ba1) * 3 a13 a21 * 2 a21 * 2 a11 (ba0) specifies bank a12 a20 l/h * 1 a10/ap specifies address/precharge a11 a19 a11 a9 a10 a18 a10 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 402 of 950 rej09b0079-0200 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 00 (11 bits) 00 (8 bits) output pin of this lsi row address output column address output synchronous dram pin function a1 a9 a1 a0 a8 a0 unused example of connected memory 64-mbit product (512 kwords x 32 bits x 4 banks, column 8 bits product): 1 16-mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 2 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification 3. if the number of 16-mbit sdram (512 kwords 16 bits 2 banks: pin with 8-bit column) is two, the bank address specificat ion is not required. therefore, the bank address should be not used.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 403 of 950 rej09b0079-0200 table 12.12 relationship between a2/3bs z[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (1)-2 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 01 (12 bits) 00 (8 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a24 a17 a16 a23 a16 unused a15 a23 * 2 a23 * 2 a13 (ba1) a14 a22 * 2 a22 * 2 a12 (ba0) specifies bank a13 a21 a13 a11 address a12 a20 l/h * 1 a10/ap specifies address/precharge a11 a19 a11 a9 a10 a18 a10 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 a9 a1 a0 a8 a0 unused example of connected memory 128-mbit product (1 mword x 32 bits x 4 banks, column 8 bits product): 1 64-mbit product (1 mword x 16 bits x 4 banks, column 8 bits product): 2 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 404 of 950 rej09b0079-0200 table 12.13 relationship between a2/3bs z[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (2)-1 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 01 (12 bits) 01 (9 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a26 a17 a16 a25 a16 unused a15 a24 * 2 a24 * 2 a13 (ba1) a14 a23 * 2 a23 * 2 a12 (ba0) specifies bank a13 a22 a13 a11 address a12 a21 l/h * 1 a10/ap specifies address/precharge a11 a20 a11 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 a10 a1 a0 a9 a0 unused example of connected memory 256-mbit product (2 mwords x 32 bits x 4 banks, column 9 bits product): 1 128-mbit product (2 mwords x 16 bits x 4 banks, column 9 bits product): 2 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 405 of 950 rej09b0079-0200 table 12.13 relationship between a2/3bs z[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (2)-2 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 01 (12 bits) 10 (10 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a27 a17 a16 a26 a16 unused a15 a25 * 2 a25 * 2 a13 (ba1) a14 a24 * 2 a24 * 2 a12 (ba0) specifies bank a13 a23 a13 a11 address a12 a22 l/h * 1 a10/ap specifies address/precharge a11 a21 a11 a9 a10 a20 a10 a8 a9 a19 a9 a7 a8 a18 a8 a6 a7 a17 a7 a5 a6 a16 a6 a4 a5 a15 a5 a3 a4 a14 a4 a2 a3 a13 a3 a1 address
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 406 of 950 rej09b0079-0200 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 01 (12 bits) 10 (10 bits) output pin of this lsi row address output column address output synchronous dram pin function a2 a12 a2 a0 a1 a11 a1 a0 a10 a0 unused example of connected memory 512-mbit product (4 mwords x 32 bits x 4 banks, column 10 bits product): 1 256-mbit product (4 mwords x 16 bits x 4 banks, column 10 bits product): 2 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 407 of 950 rej09b0079-0200 table 12.14 relationship between a2/3bs z[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (3) setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 10 (13 bits) 01 (9 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a26 a17 unused a16 a25 * 2 a25 * 2 a14 (ba1) a15 a24 * 2 a24 * 2 a13 (ba0) specifies bank a14 a23 a14 a12 a13 a22 a13 a11 address a12 a21 l/h * 1 a10/ap specifies address/precharge a11 a20 a11 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 a10 a1 a0 a9 a0 unused example of connected memory 512-mbit product (4 mwords x 32 bits x 4 banks, column 9 bits product): 1 256-mbit product (4 mwords x 16 bits x 4 banks, column 9 bits product): 2 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 408 of 950 rej09b0079-0200 table 12.15 relationship between a2/3bs z[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (4)-1 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 10 (16 bits) 00 (11 bits) 00 (8 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a25 a17 a16 a24 a16 a15 a23 a15 a14 a22 a14 unused a13 a21 a21 a12 a20 * 2 a20 * 2 a11 (ba0) specifies bank a11 a19 l/h * 1 a10/ap specifies address/precharge a10 a18 a10 a9 address a9 a17 a9 a8 a8 a16 a8 a7 a7 a15 a7 a6 a6 a14 a6 a5 a5 a13 a5 a4 a4 a12 a4 a3 a3 a11 a3 a2 a2 a10 a2 a1 a1 a9 a1 a0 a0 a8 a0 unused example of connected memory 16-mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 1 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 409 of 950 rej09b0079-0200 table 12.15 relationship between a2/3bs z[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (4)-2 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 10 (16 bits) 01 (12 bits) 00 (8 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a25 a17 a16 a24 a16 a15 a23 a15 unused a14 a22 * 2 a22 * 2 a13 (ba1) a13 a21 * 2 a21 * 2 a12 (ba0) specifies bank a12 a20 a12 a11 address a11 a19 l/h * 1 a10/ap specifies address/precharge a10 a18 a10 a9 a9 a17 a9 a8 a8 a16 a8 a7 a7 a15 a7 a6 a6 a14 a6 a5 a5 a13 a5 a4 a4 a12 a4 a3 a3 a11 a3 a2 a2 a10 a2 a1 a1 a9 a1 a0 address a0 a8 a0 unused example of connected memory 64-mbit product (1 mword x 16 bits x 4 banks, column 8 bits product): 1 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 410 of 950 rej09b0079-0200 table 12.16 relationship between a2/3bs z[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (5)-1 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 10 (16 bits) 01 (12 bits) 01 (9 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a26 a17 a16 a25 a16 a15 a24 a15 unused a14 a23 * 2 a23 * 2 a13 (ba1) a13 a22 * 2 a22 * 2 a12 (ba0) specifies bank a12 a21 a12 a11 address a11 a20 l/h * 1 a10/ap specifies address/precharge a10 a19 a10 a9 a9 a18 a9 a8 a8 a17 a8 a7 a7 a16 a7 a6 a6 a15 a6 a5 a5 a14 a5 a4 a4 a13 a4 a3 a3 a12 a3 a2 a2 a11 a2 a1 a1 a10 a1 a0 address a0 a9 a0 unused example of connected memory 128-mbit product (2 mwords x 16 bits x 4 banks, column 9 bits product): 1 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 411 of 950 rej09b0079-0200 table 12.16 relationship between a2/3bs z[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (5)-2 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 10 (16 bits) 01 (12 bits) 10 (10 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a27 a17 a16 a26 a16 a15 a25 a15 unused a14 a24 * 2 a24 * 2 a13 (ba1) a13 a23 * 2 a23 * 2 a12 (ba0) specifies bank a12 a22 a12 a11 address a11 a21 l/h * 1 a10/ap specifies address/precharge a10 a20 a10 a9 a9 a19 a9 a8 a8 a18 a8 a7 a7 a17 a7 a6 a6 a16 a6 a5 a5 a15 a5 a4 a4 a14 a4 a3 a3 a13 a3 a2 a2 a12 a2 a1 a1 a11 a1 a0 address a0 a10 a0 unused example of connected memory 256-mbit product (4 mwords x 16 bits x 4 banks, column 10 bits product): 1 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 412 of 950 rej09b0079-0200 table 12.17 relationship between a2/3bs z[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (6)-1 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 10 (16 bits) 10 (13 bits) 01 (9 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a26 a17 a16 a25 a16 unused a15 a24 * 2 a24 * 2 a14 (ba1) a14 a23 * 2 a23 * 2 a13 (ba0) specifies bank a13 a22 a13 a12 a12 a21 a12 a11 address a11 a20 l/h * 1 a10/ap specifies address/precharge a10 a19 a10 a9 a9 a18 a9 a8 a8 a17 a8 a7 a7 a16 a7 a6 a6 a15 a6 a5 a5 a14 a5 a4 a4 a13 a4 a3 a3 a12 a3 a2 a2 a11 a2 a1 a1 a10 a1 a0 address a0 a9 a0 unused example of connected memory 256-mbit product (4 mwords x 16 bits x 4 banks, column 9 bits product): 1 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 413 of 950 rej09b0079-0200 table 12.17 relationship between a2/3bs z[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (6)-2 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 10 (16 bits) 10 (13 bits) 10 (10 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a27 a17 a16 a26 a16 unused a15 a25 * 2 a25 * 2 a14 (ba1) a14 a24 * 2 a24 * 2 a13 (ba0) specifies bank a13 a23 a13 a12 a12 a22 a12 a11 address a11 a21 l/h * 1 a10/ap specifies address/precharge a10 a20 a10 a9 a9 a19 a9 a8 a8 a18 a8 a7 a7 a17 a7 a6 a6 a16 a6 a5 a5 a15 a5 a4 a4 a14 a4 a3 a3 a13 a3 a2 a2 a12 a2 a1 a1 a11 a1 a0 address a0 a10 a0 unused example of connected memory 512-mbit product (8 mwords x 16 bits x 4 banks, column 10 bits product): 1 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 414 of 950 rej09b0079-0200 burst read: a burst read occurs in the fo llowing cases with this lsi. 1. access size in reading is larger than data bus width. 2. 16-byte transf er in cache miss. 3. 16-byte transfer in dmac or e-dmac (access to non-cachable area) this lsi always accesses the sdram with burst length 1. for example, read access of burst length 1 is performed consecutively 4 times to read 16-byte continuous data from the sdram that is connected to a 32-bit data bus. table 12.18 shows the relatio nship between the access size an d the number of bursts. table 12.18 relationship between access size and number of bursts bus width access size number of bursts 8 bits 1 16 bits 1 32 bits 2 16 bits 16 bytes 8 8 bits 1 16 bits 1 32 bits 1 32 bits 16 bytes 4 figures 12.14 and 12.15 show a timing chart in burst read. in burst read, an actv command is output in the tr cycle, the read command is issued in the tc1, tc2, and tc3 cycles, the reada command is issued in the tc4 cycle, and the read data is received at the rising edge of the external clock (ckio) in the td1 to td4 cycles. the tap cycle is used to wait fo r the completion of an auto-precharge induced by th e reada command in the sdram. in the tap cycle, a new command will not be issued to the same bank. however, access to another cs space or another bank in the same sdram space is enabled. the nu mber of tap cycles is specified by the trp1 and trp0 bits in cs3wcr. in this lsi, wait cycles can be inserted by specifying each bi t in csnwcr to connect the sdram in variable frequencies. figure 12.15 shows an example in which wait cycles are inserted. the number of cycles from the tr cycle where the actv command is output to the tc1 cycle where the reada command is output can be specified using the trcd1 and t rcd0 bits in cs3wcr. if the trcd1 and trcd0 bits specify one cycle or more, a trw cycle where the nop command is issued is inserted between the tr cycle and tc 1 cycle. the number of cycles from the tc1 cycle
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 415 of 950 rej09b0079-0200 where the reada command is output to the td1 cycle where the read data is latched can be specified for the cs2 and cs3 spaces independently, using the a2cl1 and a2cl0 bits in cs2wcr or the a3cl1 and a3cl0 bits in cs 3wcr and trcd0 bit in cs3wcr. the number of cycles from tc1 to td1 corresponds to the synchronous dram cas latency. the cas latency for the synchronous dram is normally defined as up to three cycles. however, the cas latency in this lsi can be specified as 1 to 4 cycles. this cas latency can be achieved by connecting a latch circuit between this lsi and the synchronous dram. tc4 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tap dackn * 2 tr tc2 tc3 tc1 td4 tde td2 td3 td1 a12/a11 * 1 cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 12.14 burst read basic timing (auto precharge)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 416 of 950 rej09b0079-0200 tc4 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tap dackn * 2 tr tc2 tc3 tc1 td4 tde td2 td3 td1 a12/a11 * 1 cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. trw tw figure 12.15 burst read wait sp ecification timing (auto precharge)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 417 of 950 rej09b0079-0200 single read: a read access ends in one cycle when data exists in non-cachab le region and the data bus width is larger than or equal to access size. as the burst length is set to 1 in synchronous dram burst read/single write mode, only the required data is output. consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. figure 12.16 shows the single read basic timing. ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tap dackn * 2 tr tc1 tde td1 a12/a11 * 1 cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. figure 12.16 basic timing fo r single read (auto precharge)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 418 of 950 rej09b0079-0200 burst write: a burst write occurs in the fo llowing cases in this lsi. 1. access size in writing is larger than data bus width. 2. copyback of the cache 3. 16-byte transfer in dmac or e-dmac (access to non-cachable region) this lsi always accesses sdram with burst length 1. for example, write access of burst length 1 is performed continuously 4 times to write 16-byte continuous data to the sdram that is connected to a 32-bit data bus. the relationship between the access size and the number of bursts is shown in table 12.18. figure 12.17 shows a timing chart for burst writes. in burst write, an actv command is output in the tr cycle, the writ command is issued in the tc1, tc2, and tc3 cycles, and the writa command is issued to execute an auto-precharge in the tc4 cycle. in the write cycle, the write data is output simultaneously with the write comm and. after the write command with the auto- precharge is output, the trw1 cycle that waits for the auto-precharge initiation is followed by the tap cycle that waits for completion of the auto-p recharge induced by the writa command in the sdram. in the tap cycle, a new command will not be issued to the same bank. however, access to another cs space or an other bank in the same sdram space is enabled. the number of trw1 cycles is specified by the trwl1 and trwl0 b its in cs3wcr. the number of tap cycles is specified by the trp1 and trp0 bits in cs3wcr.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 419 of 950 rej09b0079-0200 tc4 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tap dackn * 2 tr tc2 tc3 tc1 trwl a12/a11 * 1 cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. figure 12.17 basic timing fo r burst write (auto precharge)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 420 of 950 rej09b0079-0200 single write: a write access ends in one cycle when data is written in non-cachable region and the data bus width is larger than or equal to access size. figure 12.18 shows the single write basic timing. ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tap dackn * 2 tr tc1 trwl a12/a11 * 1 cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. figure 12.18 basic timing for single write (auto-precharge) bank active: the synchronous dram bank function is used to support high-speed accesses to the same row address. when the bactv bit in sdcr is 1, accesses are performed using commands without auto-precharge (read or writ). this function is called bank-active function. this function is valid only for either the upper or lower bits of area 3. when area 3 is set to bank- active mode, area 2 should be set to normal sp ace or byte-selection sram. when areas 2 and 3 are both set to sdram, auto precharge mode must be set. when a bank-active function is used, prechargin g is not performed when the access ends. when accessing the same row address in the same bank , it is possible to is sue the read or writ command immediately, without issuing an actv command. as synchronous dram is internally divided into several banks, it is possible to activate one row address in each bank. if the next access is to a different row address, a pre command is first issued to precharge the relevant bank,
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 421 of 950 rej09b0079-0200 then when precharging is comp leted, the access is performed by issuing an actv command followed by a read or writ command. if this is followed by an access to a different row address, the access time will be longer because of the precharg ing performed after the access request is issued. the number of cycles between issuance of the pre command and the actv command is determined by the trp[1:0] bits in csnwcr. in a write, when an auto-precharge is performed, a command cannot be issued to the same bank for a period of trwl + tap cycles after issuan ce of the writa command. when bank active mode is used, read or writ commands can be issued successively if the row ad dress is the same. the number of cycles can thus be reduced by trwl + tap cycles for each write. there is a limit on tras, the time for placing each bank in the active state. if there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program executio n, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tras. a burst read cycle without auto-precharge is shown in figure 12.19, a burst read cycle for the same row address in figure 12.20, and a burst read cy cle for different row addresses in figure 12.21. similarly, a single write cycle without auto-prech arge is shown in figure 12.22, a single write cycle for the same row address in figure 12.23, and a single write cycle for different row addresses in figure 12.24. in figure 12.20, a tnop cycle in which no operation is performed is insert ed before the tc cycle that issues the read command. th e tnop cycle is inserted to ac quire two cycles of cas latency for the dqmxx signal that specifies the read byte in the data read from the sdram. if the cas latency is specified as two cycles or more, the tnop cycle is not inserted because the two cycles of latency can be acquired even if the dqmxx signal is asserted after the tc cycle. when bank active mode is set, if only accesses to the respective banks in the area 3 space are considered, as long as accesses to the same row address co ntinue, the operation starts with the cycle in figure 12.19 or 12.22, followed by repe tition of the cycle in figure 12.20 or 12.23. an access to a different area during this time has no effect. if there is an access to a different row address in the bank active state, after this is detected the bus cy cle in figure 12.21 or 12.24 is executed instead of that in figure 12.20 or 12.23. in bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 422 of 950 rej09b0079-0200 tc4 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs dackn * 2 tr tc2 tc3 tc1 td4 td2 td3 td1 tde a12/a11 * 1 cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. figure 12.19 burst read ti ming (no auto precharge)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 423 of 950 rej09b0079-0200 tc4 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs dackn * 2 tc2 tc3 tc1 tnop td4 tde td2 td3 td1 a12/a11 * 1 cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 12.20 burst read timing (bank active, same row address)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 424 of 950 rej09b0079-0200 tc4 ckio a25 to a0 csn rd/ wr d31 to d0 bs tpw dackn * 2 tp tc2 tc3 tc1 td4 td2 td3 td1 a12/a11 * 1 tde tr notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. ras dqmxx cas figure 12.21 burst read timing (b ank active, differen t row addresses)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 425 of 950 rej09b0079-0200 ckio a25 to a0 csn rd/ wr d31 to d0 bs dackn * 2 tr tc1 a12/a11 * 1 ras dqmxx cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. figure 12.22 single write timing (no auto precharge)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 426 of 950 rej09b0079-0200 ckio a25 to a0 csn rd/ wr d31 to d0 bs dackn * 2 tnop tc1 a12/a11 * 1 ras dqmxx cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. figure 12.23 single write timing (bank active, same row address)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 427 of 950 rej09b0079-0200 ckio a25 to a0 csn rd/ wr d31 to d0 bs tpw dackn * 2 tp tc1 a12/a11 * 1 tr ras dqmxx cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. figure 12.24 single write timing (b ank active, different row addresses) refreshing: this lsi has a function for controlling synchronous dram refreshing. auto- refreshing can be performed by clearing the rmode bit to 0 and setting the rfsh bit to 1 in sdcr. a continuous refreshing can be performed by setting the rrc[2:0] bits in rtcsr. if synchronous dram is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the rmode bit and the rfsh bit to 1.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 428 of 950 rej09b0079-0200 1. auto-refreshing refreshing is performed at intervals determined by the input clock selected by bits cks[2:0] in rtcsr, and the value set by in rtcor. the value of bits cks[2:0] in rtcor should be set so as to satisfy the refresh interval stipul ation for the synchronous dram used. first make the settings for rtcor, rtcnt, and the rmode and rfsh bits in sdcr, then make the cks[2:0] and rrc[2:0] settings. when the clock is selected by bits cks[2:0], rtcnt starts counting up from the value at that time. the rt cnt value is constantly compared with the rtcor value, and if the two values are the same , a refresh request is generated and an auto- refresh is performed for the nu mber of times specified by the rrc[2:0]. at the same time, rtcnt is cleared to 0 and the count-up is restar ted. figure 12.25 shows the auto-refresh cycle timing. after starting, the auto refreshing, pall command is issued in the tp cycle to make all the banks to precharged state from active state when some bank is being precharged. then ref command is issued in the trr cycle after insertin g idle cycles of which number is specified by the trp[1:0]bits in csnwcr. a new command is not issued for the duration of the number of cycles specified by the trc[1:0] bits in csnw cr after the trr cycle. the trc[1:0] bits must be set so as to satisfy the sdram refreshin g cycle time stipulation (trc). a nop cycle is inserted between the tp cycle and trr cycle when the setting value of the trp[1:0] bits in csnwcr is longer than or equal to 1 cycle.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 429 of 950 rej09b0079-0200 ckio a25 to a0 csn rd/ wr d31 to d0 bs tpw dackn * 2 tp trr a12/a11 * 1 trc trc trc hi-z ras dqmxx cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. figure 12.25 auto-refresh timing 2. self-refreshing self-refresh mode in which the refresh timing and refresh addresses are generated within the synchronous dram. self-refreshing is activated by setting both the rmode bit and the rfsh bit in sdcr to 1. after starting the self-refreshing, pall command is issued in tp cycle after the completion of th e pre-charging bank. a self command is then issued after inserting idle cycles of which number is specified by the trp[1:0] bits in csnwsr. synchronous dram cannot be accessed while in th e self-refresh state. self-refresh mode is cleared by clearing the rmode bit to 0. after self-refresh mode has been cleared, command issuance is disabled for the nu mber of cycles specified by the trc[1:0] bits in csnwcr.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 430 of 950 rej09b0079-0200 self-refresh timing is shown in figure 12.26. settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. when self-re freshing is activated from the st ate in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if the rfsh bit is set to 1 and the rm ode bit is cleared to 0 when self-refresh mode is cleared. if the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into c onsideration when setting the initial value of rtcnt. making the rtcnt value 1 less than the rtcor value will enable refreshing to be started immediately. after self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the lsi standby function, and is maintained even after recovery from standby mode by an interrupt. the self-refresh state is not cleared by a manual reset. in case of a power-on reset, the bus state contro ller?s registers are initialized, and therefore the self-refresh state is cleared.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 431 of 950 rej09b0079-0200 ckio a25 to a0 csn rd/ wr d31 to d0 bs tpw dackn * 2 tp trr a12/a11 * 1 trc trc trc hi-z trc trc cke ras dqmxx cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. figure 12.26 se lf-refresh timing relationship between refresh requests and bus cycles: if a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. if a refresh request occurs while the bus is released by the bus arbitration function, the refresh will not be executed until the bus mastership is acquired. this lsi supports requests by the refout pin for the bus mastership while waiting for the refresh request. the refout pin is asserted low until the bus mastership is acquired. if a new refresh request occurs while waiting for th e previous refresh request, the previous refresh request is deleted. to refresh correctly, a bus cy cle longer than the refr esh interval or the bus mastership occupation must be prevented from occurring. if a bus mastership is requested during self-refresh, the bus will not be released until the self-refresh is completed. low-frequency mode: when the slow bit in sdcr is set to 1, output of commands, addresses, and write data, and fetch of read data are perfor med at a timing suitable for operating sdram at a low frequency.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 432 of 950 rej09b0079-0200 figure 12.27 shows the access timing in low-frequency mode. in this mode, commands, addresses, and write data are output in synchronization with the falling edge of ckio, which is half a cycle delayed than the normal timing. read data is fetched at the rising edge of ckio, which is half a cycle faster than the normal timing. this timi ng allows the hold time of commands, addresses, write data, and read data to be extended. if sdram is operated at a high frequency with the slow bit set to 1, the setup time of commands, addresses, write data, and read data are not guaranteed. take the operating frequency and timing design into consideration when making the slow bit setting. ckio a25 to a0 csn rd/ wr d31 to d0 bs tc1 dackn * 2 tr td1 a12/a11 * 1 tde tap tr tc1 tnop trwl tap cke ras dqmxx cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. (high) figure 12.27 access timing in low-frequency mode power-down mode: if the pdown bit in sd cr is set to 1, the sdra m is placed in the power- down mode by bringing the cke signal to the lo w level in the non-access cycle. this power-down mode can effectively lower the power consumptio n in the non-access cycle. however, please note
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 433 of 950 rej09b0079-0200 that if an access occurs in pow er-down mode, a cycle of overhea d occurs because a cycle that asserts the cke in order to cancel power-down mode is inserted. figure 12.28 show s the access timing in power-down mode. ckio a25 to a0 csn rd/ wr d31 to d0 bs tnop dackn * 2 power-down tr a12/a11 * 1 tc1 td1 tde tap power-down cke ras dqmxx cas notes: 1.address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. figure 12.28 access timi ng in power-down mode power-on sequence: in order to use synchronous dram, mode setting must first be performed after powering on. to perform synchronous dram initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous dram mode register. in synchronous dram mode register setting, the addr ess signal value at that time is latched by a combination of the csn , ras , cas , and rd/ wr signals. if the value to be set is x, the bus state controller provides for value x to be written to the synchronous dram mode register by performing a write to address h'a4fd4000 + x for area 2 synchronous dram, and to address h'a4fd5000 + x for area 3 synchronous dram. in this operation the data is ignored, but the mode write is performed as a byte-size access. to set burst read/single write, cas latency 2 to 3,
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 434 of 950 rej09b0079-0200 wrap type = sequential, and burst length 1 supported by the lsi, arbitrary data is written in a byte- size access to the addresses shown in table 12.19. in this time 0 is output at the external address pins of a12 or later. table 12.19 access address in sdram mode register write ? setting for area 2 (sdmr2) burst read/single write (burst length 1): data bus width cas latency access address external address pin 16 bits 2 h a4fd4440 h 0000440 3 h a4fd4460 h 0000460 32 bits 2 h a4fd4880 h 0000880 3 h a4fd48c0 h 00008c0 burst read/burst write (burst length 1): data bus width cas latency access address external address pin 16 bits 2 h a4fd4040 h 0000040 3 h a4fd4060 h 0000060 32 bits 2 h a4fd4080 h 0000080 3 h a4fd40c0 h 00000c0 ? setting for area 3 (sdmr3) burst read/single write (burst length 1): data bus width cas latency access address external address pin 16 bits 2 h a4fd5440 h 0000440 3 h a4fd5460 h 0000460 32 bits 2 h a4fd5880 h 0000880 3 h a4fd58c0 h 00008c0
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 435 of 950 rej09b0079-0200 burst read/burst write (burst length 1): data bus width cas latency access address external address pin 16 bits 2 h a4fd5040 h 0000040 3 h a4fd5060 h 0000060 32 bits 2 h a4fd5080 h 0000080 3 h a4fd50c0 h 00000c0 mode register setting timing is shown in figure 12.29. a pall command (all bank precharge command) is firstly issued. a ref command (auto refresh command) is then issued 8 times. an mrs command (mode register write command) is finally issued. idle cycles, of which number is specified by the trp[1:0] bits in csnwcr, are inserted between the pall and the first ref. idle cycles, of which number is specified by the t rc[1:0]bits in csnwcr, are inserted between ref and ref, and between the 8th ref and mrs. idle cycles, of which number is one or more, are inserted between the mrs and a command to be issued next. it is necessary to keep idle time of certain cy cles for sdram before issuing pall command after power-on. refer the manual of the sdram for the idle time to be needed. when the pulse width of the reset signal is longer then the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 436 of 950 rej09b0079-0200 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tpw dackn * 2 tp trr a12/a11 * 1 cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. trc trc tmw hi-z tnop trc trr trc ref ref mrs pall figure 12.29 write timing for sdram mode register (based on jedec) low-power sdram: the low-power sdram can be accessed using the same protocol as the normal sdram. the differences between the low-power sdram and no rmal sdram are that partial refresh takes place that puts only a part of the sdram in the self-refresh state during the self-refresh function, and that power consumption is low during refresh under user conditions such as the operating temperatur e. the partial refresh is effective in systems in which data in a work area other than the specific area can be lost without severe repercussions. for details, refer to the data sheet for the low-power sdram to be used. the low-power sdram supports the extension mode register (emrs) in addition to the mode registers as the normal sdram. this lsi supports issuing of the emrs command. the emrs command is issued accor ding to the conditions specified in table 12.20. for example, if data h'0yyyyyyy is written to address h'a4fd5xxx in long-word, the commands are issued to the cs3 space in the following sequen ce: pall -> ref x 8 -> mrs -> emrs. in this case, the mrs and emrs issue addresses are h'0000xxx and h'yyyyyyy, respectively. if data h'1yyyyyyy is written to address h'a4fd5xxx in long-word, the commands are issued to the cs3 space in the following sequence: pall -> mrs -> emrs.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 437 of 950 rej09b0079-0200 table 12.20 output addresses when emrs command is issued command to be issued access address access data write access size mrs command issue address emrs command issue address cs2 mrs h'a4fd4xxx h' ******** 16 bits h'0000xxx ? cs3 mrs h'a4fd5xxx h' ******** 16 bits h'0000xxx ? cs2 mrs +emrs (with refresh) h'a4fd4xxx h'0yyyyyyy 32 bits h'0000xxx h'yyyyyyy cs3 mrs +emrs (with refresh) h'a4fd5xxx h'0yyyyyyy 32 bits h'0000xxx h'yyyyyyy cs2 mrs +emrs (without refresh) h'a4fd4xxx h'1yyyyyyy 32 bits h'0000xxx h'yyyyyyy cs3 mrs +emrs (without refresh) h'a4fd5xxx h'1yyyyyyy 32 bits h'0000xxx h'yyyyyyy
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 438 of 950 rej09b0079-0200 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tpw dackn * 4 tp trr a12/a11 * 3 ba1 * 1 ba0 * 2 cas notes: 1. address pin to be connected to the ba1 pin of sdram. 2. address pin to be connected to the ba0 pin of sdram. 3. address pin to be connected to the a10 pin of sdram. 4. the waveform for dackn is when active low is specified. trc trc tmw hi-z tnop trc trr trc ref ref mrs temw tnop emrs pall figure 12.30 emrs command issue timing ? deep power-down mode the low-power sdram supports the deep power-down mode as a low-power consumption mode. in the partial self-refresh function, self-r efresh is performed on a specific area. in the deep power-down mode, self-refresh will not be performed on any memory area. this mode is effective in systems where a ll of the system memory area s are used as work areas. if the rmode bit of the sdcr is set to 1 while the deep and rfsh bits of the sdcr are set to 1, the low-power sdram enters the deep power-down mode. if the rmode bit is cleared to 0, the cke signal is pulled high to cancel the deep power-down mode. before executing an access after returning from the deep power-down mode, the power-up sequence must be re-executed.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 439 of 950 rej09b0079-0200 ckio cke a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tpw dackn * 2 tp tdpd a12/a11 * 1 cas notes: 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. trc hi-z trc trc trc trc figure 12.31 transition timing in deep power-down mode 12.5.6 burst rom (clock asynchronous) interface the burst rom (clock async hronous) interface is used to access a memory with a high-speed read function using a method of address switching called the burst mode or page mode. in a burst rom (clock asynchronous) interface, basically the same access as the normal space is performed, but the 2nd and subsequent accesses are performed only by changing the addres s, without negating the rd signal at the end of the 1st cycle. in the 2n d and subsequent accesses, addresses are changed at the falling edge of the ckio. for the 1st access cycle, the numb er of wait cycles specified by the w[3:0] bits in csnwcr is inserted. for the 2nd and subsequent access cycles, the number of wait cycles specified by the bw[1:0] bits in csnwcr is inserted. in the access to the burst ro m (clock asynchronous), the bs signal is asserted only to the first access cycle. an external wait input is valid only to the first access cycle. in the single access or write access that do no t perform the burst operation in the burst rom (clock asynchronous) interface, access timing is same as a normal space.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 440 of 950 rej09b0079-0200 table 12.21 lists a relationship between bus width, access size, an d the number of bursts. figure 12.32 shows a timing chart. table 12.21 relationship between bus wi dth, access size, an d number of bursts bus width ben bit access size number of bursts number of accesses not affected 8 bits 1 1 not affected 16 bits 2 1 not affected 32 bits 4 1 0 16 1 8 bits 1 16 bytes 4 4 not affected 8 bits 1 1 not affected 16 bits 1 1 not affected 32 bits 2 1 0 8 1 16 bits 1 16 bytes 2 4 not affected 8 bits 1 1 not affected 16 bits 1 1 not affected 32 bits 1 1 32 bits not affected 16 bytes 4 1
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 441 of 950 rej09b0079-0200 ckio a25 to a0 rd d31 to d0 dack wait cs t1 tw tw tb2 twb tb2 twb tb2 twb t2 rd/ wr bs figure 12.32 burst rom (clock asynch ronous) access (bus width = 32 bits, 16-byte transfer (number of bursts = 4), access wait for first time = 2, access wait for 2nd time and after = 1) 12.5.7 byte-selection sram interface the byte-selection sram interface is for access to an sram which ha s a byte-selection pin ( wen ( ben )). this interface has 16-bit data pins and accesses srams having upper and lower byte selection pins, such as ub and lb. when the bas bit in csnwcr is cleared to 0 (initial value), the write access timing of the byte- selection sram interface is the same as that fo r the normal space interface. while in read access of a byte-selection sr am interface, the byte-selection signal is output from the wen ( ben ) pin, which is different from that for the normal sp ace interface. the basic access timing is shown in figure 12.33. in write access, data is written to the memory according to the timing of the byte- selection pin ( wen ( ben )). for details, refer to the data sheet for the corresponding memory. if the bas bit in csnwcr is set to 1, the wen ( ben ) pin and rd/ wr pin timings change. figure 12.34 shows the basic access timing. in write access, data is writte n to the memory according to the timing of the write enable pin (rd/ wr ). the data hold timing from rd/ wr negation to data write must be acquired by setting the hw[1:0] bits in csnwcr. figure 12.35 shows the access timing when a software wait is specified.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 442 of 950 rej09b0079-0200 ckio a25 to a0 csn wen ( ben ) rd/ wr rd rd d31 to d0 d31 to d0 rd/ wr bs dackn * read write note: the waveform for dackn is when active low is specified. t1 t2 high figure 12.33 basic access timing fo r byte-selection sram (bas = 0)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 443 of 950 rej09b0079-0200 ckio a25 to a0 csn wen ( ben ) rd rd d31 to d0 d31 to d0 rd/ wr rd/ wr bs dackn * read write note: the waveform for dackn is when active low is specified. t1 t2 high figure 12.34 basic access timing fo r byte-selection sram (bas = 1)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 444 of 950 rej09b0079-0200 t2 ckio a25 to a0 csn rd/ wr wen ( ben ) d31 to d0 bs read write th dackn * note: the waveform for dackn is when active low is specified. th t1 tw rd rd/ wr d31 to d0 rd high figure 12.35 wait timing for byte-selection sram (bas = 1) (software wait only)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 445 of 950 rej09b0079-0200 a15 a0 cs oe we i/o15 i/o0 ub lb . . . . . . . . . a17 a2 csn rd rd/ wr d31 d16 we3 ( be3 ) we2 ( be2 ) d15 d0 we1 ( be1 ) we0 ( be0 ) this lsi 64 k x 16 bits sram . . . a15 a0 cs oe we i/o15 i/o0 ub lb . . . . . . . . . figure 12.36 example of connection with 32-bit data-width byte-selection sram this lsi a16 a1 csn rd rd/ wr d15 d0 we1 ( be1 ) we0 ( be0 ) a15 a0 cs oe we i/o 15 i/o 0 ub lb 64 k x 16 bits sram figure 12.37 example of connection with 16-bit data-width byte-selection sram
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 446 of 950 rej09b0079-0200 12.5.8 pcmcia interface with this lsi, if address map (2) is select ed using the map bit in cmncr, the pcmcia interface can be specified in areas 5 and 6. areas 5 and 6 in the physical space can be used for the ic memory card and i/o card interface define d in the jeida specifi cations version 4.2 (pcmcia2.1 rev. 2.1) by specifying the type[3:0] bits of csnbcr (n = 5b, 6b) to b?0101. in addition, the sa[1:0] bits of csnwcr (n = 5b, 6b) assign the upper or lower 32 mbytes of each area to an ic memory card or i/o card interface. for example, if the sa1 and sa0 bits of the cs5bwcr are set to 1 and cleared to 0, respect ively, the upper 32 m bytes and the lower 32 mbytes of area 5b are used as an ic memory card interface and i/o card interface, respectively. when the pcmcia interface is used, the bus size must be specified as 8 bits or 16 bits using the bsz[1:0] bits in cs5bbcr or cs6bbcr. figure 12.38 shows an example of a connecti on between this lsi and the pcmcia card. to enable insertion and removal of the pcmcia card during system power-on , a three-state buffer must be connected between the lsi and the pcmcia card. in the jeida and pcmcia standards, operation in the big endian mode is not clearly defined. consequently, an original definition is provided for the pcmcia interface in big endian mode in this lsi.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 447 of 950 rej09b0079-0200 this lsi pc card (memory i/o) a25 to a0 d7 to d0 ce1 ce2 oe we / pgm iord iowr reg a25 to a0 d7 to d0 d15 to d8 rd/ wr ce1a ce2a rd we iciord iciowr i/o port wait iois16 g g dir g g dir d15 to d8 wait iois16 cd1,cd2 card detection circuit figure 12.38 example of pcmcia interface connection basic timing for memory card interface: figure 12.39 shows the basic timing of the pcmcia ic memory card interface. if areas 5 and 6 in the physical space are speci fied as the pcmcia interface, accessing the common memory areas in areas 5 and 6 automatically accesses the ic memory card interface. if the external bus frequenc y (ckio) increases, the setup times and hold times for the address pins (a25 to a0) to rd and we, card enable signals ( ce1a , ce2a , ce1b , ce2b ), and write data (d15 to d0) become insufficient. to prevent this error, the lsi can specify the setup times and hold times for areas 5 and 6 in the physical space independently, using cs5bwcr and cs6bwcr. in the pcmcia inte rface, as in the norm al space interface, a software wait or hardware wait can be inserted using the wait pin. figure 12.40 shows the pcmcia memory bus wait timing.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 448 of 950 rej09b0079-0200 tpcm1w ckio a25 to a0 cexx rd/ wr rd d15 to d0 we d15 to d0 bs read write tpcm2 tpcm1 tpcm1w tpcm1w figure 12.39 basic access timing fo r pcmcia memory card interface tpcm1w ckio a25 to a0 cexx rd/ wr rd d15 to d0 we d15 to d0 bs read write tpcm2 tpcm0 tpcm1 tpcm1w tpcm0w tpcm2w tpcm1w tpcm1w wait figure 12.40 wait ti ming for pcmcia memo ry card interface (ted[3:0] = b 0010, teh[3:0] = b 0001, software wait = 1, hardware wait = 1)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 449 of 950 rej09b0079-0200 if all 32 mbytes of the memory space are us ed as an ic memory card interface, the reg signal that switches between the common memory and attribute memory can be generated by a port. if the memory space used for the ic memory card inte rface is 16 mbytes or less, the a24 pin can be used as the reg signal by using the memory space as a 16-mbyte common memory space and a 16-mbyte attribute memory space. pcmcia interface area is 32 mbytes (an i/o port is used as the reg ) area 5 : h'14000000 attribute memory/common memory i/o space attribute memory/common memory i/o space area 5 : h'16000000 area 6 : h'18000000 area 6 : h'1a000000 pcmcia interface area is 16 mbytes (a24 is used as the reg ) area 5 : h'14000000 attribute memory i/o space area 5 : h'15000000 area 5 : h'16000000 h'17000000 area 6 : h'18000000 area 6 : h'19000000 area 6 : h'1a000000 h'1b000000 common memory attribute memory i/o space common memory figure 12.41 example of pcmcia space assignment (cs5bwcr.sa[1:0] = b 10, cs6bwcr.sa[1:0] = b 10) basic timing for i/o card interface: figures 12.42 and 12.43 show the basic timings for the pcmcia i/o card interface. the i/o card and ic memory card interfaces can be switched using an address to be accessed. if area 5 of the physical space is specified as the pcmcia, the i/o card interface can automatically be accessed by accessing the physical addresses fro m h?16000000 to h'17fffff f. if area 6 of the physical space is specified as the pcmcia, the i/o card interface can automatically be accessed by accessing the physical addresses from h 1a000000 to h 1bffffff. note that areas to be accessed as the pcmcia i/ o card must be non-cached if they are logical space (space p2 or p3) areas, or a no n-cached area specified by the mmu.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 450 of 950 rej09b0079-0200 if the pcmcia card is accessed as an i/o card in little endian m ode, dynamic bus sizing for the i/o bus can be achieved using the iois16 signal. if the iois16 signal is brought high in a word- size i/o bus cycle while the bus width of area 6 is specified as 16 bits, the bus width is recognized as 8 bits and data is accessed twice in 8-bit units in the i/o bus cycle to be executed. the iois16 signal is sampled at the falling edge of ckio in the tpci0, tpci0w, and tpci1 cycles when the ted[3:0] bits are specifi ed as 1.5 cycles or more, and is reflected in the ce2 signal 1.5 cycles after the ckio sampling point. the ted[3:0] bits must be specified appropriately to satisfy the setup time from iciord and iciowr of the pc card to cen. figure 12.44 shows the dynamic bus sizing basic timing. note that the iois16 signal is not supported in big endian mode. in the big endian mode, the iois16 signal must be fixed low. tpci1w ckio a25 to a0 cexx rd/ wr iciord d15 to d0 iciowr d15 to d0 bs read write tpci2 tpci1 tpci1w tpci1w figure 12.42 basic timing fo r pcmcia i/o card interface
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 451 of 950 rej09b0079-0200 tpci1w ckio a25 to a0 cexx rd/ wr iciord d15 to d0 iciowr iois16 d15 to d0 bs read write tpci2 tpci0 tpci1 tpci1w tpci0w tpci2w tpci1w tpci1w wait figure 12.43 wait timing fo r pcmcia i/o card interface (ted[3:0] = b 0010, teh[3:0] = b 0001, software wait = 1, hardware wait = 1) tpci1w ckio a25 to a0 ce1x rd/ wr iciord d15 to d0 iciowr iois16 d15 to d0 bs read write tpci2 ce2x tpci0 tpci1 tpci1w tpci0w tpci2w tpci1w tpci1w wait tpci1w tpci2 tpci0 tpci1 tpci1w tpci0w tpci2w tpci1w tpci1w figure 12.44 timing for dynamic bus sizing of pcmc ia i/o card interface (ted[3:0] = b 0010, teh[3:0] = b 0001, software waits = 3)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 452 of 950 rej09b0079-0200 12.5.9 burst rom (clock synchronous) interface the burst rom (clock synchronou s) interface is supported to access a rom with a synchronous burst function at high speed. the burst rom inte rface accesses the burst rom in the same way as a normal space. this interface is valid only for area 0. in the first access cycle, wait cycl es are inserted. in th is case, the number of wait cycles to be inserted is specified by the w[3:0] bits of the cs0wcr. in the second and subsequent cycles, the number of wait cycles to be inserted is specified by the bw[1:0 ] bits of the cs0wcr. while the burst rom is accesse d (clock synchronous), the bs signal is asserted only for the first access cycle and an external wait input is also valid for the first access cycle. if the bus width is 16 bits, the burst length must be specified as 8. if the bus width is 32 bits, the burst length must be specified as 4. the burst rom interface does not support the 8-bit bus width for the burst rom. the burst rom interface perfor ms burst operations for all read accesses. for example, in a longword acces s over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is read six times. these invalid data read cycles increase the memory access time and degrade the program execution speed and dma transfer sp eed. to prevent this problem, a 16-byte read by cache fill or 16-byte read by the dma should be used. the burst rom interface performs write accesses in the same way as normal space access. note: the burst rom (clock synchronous) must be accessed as cacheable space. twb ckio address note: the waveform for dackn is when active low is specified. csn rd/ wr rd d15 to d0 dackn * bs t1 t2 tw t2b tw t2b twb twb t2b t2b twb twb t2b t2b twb t2b twb wait figure 12.45 burst rom (clock synchronous) access timing (burst length = 8, wait cycles inserted in first access = 2, wait cycles inserted in seco nd and subsequent accesses = 1)
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 453 of 950 rej09b0079-0200 12.5.10 wait between access cycles as the operating frequency of lsis becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. as a result of these collisions, the reliability of the device is low and malfunctions may occur. this lsi has a function that avoids data collisions by inserting wait cycles between continuous access cycles. the number of wait cycles betw een access cycles can be set by bits iww[2:0], iwrwd[2:0], iwrws[2:0], iwrrd[2:0], and iwrrs[2:0] in csnbcr, and bits dmaiw[2:0] and dmaiwa in cmncr. the co nditions for setting the wait cycles between access cycles (idle cycles) are shown below. 1. continuous accesses are write-read or write-write 2. continuous accesses are re ad-write for different spaces 3. continuous accesses are re ad-write for the same space 4. continuous accesses are re ad-read for different spaces 5. continuous accesses are read-read for the same space 6. data output from an external device caused by dma single transfer is followed by data output from another device that includes this lsi (dmaiwa = 0) 7. data output from an external device caused by dma single transfer is followed by any type of access (dmaiwa = 1) 12.5.11 bus arbitration to prevent device malfunction while the bus master ship is transferred between master and slave, the lsi negates all of the bus control signals before bus release. when the bus mastership is received, all of the bus control signa ls are first negated and then driv en appropriately. in this case, output buffer contention can be prevented because the master and slave drive the same signals with the same values. in addition, to prevent noise while the bus control signal is in the high impedance state, pull-up resistors must be connected to these control signals. bus mastership is transf erred at the boundary of bus cycles. namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed. the release of bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. even when from outside the lsi it looks like a bus cycle is not being performed, a bus cycle may be performing internally, started by inserting wait cycles between acces s cycles. therefore, it cannot be immediately determined whether or not bus mastership has been released by looking at the csn
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 454 of 950 rej09b0079-0200 signal or other bus control signals. the states th at do not allow bus mast ership release are shown below. 1. 16-byte transfer because of a cache miss 2. during copyback operation for the cache 3. between the read and write cycles of a tas instruction 4. multiple bus cycles generated when the data bus width is smaller than the access size (for example, between bus cycles when longword acces s is made to a memory with a data bus width of 8 bits) 5. 16-byte transfer by the dmac or e-dmac 6. setting the block bit in cmncr to 1 bits dprty[1:0] in cmncr can select whether or not the bus request is received during dmac burst transfer. this lsi has the bus mastership until a bus request is received from another device. upon acknowledging the assertion (low level) of the external bus request signal breq , the lsi releases the bus at the completion of the current bus cycle and asserts the back signal. after the lsi acknowledges the negation (high level) of the breq signal that indicates the slave has released the bus, it negates the back signal and resumes the bus usage. the sdram issues a all bank pr echarge command (pall) when active banks exist and releases the bus after completion of a pall command. the bus sequence is as follows. th e address bus and data bus are pl aced in a high-impedance state synchronized with the rising edge of ckio. th e bus mastership enable signal is asserted 0.5 cycles after the above timing, sync hronized with the falling edge of ckio. the bus control signals ( bs , csn , ras , cas , dqmxx, wen ( ben ), rd , and rd/ wr ) are placed in the high-impedance state at subsequent rising edges of ckio. bus re quest signals are sampled at the falling edge of ckio. the sequence for reclaiming the bu s mastership from a slave is described below. 1.5 cycles after the negation of breq is detected at the falling edge of ck io, the bus control signals are driven high. the back is negated at the next falling edge of the clock. the fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the ckio where address and data signals are driven. figure 12.46 shows the bus arbitration timing. in an original slave device de signed by the user, multiple bus accesses are generated continuously to reduce the overhead caused by bus arbitration. in this case, to execute sdram refresh correctly, the slave device must be designed to release the bus mastership within the refresh interval time. to achieve this, the lsi instructs the refout pin to request the bus mastership
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 455 of 950 rej09b0079-0200 while the sdram waits for the refresh. the lsi asserts the refout pin until the bus mastership is received. if the slave releases the bus, the lsi acquires the bus mast ership to execute the sdram refresh. the bus release by the breq and back signal handshaking requires some overhead. if the slave has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. reducing the cycles required for master to slave bus mastership transitions streamlines the system design.
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 456 of 950 rej09b0079-0200 cmncr cs0wcr cs6bwcr cs0bcr cs6bbcr sdcr rtcsr rtcnt rtcor comparator bus mastership controller wait controller area controller internal master module internal slave module internal bus memory controller refresh controller interrupt controller [legend] module bus bsc cs0 , cs2 , cs3 , cs4 , cs5a , cs5b , cs6a , cs6b wait md5 to md3 iois16 a25 to a0, d31 to d0 refout back breq bs , rd/ wr , rd , we3(be3) to we0(be0) , ras , cas , cke, dqmxx, ce2a , ce2b cmncr: csnwcr: csnbcr: sdcr: rtcsr: rtcnt: rtcor: common control register csn space wait control register (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) csn space bus control register (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) sdram control register refresh timer control/status register refresh timer counter refresh time constant register . . . . . . . . . . . . . . . figure 12.46 bus arbitration timing
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 457 of 950 rej09b0079-0200 12.5.12 others reset: the bus state controller (bsc) can be initialized completely only at power-on reset. at power-on reset, all signals are negated and output buffers are turned off regardless of the bus cycle state. all control registers are initialized. in standb y, sleep, and manual reset, control registers of the bus state controller are not initialized. at manual reset, the current bus cycle being executed is completed and then the access wait state is entered. if a 16-byte transfer is performed by a cache or if another lsi on-chip bus master module is executed when a manual reset occurs, the current access is cancelled in longword un its because the access request is ca ncelled by the bus master at manual reset. if a manual reset is requested duri ng cache fill operations, the contents of the cache cannot be guaranteed. since the rtcnt continues counting up during manual reset signal assertion, a refresh request occurs to initiate th e refresh cycle. note, however, a bus arbitration request by the breq signal can?t be accepted during manual reset signal assertion. some flash memories ma y specify a minimum time from rese t release to the first access. to ensure this minimum time, the bus state controll er supports a 5-bit reset wait counter (rwtcnt). at power-on reset, the rwtcnt is cleared to 0. after a power-on reset, rwtcnt is counted up synchronously together w ith ckio and an external access will not be generated until rwtcnt is counted up to h 007f. at a manual reset, rwtcnt is no t cleared. rwtcnt cannot be read from or written to. access from the site of th e lsi internal bus master: there are three types of lsi internal buses: a cache bus, internal bus, and peripheral bus. the cpu and cache memory are connected to the cache bus. internal bu s masters other than the cpu and bu s state controller are connected to the internal bus. low-speed peri pheral modules are connected to the peripheral bus. internal memories other than the cache memory and debugging modules such as a ubc and aud are connected bidirectionally to the cache bus and internal bus. access from the cache bus to the internal bus is enabled but access from the internal bus to the cache bus is disabled. this gives rise to the following problems. internal bus masters such as dmac or e-dmac other than the cpu can access on-chip memory other than the cache memory but cannot access the cache memory. if an on-chip bus master other than the cpu writes data to an external memory ot her than the cache, the contents of the external memory may differ from that of the cache memo ry. to prevent this problem, if the external memory whose contents is cached is written by an on-chip bus master other than the cpu, the corresponding cache memory shoul d be purged by software. if the cpu initiates read access for the cache, the cac he is searched. if th e cache stores data, the cpu latches the data and completes the read access. if the cache does not store data, the cpu performs four contiguous longword read cycles to perform cach e fill operations via the internal bus. if a cache miss occurs in byte or word operan d access or at a branch to an odd word boundary
section 12 bus state controller (bsc) rev. 2.00 dec. 07, 2005 page 458 of 950 rej09b0079-0200 (4n + 2), the cpu performs four contiguous longword accesses to perform a cache fill operation on the external interface. for a non-cacheable area, the cpu pe rforms access according to the actual access addresses. for an instruction fetch to an even word boundary (4n), the cpu performs longword access. for an instruc tion fetch to an odd word bound ary (4n + 2), the cpu performs word access. for a read cycle of a cache-through area or an on-c hip peripheral module, the read cycle is first accepted and then read cycle is initiated. the read data is sent to the cpu via the cache bus. in a write cycle for the cache area, the write cy cle operation differs accord ing to the cache write methods. in write-back mode, the cache is first searched. if data is detected at the address corresponding to the cache, the data is then re-wr itten to the cache. in the actual me mory, data will not be re-written until data in the corresponding address is re-wri tten. if data is not detected at the address corresponding to the cache, the cache is modified. in this case, data to be modified is first saved to the internal buffer, 16-byte data including the data corresponding to the address is then read, and data in the corresponding access of the cache is finally modified. following these operations, a write-back cycle for the save d 16-byte data is executed. in write-through mode, the cache is first searched . if data is detected at the address corresponding to the cache, the data is re-written to the cache si multaneously with the actua l write via the internal bus. if data is not detected at the address corres ponding to the cache, the cache is not modified but an actual write is performed via the internal bus. since the bus state controller (b sc) incorporates a one-stage writ e buffer, the bsc can execute an access via the internal bus before the previous exte rnal bus cycle is comple ted in a write cycle. if the on-chip module is read or written after the ex ternal low-speed memory is written, the on-chip module can be accessed before the completion of th e external low-speed me mory write cycle. in read cycles, the cpu is placed in the wait st ate until read operation has been completed. to continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. the write buffer of the bsc func tions in the same way for an acces s by a bus master other than the cpu such as the dmac or e-dmac. accordingly, to perfor m dual address dma transfers, the next read cycle is initiated before the previous write cycle is completed. note, however, that if both the dma source and destinati on addresses exist in external memory space, the next write cycle will not be initiated until the previous write cycle is completed. on-chip periphera l module access: to access an on-chip modul e register, two or more peripheral module clock (p ) cycles are required. care must be taken in system design.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 459 of 950 rej09b0079-0200 section 13 direct memory access controller (dmac) the direct memory access controlle r (dmac) can be used in place of the cpu to perform high- speed transfers between external devices that have dack (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules. 13.1 features ? ? ? ? ? ? ? ? ? ? ?
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 460 of 950 rej09b0079-0200 figure 13.1 shows a block diagram of the dmac. on-chip peripheral module dma transfer request signal dma transfer acknowledge signal peripheral bus internal bus external rom on-chip memory interrupt controller dreq0, dreq1 dein dack0, dack1, tend0, tend1 external ram bus interface bus state controller external i/o (memory mapped) external i/o (with acknowledge- ment) request priority control start-up control register control iteration control sar_n dar_n dmatcr_n chcr_n dmaor dmars0-2 legend sar_n dar_n dmatcr_n chcr_n dmaor dmars0-2 dein n : dma source address register : dma destination address register : dma transfer count register : dma channel control register : dma operation register : dma extension resource selector : dma transfer end interrupt request to the cpu : 0 , 1 , 2 , 3 , 4 , 5 dmac module figure 13.1 block diagram of dmac
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 461 of 950 rej09b0079-0200 13.2 input/output pins the external pins for the dmac are described below. table 13.1 lists the configuration of the pins th at are connected to external bus. the dmac has pins for 2 channels (channels 0 and 1) for external bus use. table 13.1 pin configuration channel name abbreviation i/o function dma transfer request dreq0 i dma transfer request input from external device to channel 0 dma transfer request acknowledge dack0 o dma transfer request acknowledge output from channel 0 to external device 0 dma transfer end tend0 o dma transfer end output for channel 0 dma transfer request dreq1 i dma transfer request input from external device to channel 1 dma transfer request acknowledge dack1 o dma transfer request acknowledge output from channel 1 to external device 1 dma transfer end tend1 o dma transfer end output for channel 1
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 462 of 950 rej09b0079-0200 13.3 register descriptions the dmac has the following registers. refer to s ection 24, list of registers, for the addresses and access size of these registers. channel 0: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 463 of 950 rej09b0079-0200 channel 5: ? ? ? ? ? ? ? ?
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 464 of 950 rej09b0079-0200 13.3.3 dma transfer count register (dmatcr) dmatcr is a 32-bit readable/writable registers that specifies the dma transfer count. the number of transfers is 1 when the setting is h'00000001, 16,777,215 when h'00ffffff is set, and 16,777,216 (the maximum) when h'00000000 is set. during a dma transfer, dmatcr indicates the remaining transfer count. the upper eight bits of dmatcr will return 0 if read, and should only be written with 0. to transfer data in 16 bytes, one 16 -byte transfer (128 bits) counts one. dmatcr is undefined at reset and retains the current value in standby or module standby mode. 13.3.4 dma channel control register (chcr) chcr is a 32-bit readable/writable register that controls the dma transfer mode. chcr is initialized to h'00000000 at reset and reta ins the current value in the standby or module standby mode. bit bit name initial value r/w description 31 to 24 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 23 do 0 r/w dma overrun selects whether the dreq is det ected by overrun 0 or by overrun 1. this bit is valid only in chcr0 and chcr1.this bit is reserved and always read as 0 in chcr2 to chcr5. the write value should always be 0. 0: detects dreq by overrun 0 1: detects dreq by overrun 1
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 465 of 950 rej09b0079-0200 bit bit name initial value r/w description 22 tl 0 r/w transfer end level specifies the tend signal output is high active or low active. this bit is valid only in chcr0 and chcr1.this bit is reserved and always read as 0 in chcr2 to chcr5. the write value should always be 0. 0: low-active output of tend 1: high-active output of tend 21 to 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 am 0 r/w acknowledge mode specifies whether the dack is output in data read cycle or in data write cycle in dual address mode. in single address mode, the dack is always output regardless of the specification by this bit. this bit is valid only in chcr0 and chcr1.this bit is reserved and always read as 0 in chcr2 to chcr5. the write value should always be 0. 0: dack output in read cycle (dual address mode) 1: dack output in write cycle (dual address mode) 16 al 0 r/w acknowledge level specifies the dack signal output is high active or low active. this bit is valid only in chcr0 and chcr1.this bit is reserved and always read as 0 in chcr2 to chcr5. the write value should always be 0. 0: low-active output of dack 1: high-active output of dack
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 466 of 950 rej09b0079-0200 bit bit name initial value r/w description 15 14 dm1 dm0 0 0 r/w r/w destination address mode specify whether the dma destination address is incremented, decremented, or left fixed. (in single address mode, the dm1 and dm0 bits are ignored when data is transferred to an external device with the dack.) 00: fixed destination address (setting prohibited in 16-byte transfer) 01: destination address is incremented (+1 in byte transfer, +2 in word transfer, +4 in longword transfer, +16 in 16- byte transfer) 10: destination address is decremented (?1 in byte transfer, ?2 in word transfer, ?4 in longword transfer; setting prohibited in 16-byte transfer) 11: reserved (setting prohibited) 13 12 sm1 sm0 0 0 r/w r/w source address mode specify whether the dma sour ce address is incremented, decremented, or left fixed. (in single address mode, the sm1 and sm0 bits are ignored when data is transferred from an external device with the dack.) 00: fixed source address (setting prohibited in 16-byte transfer) 01: source address is incremented (+1 in byte transfer, +2 in word transfer, +4 in longword transfer, +16 in 16-byte transfer) 10: source address is decremented (?1 in byte transfer, ?2 in word transfer, ?4 in longword transfer; setting prohibited in 16-byte transfer) 11: reserved (setting prohibited)
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 467 of 950 rej09b0079-0200 bit bit name initial value r/w description 11 10 9 8 rs3 rs2 rs1 rs0 0 0 0 0 r/w r/w r/w r/w resource select specify which transfer requests will be sent to the dmac. the change of transfer request source should be done in the state that the dma enable bit (de) is cleared to 0. 0000: external request, dual address mode 0010: external request, single address mode external address space external device with dack 0011: external request, single address mode external device with dack external address space 0100: auto request 1000: dma extension resource selector other than above: reserved (setting prohibited) note: an external request specification is valid only in chcr0 and chcr1. none of the external request specification can be selected in chcr2 to chcr5. 7 6 dl ds 0 0 r/w r/w dreq level and dreq edge select specify the sampling method of the dreq pin input and the sampling level. these bits are valid only in chcr0 and chcr1. these bits are reserved and always read as 0 in chcr2 to chcr5. the write value should always be 0. in channels 0 and 1, also, if the transfer request source is specified as an on-chip peripheral module or if an auto- request is specified, the specific ation by this bit is invalid. 00: dreq detected in low level 01: dreq detected at falling edge 10: dreq detected in high level 11: dreq detected at rising edge 5 tb 0 r/w transfer bus mode specifies the bus mode when the dma transfers data. 0: cycle steal mode 1: burst mode
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 468 of 950 rej09b0079-0200 bit bit name initial value r/w description 4 3 ts1 ts0 0 0 r/w r/w transfer size specify the size of data to be transferred. select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: byte size 01: word (two bytes) size 10: longword (four bytes) size 11: 16-byte (four longwords) size 2 ie 0 r/w interrupt enable specifies whether or not an in terrupt request is generated to the cpu at the end of the dma transfer. setting this bit to 1 generates an interrupt request (dei) to the cpu when the te bit is set to 1. 0: interrupt request is disabled 1: interrupt request is enabled 1 te 0 r/(w) * transfer end flag the te bit is set to 1 when data transfer ends when dmatcr becomes to 0. the te bit is not set to 1 in the following cases. ? dma transfer ends due to an nmi interrupt or dma address error before dmatcr becomes 0. ? dma transfer is ended by clearing the de bit and dme bit in the dma operation register (dmaor). even if the de bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: during the dma transfer or dma transfer has been interrupted 1: dma transfer ends by the specified count (dmatcr = 0) [clearing condition] writing 0 after reading 1 from this bit
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 469 of 950 rej09b0079-0200 bit bit name initial value r/w descriptions 0 de 0 r/w dma enable enables or disables the dma transfer. in auto-request mode, dma transfer starts by setting the de bit and dme bit in dmaor to 1. in this time, all of the bits te, nmif in dmaor, and ae in dmaor must be 0. in an external request or peripheral module request, dma transfer starts if dma transfer request is generated by the devices or peripheral modules after setting the bits de and dme to 1. in this case, however, all of the bits te, nmif, and ae must be 0 as in the case of auto-request mode. clearing the de bit to 0 can terminate the dma transfer. 0: dma transfer disabled 1: dma transfer enabled note: * only 0 can be written to clear the flag. 13.3.5 dma operation register (dmaor) dmaor is a 16-bit readable/writable register that specifies the priority level of channels at the dma transfer. this register indi cates the dma transfer status. dmaor is initialized to h bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 pr1 pr0 0 0 r/w r/w priority mode select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: fixed mode 1: ch0 > ch1 > ch2 > ch3 > ch4 > ch5 01: fixed mode 2: ch0 > ch2 > ch3 > ch1 > ch4 > ch5 10: reserved (setting prohibited) 11: all channel round-robin mode
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 470 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 ae 0 r/(w) * address error flag indicates that an address error occurred by the dmac. when this bit is set, dma transfer is disabled even if the de bit in chcr and the dme bit in dmaor are set to 1. this bit can only be cleared by writing 0 after reading 1. 0: no dmac address error 1: dmac address error [clear conditions] writing 0 after reading 1 from this bit 1 nmif 0 r/(w) * nmi flag indicates that an nmi interrupt occurred. when this bit is set, dma transfer is disabled even if the de bit in chcr and the dme bit in dmaor are set to 1. this bit can only be cleared by writing 0 after reading 1. when the nmi is input, the dma transfer in progress can be done in one transfer unit. even if the dmac is not in operational, this bit is set to 1 when the nmi interrupt was input. 0: no nmi interrupt 1: nmi interrupt occurs [clearing conditions] writing 0 after reading 1 from this bit 0 dme 0 r/w dma master enable enables or disables dma transfers on all channels. if the dme bit and the de bit in chcr are set to 1, dma transfer is enabled. note that transfer is enabled if the te bit in chcr and the nmif and ae bits in dmaor are all 0. if this bit is cleared, dma transfers in all the channels can be terminated. 0: disables dma transfers on all channels 1: enables dma transfers on all channels note: * only 0 can be written to clear the flag.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 471 of 950 rej09b0079-0200 13.3.6 dma extension resource selector 0 to 2 (dmars0 to dmars2) dmars is a 16-bit readable/writable register th at specifies the dma tr ansfer sources from peripheral modules in each channel. dmars0 speci fies for channels 0 an d 1, dmars1 specifies for channels 2 and 3, and dmars2 specifies for channels 4 and 5. this register can set the transfer requests of the scif0, scif1, siof0, and siof1. when mid and rid other than the values listed in table 13.2 are set, the operation of this lsi is not guaranteed. the transfer request from dmars is valid only when bits rs3 to rs0 has been set to b'1000 in chcr0 to chcr5. otherwise, even if dmars has been set, a transfer request source is not accepted. dmars is initialized to h'0000 at reset and retains the current value in standby or module standby mode. ? bit bit name initial value r/w description 15 14 13 12 11 10 c1mid5 c1mid4 c1mid3 c1mid2 c1mid1 c1mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id for dma channel 1 (mid) see table 13.2. 9 8 c1rid1 c1rid0 0 0 r/w r/w transfer request register id for dma channel 1 (rid) see table 13.2. 7 6 5 4 3 2 c0mid5 c0mid4 c0mid3 c0mid2 c0mid1 c0mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id for dma channel 0 (mid) see table 13.2. 1 0 c0rid1 c0rid0 0 0 r/w r/w transfer request register id for dma channel 0 (rid) see table 13.2.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 472 of 950 rej09b0079-0200 ? bit bit name initial value r/w description 15 14 13 12 11 10 c3mid5 c3mid4 c3mid3 c3mid2 c3mid1 c3mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id for dma channel 3 (mid) see table 13.2. 9 8 c3rid1 c3rid0 0 0 r/w r/w transfer request module id for dma channel 3 (rid) see table 13.2. 7 6 5 4 3 2 c2mid5 c2mid4 c2mid3 c2mid2 c2mid1 c2mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id for dma channel 2 (mid) see table 13.2. 1 0 c2rid1 c2rid0 0 0 r/w r/w transfer request module id for dma channel 2 (rid) see table 13.2.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 473 of 950 rej09b0079-0200 ? bit bit name initial value r/w description 15 14 13 12 11 10 c5mid5 c5mid4 c5mid3 c5mid2 c5mid1 c5mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id for dma channel 5 (mid) see table 13.2. 9 8 c5rid1 c5rid0 0 0 r/w r/w transfer request module id for dma channel 5 (rid) see table 13.2. 7 6 5 4 3 2 c4mid5 c4mid4 c4mid3 c4mid2 c4mid1 c4mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id for dma channel 4 (mid) see table 13.2. 1 0 c4rid1 c4rid0 0 0 r/w r/w transfer request module id for dma channel 4 (rid) see table 13.2.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 474 of 950 rej09b0079-0200 transfer requests from the vari ous modules are specified by the mid and rid as shown in table 13.2. table 13.2 dmars setting peripheral module setting value for one channel (mid + rid) mid rid function h'21 b'01 transmit scif0 h'22 b'001000 b'10 receive h'29 b'01 transmit scif1 h'2a b'001010 b'10 receive h'51 b'01 transmit siof0 h'52 b'010100 b'10 receive h'55 b'01 transmit siof1 h'56 b'010101 b'10 receive 13.4 operation when there is a dma transfer request, the dmac starts the transfer according to the predetermined channel priority order; when the tr ansfer end conditions are satisfied, it ends the transfer. transfer s can be requested in three modes: auto request, external request, and on-chip peripheral module request. in the bus mode, the burst mode or the cycle steal mode can be selected. 13.4.1 dma transfer flow after the dma source address registers (sar), dma destination address registers (dar), dma transfer count registers (dmatcr), dma channel control registers (chcr), dma operation register (dmaor), and dma extension resource se lector (dmars) are set, the dmac transfers data according to the following procedure: 1. checks to see if transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0) 2. when a transfer request comes and transfer is enabled, the dmac transfers 1 transfer unit of data (depending on the ts0 and ts1 settings). for an auto request, the transfer begins automatically when the de bit and dme bit are set to 1. the dmatcr value will be decremented for each transfer. th e actual transfer flows vary by address mode and bus mode.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 475 of 950 rej09b0079-0200 3. when the specified number of transfer ha ve been completed (when dmatcr reaches 0), the transfer ends normally. if the ie bit of the chcr is set to 1 at this time, a dei interrupt is sent to the cpu. 4. when an address error or an nmi interrupt is generated, the transfer is aborted. transfers are also aborted when the de bit of the chcr or the dme bit of the dmaor are changed to 0.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 476 of 950 rej09b0079-0200 figure 13.2 is a flowch art of this procedure. normal end nmif = 1 or ae = 1 or de = 0 or dme = 0? bus mode, transfer request mode, dreq detection selection system initial settings (sar, dar, dmatcr, chcr, dmaor, dmars) transfer (1 transfer unit); dmatcr ? 1 dmatcr, sar and dar updated dei interrupt request (when ie = 1) te = 1 no yes no yes no yes yes no yes no * 3 * 2 start transfer aborted dmatcr = 0? transfer request occurs? * 1 de, dme = 1 and nmif, ae, te = 0? nmif = 1 or ae = 1 or de = 0 or dme = 0? transfer end notes: * 1 in auto-request mode, transfer begins when nmif, ae and te are all 0 and the de and dme bits are set to 1. * 2 dreq = level detection in burst mode (external request) or cycle-steal mode. * 3 dreq = edge detection in burst mode (external request), or auto-request mode in burst mode. figure 13.2 dma transfer flowchart
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 477 of 950 rej09b0079-0200 13.4.2 dma transfer requests dma transfer requests are basically generated in e ither the data transfer so urce or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. the request mode is selected in the rs3 to rs0 bits in the dma channel control registers 0 to 5 (chcr_0 to chcr_5), and th e dma extension resource selectors 0 to 2 (dmars0 to dmars2). auto-request mode: when there is no transfer request sign al from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the dmac to automatically generate a transfer request signal internally. when the de bits of chcr_0 to chcr_5 and the dme bit of the dmaor are set to 1, the transfer begins so long as the te bits of chcr_0 to chcr_5 ae bit of dmaor, and the nmif bit of dmaor are all 0. external request mode: in this mode a transfer is perfor med at the request signals (dreq0 or dreq1) of an external device. choose one of the modes shown in table 13.3 according to the application system. when this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0), a transfer is performed upon a request at the dreq input. table 13.3 selecting external request modes with rs bits rs3 rs2 rs1 rs0 address mode source destination 0 0 0 0 dual address mode any any 0 external memory, memory-mapped external device external device with dack 0 0 1 1 single address mode external device with dack external memory, memory-mapped external device whether the dreq is detected by either the edge or level of the signal input is selected with the dreq level (dl) bit and dreq select (ds) bit in chcr_0 and chcr_1 as shown in table 13.4. the source of the transfer reques t does not have to be the data transfer source or destination.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 478 of 950 rej09b0079-0200 table 13.4 selecting external request detection with dl, ds bits chcr dl ds detection of external request 0 low level detection 0 1 falling edge detection 0 high level detection 1 1 rising edge detection when dreq is accepted, the dreq pin becomes request accept disabled state (non-sensitive period). after issuing acknowledge signal da ck for the accepted dreq, the dreq pin again becomes request accept enabled state. when dreq is used by level detection, there ar e following two cases by th e timing to detect the next dreq after outputting dack. overrun 0: transfer is aborted after the same number of transfer has been performed as requests. overrun 1: transfer is aborted after transfers have been performed for (the number of requests plus 1) times. the do bit in chcr selects this overrun 0 or overrun 1. table 13.5 selecting external request detection with do bit chcr do external request 0 overrun 0 1 overrun 1 on-chip peripheral module request mode: in this mode, the transfer is performed in response to the transfer request signal of an on-chip peripheral module. the dma transfer request signals comprise the tr ansmit data empty transfer request and receive data full transfer request from the scif0, scif1, siof0, and siof1 set by dmars0 to dmars2. when this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0), a transfer is performed upon the inpu t of a transfer request signal. when a transfer request is set to txi of the scif0, the transfer destination must be the scif0's transmit data
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 479 of 950 rej09b0079-0200 register. likewise, when a transfer request is set to rxi of the scif0, the transfer source must be the scif0's receive data register. these conditions also apply to the scif1, siof0, and siof1. depending on the on-chip periphera l module, the number of receive fifo trigge rs can be set as a transfer request. if the receive fi fo trigger condition is not satisfied , data may be remained in the receive fifo. therefore, data needs to be read upon completion of the dma transfer. table 13.6 selecting on-chip peripheral modu le request modes with rs3 to rs0 bits chcr dmars rs[3:0] mid rid dma transfer request source dma transfer request signal source destination bus mode 01 scif0 transmitter txi (transmit fifo data empty interrupt) any scftdr_0 cycle steal 001000 10 scif0 receiver rxi (receive fifo data full interrupt) scfrdr_0 any cycle steal 01 scif1 transmitter txi (transmit fifo data empty interrupt) any scftdr_1 cycle steal 001010 10 scif1 receiver rxi (receive fifo data full interrupt) scfrdr_1 any cycle steal 01 siof0 transmitter txi (transmit fifo data empty interrupt) any sitdr_0 cycle steal 010100 10 siof0 receiver rxi (receive fifo data full interrupt) siof0/ sirdr_0 any cycle steal 01 siof1 transmitter txi (transmit fifo data empty interrupt) any sitdr_1 cycle steal 1000 010101 10 siof1 receiver rxi (receive fifo data full interrupt) siof1/ sirdr_1 any cycle steal 13.4.3 channel priority when the dmac receives simultaneous transfer re quests on two or more channels, it selects a channel according to a predetermined priority order. the two modes (fixed mode and round-robin mode) can be selected using bits pr0 and pr1 in dmaor. fixed mode: in this mode, the priority levels among the channels remain fixed. there are two kinds of fixed modes as follows: fixed mode 1: ch0 > ch1 > ch2 > ch3 > ch4 > ch5 fixed mode 2: ch0 > ch2 > ch3 > ch1 > ch4 > ch5 these are selected by the pr1 and the pr0 bits in dmaor.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 480 of 950 rej09b0079-0200 round-robin mode: each time one word, byte, longword or 16-byte unit is transferred on one channel, the priority order is rotated. the channel on which the transfer was just finished rotates to the bottom of the priority order. the round-robin mode operation is shown in figure 13.3. the priority of the round-robin mode is ch0 > ch1 > ch2 > ch3 > ch4 > ch5 immediately after a reset. when round-robin mode is specified, the bus mode setting of multiple channels does not allow a mixture of cycle st eal mode and burst mode. ch1 > ch2 > ch3 > ch4 > ch5 > ch0 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch2 > ch3 > ch4 > ch5 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch3 > ch4 > ch5 > ch0 > ch1 > ch2 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 (1) when channel 0 transfers initial priority order initial priority order initial priority order initial priority order priority order afrer transfer priority order does not change channel 2 becomes bottom priority. the priority of channels 0 and 1, which were higher than channel 2, are also shifted. if immediately after there is a request to transfer channel 5 only, channel 5 becomes bottom priority and the priority of channels 3 and 4, which were higher than channel 5, are also shifted. channel 1 becomes bottom priority. the priority of channel 0, which was higher than channel 1, is also shifted. channel 0 becomes bottom priority priority order afrer transfer priority order afrer transfer priority order afrer transfer post-transfer priority order when there is an immediate transfer request to channel 5 only (2) when channel 1 transfers (3) when channel 2 transfers (4) when channel 5 transfers figure 13.3 round-robin mode
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 481 of 950 rej09b0079-0200 figure 13.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. the dmac operates as follows: 1. transfer requests are generated simultaneously to channels 0 and 3. 2. channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. a channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. when the channel 0 transfer ends, channel 0 becomes lowest priority. 5. at this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. when the channel 1 transfer ends, channel 1 becomes lowest priority. 7. the channel 3 transfer begins. 8. when the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority. transfer request waiting channel(s) dmac operation channel priority (1) channels 0 and 3 (3) channel 1 0 > 1 > 2 > 3 > 4 > 5 (2) channel 0 transfer start (4) channel 0 transfer ends (5) channel 1 transfer starts (6) channel 1 transfer ends (7) channel 3 transfer starts (8) channel 3 transfer ends 1 > 2 > 3 > 4 > 5 > 0 2 > 3 > 4 > 5 > 0 > 1 4 > 5 > 0 > 1 > 2 > 3 priority order changes priority order changes priority order changes none 3 3 1,3 figure 13.4 changes in channe l priority in round-robin mode
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 482 of 950 rej09b0079-0200 13.4.4 dma transfer types dma transfer has two types; single address mode transfer and dual address mode transfer, they depend on the number of bus cycl es of access to source and destin ation. a data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. the dmac supports the transfers shown in table 13.7. table 13.7 supported dma transfers destination source external device with dack external memory memory- mapped external device on-chip peripheral module x/y memory external device with dack not available single single not available not available external memory single dual dual dual dual memory-mapped external device single dual dual dual dual on-chip periphera l module not available dual dual dual dual x/y memory not available dual dual dual dual notes: 1. dual: dual address mode 2. single: single address mode 3. 16-byte transfer is not available for on-chip peripheral modules. address modes: 1. dual address mode in the dual address mode, both the transfer source and destinat ion are accessed (selected) by an address. the source and des tination can be located ex ternally or internally. dma transfer requires two bus cycl es because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. at this time, transfer data is temporarily stored in the dmac. in th e transfer between extern al memories as shown in figure 13.5, data is read to the dmac from one external memo ry in a data read cycle, and then that data is written to the other external memory in a write cycle.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 483 of 950 rej09b0079-0200 data buffer address bus data bus address bus data bus memory transfer source module transfer destination module memory transfer source module transfer destination module sar dar data buffer sar dar the sar value is an address, data is read from the transfer source module, and the data is temporarily stored in the dmac. first bus cycle second bus cycle the dar value is an address and the value stored in the data buffer in the dmac is written to the transfer destination module. dmac dmac figure 13.5 data flow in dual address mode auto request, external request, and on-chip pe ripheral module request are available for the transfer request. dack can be ou tput in read cycle or write cy cle in dual address mode. the am bit of the channel control register (chcr) can specify whether the dack is output in read cycle or write cycle. figure 13.6 shows an example of dma transfer timing in dual address mode.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 484 of 950 rej09b0079-0200 ckio a25 to a0 note: in transfer between external memories, with dack output in the read cycle, dack output timing is the same as that of csn . d31 to d0 wen rd dackn (active-low) csn transfer source address transfer destination address data read cycle data write cycle (1st cycle) (2nd cycle) figure 13.6 example of dma transfer timing in dual address mode (source: ordinary memory, destination: ordinary memory) 2. single address mode in single address mode, either the transfer sour ce or transfer destination external device is accessed (selected) by means of the dack signal, and the other device is accessed by address. in this mode, the dmac performs one dma tran sfer in one bus cycle, accessing one of the external devices by outputting the dack transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. for example, in the case of transfer between external memory and an external device with dack shown in figure 13.7, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 485 of 950 rej09b0079-0200 dmac this lsi dack dreq external address bus external data bus external memory external device with dack data flow figure 13.7 data flow in single address mode two kinds of transfer are possib le in single address mode: (1) transfer between an external device with dack and a memory-mapped external device, and (2) transfer between an external device with dack and external memo ry. in both cases, only the external request signal (dreq) is used for transfer requests. figures 13.8 shows example of dma tr ansfer timing in si ngle address mode.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 486 of 950 rej09b0079-0200 address output to external memory space select signal to external memory space select signal to external memory space data output from external device with dack dack signal (active-low) to external device with dack write strobe signal to external memory space address output to external memory space data output from external memory space dack signal (active-low) to external device with dack read strobe signal to external memory space (a) external device with dack external memory space (ordinary memory) (b) external memory space (ordinary memory) external device with dack ckio a25 to a0 d31 to d0 dackn csn we ckio a25 to a0 d31 to d0 dackn csn rd figure 13.8 example of dma transf er timing in single address mode bus modes: there are two bus modes: cycle steal and burst. select the mode in the tb bits of the channel control register (chcr). ?
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 487 of 950 rej09b0079-0200 cpu cpu cpu dmac dmac cpu dmac dmac cpu dreq bus cycle bus mastership returned to cpu once read write write read figure 13.9 dma transfer ex ample in cycle-steal mode (dual address, dreq low level detection) ? cpu cpu cpu dmac dmac dmac dmac cpu dreq bus cycle read read write write figure 13.10 dma transfer example in burst mode (dual address, dreq low level detection) relationship between request modes and bus modes by dma transfer category: table 13.8 shows the relationship between request modes and bus modes by dma transfer category.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 488 of 950 rej09b0079-0200 table 13.8 relationship of request mode s and bus modes by dma transfer category address mode transfer category request mode bus mode transfer size (bits) usable channels external device with dack and external memory external b/c 8/16/32/128 0, 1 external device with dack and memory- mapped external device external b/c 8/16/32/128 0, 1 external memory and external memory external, auto b/c 8/16/32/128 0 to 5 * 2 dual external memory and memory-mapped external device external, auto b/c 8/16/32/128 0 to 5 * 2 memory-mapped external device and memory-mapped external device external, auto b/c 8/16/32/128 0 to 5 * 2 external memory and on-chip peripheral module all * 1 c 8/16/32 * 3 0 to 5 * 2 memory-mapped external device and on-chip peripheral module all * 1 c 8/16/32 * 3 0 to 5 * 2 on-chip peripheral module and on-chip peripheral module all * 1 c 8/16/32 * 3 0 to 5 * 2 x/y memory and x/y memory external, auto b/c 8/16/32/128 0 to 5 * 2 x/y memory and memory-mapped external device external, auto b/c 8/16/32/128 0 to 5 * 2 x/y memory and on-chip peripheral module all * 1 c 8/16/32 * 3 0 to 5 * 2 x/y memory and external memory external, auto b/c 8/16/32/128 0 to 5 * 2 external device with dack and external memory external b/c 8/16/32 0, 1 single external device with dack and memory- mapped external device external b/c 8/16/32 0, 1 [legend] b: burst, c: cycle steal notes: 1. external requests, auto requests, and on-chip peripheral module requests are all available. however, the request-source register must be designated as the transfer source or the transfer destination. 2. if the transfer request is an external request, channels 0 and 1 are only available. 3. access size permitted for each module must be used when accessing the on-chip peripheral module.
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 489 of 950 rej09b0079-0200 bus mode and channel priority: even if channel 1 is performing burst-mode transfer in priority fixed mode (ch0 > ch1), channel 0 starts transfer immediately when a request is made for transfer on channel 0 with higher priority. if channel 0 is also in burst mode at this time, channel 1 resumes transfer after transfer on channel 0 with higher priority is completed. if channel 0 is in cycle-steal mode, channel 0 with higher priority transfers one transfer unit then allows channel 1 to perform transfers without releasing bus mastership. next, transfers are performed alternately by channel 0, channel 1, channel 0, channel 1, and so on. this means that a bus state is set for the cpu cycle after completion of the cycle-steal mode transfer is replaced with the burst-mode transfer. (this op eration is hereinafter referred to as burst-mode priority execution.) figure 13.1 1 shows an example. if multiple channels are conflicting in burst mode, th e channel with the highest priority is selected for execution. if multiple channels perform dma transfers, bus mast ership is not released to the bus master until all conflicting burst tran sfers are completed. cpu dma ch1 dma ch1 dma ch0 dma ch1 dma ch0 dma ch1 dma ch1 cpu ch0 ch1 ch0 cycle-steal mode in dmac ch0 and ch1 dmac ch1 burst mode cpu cpu priority: ch0 > ch1 ch0: cycle-steal mode ch1: burst mode dmac ch1 burst mode figure 13.11 bus state when mu ltiple channels are operating in round-robin mode, the priority changes according to the specification shown in figure 13.11. however, no mixture of channels in cycle-steal mode and channels in burst mode is allowed. 13.4.5 number of bus cycle states and dreq pin sampling timing number of bus cycle states: when the dmac is the bus master, the number of bus cycle states is controlled by the bus state controller (bsc) in the same way as when the cpu is the bus master. for details, see section 12, bus state controller (bsc).
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 490 of 950 rej09b0079-0200 dreq pin sampling timing: ckio 1st acceptance 2nd acceptance acceptance start bus cycle dreq (rising) dack (active-high) cpu cpu cpu dmac non sensitive period figure 13.12 example of dreq input det ection in cycle steal mode edge detection ckio bus cycle bus cycle dreq (overrun 0 at high level) dack (active-high) dreq (overrun 1 at high level) dack (active-high) cpu cpu cpu dmac ckio cpu cpu cpu dmac 1st acceptance 2nd acceptance 1st acceptance 2nd acceptance acceptance start acceptance start non sensitive period non sensitive period figure 13.13 example of dreq input det ection in cycle steal mode level detection
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 491 of 950 rej09b0079-0200 ckio dreq (rising edge) dack (high active) cpu cpu dmac dmac bus cycle non sensitive period burst acceptance figure 13.14 example of dreq input de tection in burst mode edge detection ckio cpu cpu dmac ckio cpu cpu dmac dmac 1st acceptance 1st acceptance acceptance start acceptance start acceptance start bus cycle dreq (overrun 0 at high level) dack (active-high) bus cycle dreq (overrun 1 at high level) dack (active-high) non sensitive period non sensitive period 2nd acceptance 2nd acceptance 3rd acceptance figure 13.15 example of dreq input detection in burst mode level detection ckio dack (high active) dreq tend (high active) bus cycle end of dma transfer dmac cpu cpu cpu dmac figure 13.16 example of dma transfer e nd timing (cycle steal level detection)
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 492 of 950 rej09b0079-0200 ckio address rd data wen dackn tendn wait cs t1 t2 taw t1 t2 (active low) (active low) note: tend is asserted for the last transfer unit of dma transfers. if a transfer unit is divided into multiple bus cycles and if cs is negated during the bus cycle, tend is also divided. figure 13.17 example of bsc ordinary memory access (no wait, idle cycle = 1, long word access to 16-bit device)
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 493 of 950 rej09b0079-0200 13.5 usage note when using the dmac, note the following: note on using tend pin: if a dma transfer is performed under one of the conditions described below and, after completion of the transfer, retransfer is performed on the same channel, the tend pin is asserted once in the first dma transfer in retransfer when the retran sfer condition satisfies (1) dack is output in a dual address mode read cycle (with the am bit in chcr cleared to 0) and the dma transfer source address (sar) is in external memo ry space or (2) in single address mode. conditions: ? ? ? ? ?
section 13 direct memory access controller (dmac) rev. 2.00 dec. 07, 2005 page 494 of 950 rej09b0079-0200
section 14 timer unit (tmu) rev. 2.00 dec. 07, 2005 page 495 of 950 rej09b0079-0200 section 14 timer unit (tmu) this lsi includes a three-channel (chann el 0 to 2) 32-bit timer unit (tmu). 14.1 features the tmu has the following features: ? ? ? ?
section 14 timer unit (tmu) rev. 2.00 dec. 07, 2005 page 496 of 950 rej09b0079-0200 prescaler tstr tcr0 tcnt0 module bus internal bus tcor0 tcr1 tcnt1 tcor1 counter controller p tuni0 bus interface ch. 0 interrupt controller interrupt controller interrupt controller counter controller counter controller tuni1 tuni2 tcr2 tcnt2 tcor2 tmu ch. 1 ch. 2 clock controller tstr: tcr: legend timer start register timer control register tcnt: tcor: 32-bit timer counter 32-bit timer constant register figure 14.1 tmu block diagram
section 14 timer unit (tmu) rev. 2.00 dec. 07, 2005 page 497 of 950 rej09b0079-0200 14.2 register descriptions the tmu has the following registers. refer the sec tion 24, list of registers, for the addresses and access size for these registers. ? ? ? ? ? ? ? ? ? ? to 2. tstr is an 8-bit readable/writable register. it is initialized to h'00 by a power-on reset or manual reset. it is initialized in standby mode when th e multiplication ratio of pll circuit 1 (pll1) is changed or when the mstp2 bit in stbcr is set to 1. bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 str2 0 r/w counter start 2 selects whether to run or halt tcnt2. 0: tcnt2 count halted 1: tcnt2 counts 1 str1 0 r/w counter start 1 selects whether to run or halt tcnt1. 0: tcnt1 count halted 1: tcnt1 counts
section 14 timer unit (tmu) rev. 2.00 dec. 07, 2005 page 498 of 950 rej09b0079-0200 bit bit name initial value r/w description 0 str0 0 r/w counter start 0 selects whether to run or halt tcnt0. 0: tcnt0 count halted 1: tcnt0 counts 14.2.2 timer control registers (tcr) the timer control registers (tcr) control the time r counters (tcnt) and interrupts. the tmu has three tcr registers, one for each channel. the tcr registers control the issuance of inte rrupts when the flag indicating timer counters (tcnt) underflow has been set to 1, and also carry out counter clock selection. the tcr registers are 16-bit readab le/writable registers. they ar e initialized to h'0000 by a power-on reset and manual reset, but are not initia lized, and retain their contents, in standby mode. bit bit name initial value r/w description 15 or 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 unf 0 r/w underflow flag status flag that indicates occurrence of a tcnt underflow. 0: tcnt has not underflowed [clearing condition] 0 is written to unf 1: tcnt has underflowed [setting condition] tcnt underflows * note: * contents do not change when 1 is written to unf. 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 14 timer unit (tmu) rev. 2.00 dec. 07, 2005 page 499 of 950 rej09b0079-0200 bit bit name initial value r/w description 5 unie 0 r/w underflow interrupt control controls enabling of inte rrupt generation when the status flag (unf) indicating tcnt underflow has been set to 1. 0: interrupt due to unf (tuni) is disabled 1: interrupt due to unf (tuni) is enabled 4, 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w timer prescaler 2 to 0 select the tcnt count clock. 000: count on p /4 001: count on p /16 010: count on p /64 011: count on p /256 100: reserved (setting prohibited) 101: reserved (setting prohibited) 110: reserved (setting prohibited) 111: reserved (setting prohibited) 14.2.3 timer constant registers (tcor) the tmu has three timer constant registers (tco r), one for each channel. the tcor registers set the value to be set in tcnt when tcnt underflows. the tcor registers are 32-bit r eadable/writable registers. they are initialized to h'ffffffff by a power-on reset or manual reset, but are not initialized, and retain their contents, in standby mode. 14.2.4 timer counters (tcnt) the tmu has three timer counters (tcnt), one for each channel. the timer counters (tcnt) counts down upon input of a clock. the input clock is selected using the tpsc2 to tpsc0 bits in the timer control registers (tcr).
section 14 timer unit (tmu) rev. 2.00 dec. 07, 2005 page 500 of 950 rej09b0079-0200 when a tcnt count-down results in an underflow (h'00000000 to str2 bits in tstr are set to 1, th e corresponding tcnt starts counting. when tcnt underflows, the underflow flag (unf) of the corresponding tcr is set. at this time, if the unie bit in tcr is 1, an interrupt request is sent to the cpu. also at this time, the value is copied from tcor to tcnt and the down-count operation is continued. count operation setting procedure: an example of the procedure for setting the count operation is shown in figure 14.2.
section 14 timer unit (tmu) rev. 2.00 dec. 07, 2005 page 501 of 950 rej09b0079-0200 select operation select counter clock set underflow interrupt generation set timer constant register initialize timer counter start counting (1) (2) (3) (4) (5) note: when an interrupt has been generated, clear the flag in the interrupt handler that caused it. if interrupts are enabled without clearing the flag, another interrupt will be generated. (1) select the counter clock with the tpsc2 to tpsc0 bits in tcr. (2) use the unie bit in tcr to set whether to generate an interrupt when tcnt underflows. (3) set a value in tcor (the cycle is the set value plus 1). (4) set the initial value in tcnt. (5) set the str bit in tstr to 1 to start operation. figure 14.2 setting count operation auto-reload count operation: figure 14.3 shows the tcnt auto-reload operation. tcnt value tcor h'00000000 str0?str2 unf tcor value set to tcnt during underflow time figure 14.3 auto-r eload count operation
section 14 timer unit (tmu) rev. 2.00 dec. 07, 2005 page 502 of 950 rej09b0079-0200 tcnt count timing: set the tpsc2 to tpsc0 bits in tcr to select whether peripheral module clock p p internal clock tcnt input clock tcnt n + 1 n n ? 1 figure 14.4 count timing when internal clock is operating
section 14 timer unit (tmu) rev. 2.00 dec. 07, 2005 page 503 of 950 rej09b0079-0200 14.4 interrupts the interrupt source of tmu is underflow interrupt (tuni). 14.4.1 status fl ag set timing the unf bit is set to 1 when the tcnt underflows. figure 14.5 shows the timing. p tcnt underflow signal unf tuni tcor value h'00000000 figure 14.5 unf set timing 14.4.2 status flag clear timing the status flag can be cleared by writing 0 from the cpu. figure 14.6 shows the timing. p peripheral address bus unf tcr address t1 t2 tcr write cycle t3 figure 14.6 status flag clear timing
section 14 timer unit (tmu) rev. 2.00 dec. 07, 2005 page 504 of 950 rej09b0079-0200 14.4.3 interrupt sou rces and priorities the tmu generates underflow interrupts for each channel. when the interrupt request flag and interrupt enable bit are both set to 1, the interrupt is requested. codes are set in the interrupt event register (intevt2) for these interrupts and interrupt processing occurs according to the codes. the relative priorities of channels can be change d using the interrupt controller (see section 4, exception handling, and section 8, interrupt c ontroller (intc)). table 14.1 lists tmu interrupt sources. table 14.1 tmu interrupt sources channel interrupt source description priority 0 tuni0 underflow interrupt 0 high 1 tuni1 underflow interrupt 1 2 tuni2 underflow interrupt 2 low 14.5 usage notes 14.5.1 writing to registers synchronization processing is not performed for timer counting during register writes. when writing to registers, always clear the appropriate start bits for the channel (str2 to str0) in tstr to halt timer counting. 14.5.2 reading registers synchronization processing is performed for timer counting during register reads. when timer counting and register read proce ssing are performed simultaneous ly, the register value before tcnt counting down (with synchronization processing) is read.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 505 of 950 rej09b0079-0200 section 15 realtime clock (rtc) this lsi has a realtime clock (rtc) with its ow n 32.768-khz crystal oscillator. a block diagram of the rtc is shown in figure 15.1. 15.1 feature the rtc has following features: ? ? ? ? ? ? ? ?
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 506 of 950 rej09b0079-0200 carry detection circuit bus interface rhrcnt rtc r64cnt: rseccnt: rmincnt: rhrcnt: rwkcnt: rdaycnt: rmoncnt: ryrcnt: rsecar: 64-hz counter second counter minute counter hour counter day of the week counter date counter month counter year counter second alarm register rmincnt interrupt control circuit rdaycnt ryrcnt rmoncnt oscillator circuit extal2 rcr2 rcr3 xtal2 rwkcnt rhrar rminar rdayar rwkar externally connected circuit prescaler ( 2) prescaler ( 128) 32.768 khz 16.384 khz rcr1 comparator r64cnt rseccnt rsecar 128hz reset peripheral bus module bus 30- second adj ati pri cui rminar: rhrar: rwkar: rdayar: rmonar: ryrar: rcr1: rcr2: rcr3: minute alarm register hour alarm register day of the week alarm register date alarm register month alarm register year alarm register rtc control register 1 rtc control register 2 rtc control register 3 rmonar ryrar [legend] figure 15.1 rtc block diagram
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 507 of 950 rej09b0079-0200 15.2 input/output pins table 15.1 shows the rtc pin configuration. table 15.1 pin configuration pin name abbreviation i/o function rtc external clock extal2 i connects crystal to rtc oscillator * 1 rtc crystal xtal2 o connects crystal to rtc oscillator * 1 rtc oscillator power supply vccq-rtc ? dedicated power-supply pin for rtc * 2 rtc oscillator ground vssq-rtc ? dedicated gnd pin for rtc note: 1. pull up (vccq-rtc) the extal2 pin, and open (nc) the xtal2 pin when the realtime clock (rtc) is not used. 2. rtc in this lsi does not operate even if vccq-rtc is turned on. the crystal oscillator circuit for rtc operates with vccq-rtc. the control circuit and the rtc counter operate with vcc (common to the internal circ uit). therefore, all power supplies other than vccq-rtc should always be tur ned on even if only rtc operates. 15.3 register descriptions the rtc has the following registers. refer to section 24, list of registers, for more details on the address and access size. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 508 of 950 rej09b0079-0200 ? ? ? bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. 6 to 0 ? ? r 64-hz counter each bit (bits 6 to 0) indicates the state of the rtc divider circuit between 64 and 1hz. bit frequency 6: 1 hz 5: 2 hz 4: 4 hz 3: 8 hz 2: 16 hz 1: 32 hz 0: 64 hz 15.3.2 second counter (rseccnt) rseccnt is used for setting/counting in the bcd-c oded second section. the count operation is performed by a carry fo r each second of the 64 - hz counter. the range of second can be set is 0 to 59 (decimal). errant operation will result if any other value is set. carry out write processing after stoppin g the count operation with the start bit in rcr2.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 509 of 950 rej09b0079-0200 rseccnt is an 8-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 to 4 ? ? r/w counter for 10-unit of second in the bcd-code. the range can be set from 0 to 5 (decimal). 3 to 0 ? ? r/w counter for 1-unit of second in the bcd-code. the range can be set from 0 to 9 (decimal). 15.3.3 minute counter (rmincnt) rmincnt is used for setting/counting in the bcd-coded minute section. the count operation is performed by a carry for each minute of the second counter. the range of minute can be set is 0 to 59 (decimal). errant operation will result if any other value is set. carry out write processing after stoppin g the count operation with the start bit in rcr2. rmincnt is an 8-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0.the write value should always be 0. 6 to 4 ? ? r/w counter for 10-unit of minute in the bcd-code. the range can be set from 0 to 5 (decimal). 3 to 0 ? ? r/w counter for 1-unit of minute in the bcd-code. the range can be set from 0 to 9 (decimal). 15.3.4 hour counter (rhrcnt) rhrcnt is used for setting/counting in the bcd-coded hour section. the count operation is performed by a carry for each 1 hour of the minute counter.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 510 of 950 rej09b0079-0200 the range of hour can be set is 0 to 23 (decimal). errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2. rhrcnt is an 8-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0.the write value should always be 0. 5, 4 ? ? r/w counter for 10-unit of hour in the bcd-code. the range can be set from 0 to 2 (decimal). 3 to 0 ? ? r/w counter for 1-unit of hour in the bcd-code. the range can be set from 0 to 9 (decimal). 15.3.5 day of week counter (rwkcnt) rwkcnt is used for setting/counting day of week section. the count operation is performed by a carry for each day of the date counter. the range for day of the week can be set is 0 to 6 (decimal). errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2. rwkcnt is an 8-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 511 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 to 0 ? ? r/w counter for the day of week in the bcd-code. the range can be set from 0 to 6 (decimal). code day of week 0: sunday 1: monday 2: tuesday 3: wednesday 4: thursday 5: friday 6: saturday
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 512 of 950 rej09b0079-0200 15.3.6 date counter (rdaycnt) rdaycnt is used for setting/counting in the bcd-coded date section. the count operation is performed by a carry for each day of the hour counter. though the range of date which can be set is 1 to 31 (decimal), it changes with each month and in leap years. please confirm the correct setting. errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2. rdaycnt is an 8-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5, 4 ? ? r/w counter for 10-unit of date in the bcd-code. the range can be set from 0 to 3 (decimal). 3 to 0 ? ? r/w counter for 1-unit of date in the bcd-code. the range can be set from 0 to 9 (decimal). 15.3.7 month counter (rmoncnt) rmoncnt is used for setting/counting in the bcd-coded month section. the count operation is performed by a carry for each month of the date counter. the range of month can be set is 1 to 12 (decimal). errant operation will result if any other value is set. carry out write processing after stoppin g the count operation with the start bit in rcr2. rmoncnt is an 8-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 513 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 ? ? r/w counter for 10-unit of month in the bcd-code. the range can be set from 0 to 1 (decimal). 3 to 0 ? ? r/w counter for 1-unit of month in the bcd-code. the range can be set from 0 to 9 (decimal). 15.3.8 year counter (ryrcnt) ryrcnt is used for setting/counting in the bcd-coded year section. the 4 digits of the year are displayed. the count operation is performed by a carry for each year of the month counter. the range for year which can be set is 0000 to 9999 (decimal). errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2 or using a carry flag. ryrcnt is a 16-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode. leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result of 0. the year counter value of 0000 is included in the leap year. bit bit name initial value r/w description 15 to 12 ? ? r/w counter for 1000-unit of year in the bcd-code. the range can be set from 0 to 9 (decimal) 11 to 8 ? ? r/w counter for 100-unit of year in the bcd-code. the range can be set from 0 to 9 (decimal). 7 to 4 ? ? r/w counter for 10-unit of year in the bcd-code. the range can be set from 0 to 9 (decimal). 3 to 0 ? ? r/w counter for 1-unit of year in the bcd-code. the range can be set from 0 to 9 (decimal).
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 514 of 950 rej09b0079-0200 15.3.9 second alarm register (rsecar) rsecar is an alarm register co rresponding to the second counter rseccnt of the rtc. when the enb bit is set to 1, a comparison with the rseccnt value is performed. from among rsecar/rminar/rhrar/rwkar/rdayar/rmonar, the counter and alarm register comparison is performed only on those with enb bits and the yaen bit in rcr3 set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range of second alarm which ca n be set is 0 to 59 (decimal). errant operation will result if any other value is set. rsecar is an 8-bit readable/writable register. th e enb bit in rsecar is initialized to 0 by a power-on reset. the remaining rsecar fields ar e not initialized by a pow er-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w second alarm enable specifies whether comparison of rseccnt and rsecar is performed as an alarm condition. 0: not compared 1: compared 6 to 4 ? ? r/w setting value for 10-unit of second alarm in the bcd-code. the range can be set from 0 to 5 (decimal). 3 to 0 ? ? r/w setting value for 1-unit of second alarm in the bcd-code. the range can be set from 0 to 9 (decimal). 15.3.10 minute alarm register (rminar) rminar is an alarm register corresponding to the minute counter rmincnt. when the enb bit is set to 1, a comparison with the rmincnt value is performed. from among rsecar/rminar/rhrar/rwkar/rdayar/rmonar, the counter and alarm register comparison is performed only on those with enb bits and the yaen bit in rcr3 set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range of minute alarm which can be set is 0 to 59 (decimal). errant operation will result if any other value is set.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 515 of 950 rej09b0079-0200 rminar is an 8-bit readable/writable register. the enb bit in rminar is initialized by a power-on reset. the remaining rminar fields ar e not initialized by a pow er-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w minute alarm enable specifies whether comparison of rmincnt and rminar is performed as an alarm condition. 0: not compared 1: compared 6 to 4 ? ? r/w setting value for 10-unit of minute alarm in the bcd-code. the range can be set from 0 to 5 (decimal). 3 to 0 ? ? r/w setting value for 1-unit of minute alarm in the bcd-code. the range can be set from 0 to 9 (decimal). 15.3.11 hour alarm register (rhrar) rhrar is an alarm register co rresponding to the hour counter rhrcnt of the rtc. when the enb bit is set to 1, a comparison with the rhrcnt value is performed. from among rsecar/rminar/rhrar/rwkar/rdayar/rmonar, the counter and alarm register comparison is performed only on those with enb bits and the yaen bit in rcr3 set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range of hour alarm which can be set is 0 to 23 (decimal). errant operation will result if any other value is set. rhrar is an 8-bit readable/writable register. the enb bit in rhrar is initialized by a power- on reset. the remaining rhrar fields are not initialized by a power-on reset or manual reset, or in standby mode.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 516 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 enb 0 r/w hour alarm enable specifies whether comparison of rhrcnt and rhrar is performed as an alarm condition. 0: not compared 1: compared 6 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 5, 4 ? ? r/w setting value for 10-unit of hour alarm in the bcd-code. the range can be set from 0 to 2 (decimal). 3 to 0 ? ? r/w setting value for 1-unit of hour alarm in the bcd- code. the range can be set from 0 to 9 (decimal). 15.3.12 day of week alarm register (rwkar) rwkar is an alarm register co rresponding to the day of week counter rwkcnt. when the enb bit is set to 1, a comparison with the rwkcnt value is performed. from among rsecar/rminar/rhrar/rwkar/rdayar/rmonar, the counter and alarm register comparison is performed only on those with enb bits and the yaen bit in rcr3 set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range of day of the week alarm which can be set is 0 to 6 (decimal). errant operation will result if any other value is set. rwkar is an 8-bit readable/writable register. the enb bit in rwkar is initialized by a power- on reset. the remaining rwkar fields are not initialized by a power-on reset or manual reset, or in standby mode.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 517 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 enb 0 r/w day of week alarm enable specifies whether comparison of rwkcnt and rwkar is performed as an alarm condition. 0: not compared 1: compared 6 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 to 0 ? ? r/w day of week alarm code the range can be set from 0 to 6 (decimal). code day of the week 0: sunday 1: monday 2: tuesday 3: wednesday 4: thursday 5: friday 6: saturday 15.3.13 date alarm register (rdayar) rdayar is an alarm register corresponding to the date counter rdaycnt. when the enb bit is set to 1, a comparison with the rdaycnt value is performed. from among rsecar/rminar/rhrar/rwkar/rdayar/ and rm onar, the counter and alarm register comparison is performed only on those with enb bits and the yaen bit in rcr3 set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range of date alarm which can be set is 1 to 31 (decimal). errant operation will result if any other value is set. the rdaycnt range that can be set changes with some months and in leap years. please confirm the correct setting. rdayar is an 8-bit readable/writable register. the enb bit in rdayar is initialized by a power-on reset. the remaining rdayar fields are not initialized by a power-on reset or manual reset, or in standby mode.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 518 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 enb 0 r/w date alarm enable specifies whether comparison of rdaycnt and rdayar is performed as an alarm condition. 0: not compared 1: compared 6 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 5, 4 ? ? r/w setting value for 10-unit of date alarm in the bcd-code. the range can be set from 0 to 3 (decimal). 3 to 0 ? ? r/w setting value for 1-unit of date alarm in the bcd- code. the range can be set from 0 to 9 (decimal). 15.3.14 month alarm register (rmonar) rmonar is an alarm register corresponding to the month counter rmoncnt. when the enb bit is set to 1, a comparison with the rmoncnt value is performed. from among rsecar/rminar/rhrar/rwkar/rdayar/ and rm onar, the counter and alarm register comparison is performed only on those with enb bits and the yaen bit in rcr3 set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range of month alarm which can be set is 1 to 12 (decimal). errant operation will result if any other value is set. rmonar is an 8-bit readable/writable register. the enb bit in rmonar is initialized by a power-on reset. the remaining rmonar fields are not initialized by a power-on reset or manual reset, or in standby mode.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 519 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 enb 0 r/w month alarm enable specifies whether comparison of rmoncnt and rmonar is performed as an alarm condition. 0: not compared 1: compared 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 ? ? r/w setting value for 10-unit of month alarm in the bcd-code. the range can be set from 0 to 1 (decimal). 3 to 0 ? ? r/w setting value for 1-unit of month alarm in the bcd-code. the range can be set from 0 to 9 (decimal). 15.3.15 year alarm register (ryrar) ryrar is an alarm register co rresponding to the year counter ryrcnt. when the yaen bit in rcr3 is set to 1, a comparison with th e ryrcnt value is performed. from among rsecar/rminar/rhrar/rwkar/rdayar/ and rm onar, the counter and alarm register comparison is performed only on those with enb bits and the yaen bit in rcr3 set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range of year alarm which can be set is 0000 to 9999 (decimal). errant operation will result if any other value is set. ryrar is a 16-bit readable/writa ble register. the contents are no t initialized by a power-on reset or manual reset, or in standby mode.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 520 of 950 rej09b0079-0200 bit bit name initial value r/w description 15 to 12 ? ? r/w setting value for 1000-unit of year alarm in the bcd-code. the range can be set from 0 to 9 (decimal). 11 to 8 ? ? r/w setting value for 100-unit of year alarm in the bcd-code. the range can be set from 0 to 9 (decimal). 7 to 4 ? ? r/w setting value for 10-unit of year alarm in the bcd-code. the range can be set from 0 to 9 (decimal). 3 to 0 ? ? r/w setting value for 1-unit of year alarm in the bcd- code. the range can be set from 0 to 9 (decimal). 15.3.16 rtc control register 1 (rcr1) rcr1 is a register that affects carry flags and al arm flags. it also selects whether to generate interrupts for each flag. because flags are sometimes set after an operand read, do not use this register in read-modify-write processing. rcr1 is an 8-bit readable/writable register. rcr1 is initialized to h'00 by a power-on reset or a manual reset, all bits are initialized to 0 except for the cf flag, which is undefined. when using the cf flag, it must be initialized beforehand. th is register is not initialized in standby mode. bit bit name initial value r/w description 7 cf undefined r/w carry flag status flag that indicates that a carry has occurred. cf is set to 1 when a count-up to r64cnt or rseccnt occurs. a count register value read at this time cannot be guaranteed; another read is required. 0: no count up of r64cnt or rseccnt. clearing condition: when 0 is written to cf 1: count up of r64cnt or rseccnt. setting condition: when 1 is written to cf or if the carry of r64cnt or rseccnt occurs when r64cnt or rseccnt is read.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 521 of 950 rej09b0079-0200 bit bit name initial value r/w description 6 5 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0. 4 cie 0 r/w carry interrupt enable flag when the carry flag (cf) is set to 1, the cie bit enables interrupts. 0: a carry interrupt is not generated when the cf flag is set to 1 1: a carry interrupt is generated when the cf flag is set to 1 3 aie 0 r/w alarm interrupt enable flag when the alarm flag (af) is set to 1, the aie bit allows interrupts. 0: an alarm interrupt is not generated when the af flag is set to 1 1: an alarm interrupt is generated when the af flag is set to 1 2 1 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0. 0 af 0 r/w alarm flag the af flag is set to 1 when the alarm time set in an alarm register (only registers with the enb bit of the corresponding al arm registers and yaen bit in rcr3 set to 1) matches the clock and calendar time. this flag is cleared to 0 when 0 is written, but holds the previous value when 1 is to be written. 0: clock/calendar and alarm register have not matched. clearing condition: when 0 is written to af 1: clock/calendar and alarm register have matched. setting condition: clock/calendar and alarm register have matched (only registers with the enb bit and yaen bit in rcr3 set to 1)
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 522 of 950 rej09b0079-0200 15.3.17 rtc control register 2 (rcr2) rcr2 is a register for periodic interrupt contro l, 30-second adjustment adj, divider circuit reset, and rtc count start/stop control. rcr2 is an 8-bit readable/writable register. it is initialized to h'09 by a power-on reset. it is initialized except for rtcen and start by a manual reset. it is not initialized in standby mode, and retains its contents. bit bit name initial value r/w description 7 pef 0 r/w periodic interrupt flag indicates interrupt generation with the period designated by the pes2 to pes0 bits. when set to 1, pef generates periodic interrupts. 0: interrupts not generated with the period designated by the pes bits. clearing condition: when 0 is written to pef 1: interrupts generated with the period designated by the pes bits. setting condition: when an interrupt is generated with the period designated by the pes0 to pes2 bits or when 1 is written to the pef flag 6 5 4 pes2 pes1 pes0 0 0 0 r/w r/w r/w periodic interrupt flags these bits specify the periodic interrupt. 000: no periodic interrupts generated 001: periodic interrupt generated every 1/256 second 010: periodic interrupt generated every 1/64 second 011: periodic interrupt generated every 1/16 second 100: periodic interrupt generated every 1/4 second 101: periodic interrupt generated every 1/2 second 110: periodic interrupt generated every 1 second 111: periodic interrupt generated every 2 seconds
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 523 of 950 rej09b0079-0200 bit bit name initial value r/w description 3 rtcen 1 r/w controls the operatio n of the crystal oscillator for the rtc. 0: halts the crystal o scillator for the rtc. 1: runs the crystal oscillator for the rtc. 2 adj 0 r/w 30-second adjustment when 1 is written to the adj bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. the divider circuit (rtc prescaler and r64cnt) will be simultaneously reset. this bit always reads 0. 0: runs normally. 1: 30-second adjustment. 1 reset 0 r/w reset when 1 is written, initializes the divider circuit (rtc prescaler and r64cnt). this bit always reads 0. 0: runs normally. 1: divider circuit is reset. 0 start 1 r/w start bit halts and restarts the counter (clock). 0: second/minute/hour/day/week/month/year counter halts. 1: second/minute/hour/day/week/month/year counter runs normally. note: the 64-hz counter always runs unless stopped with the rtcen bit.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 524 of 950 rej09b0079-0200 15.3.18 rtc control register 3 (rcr3) rcr3 is a register that controls comparison of the bcd-coded year counter ryrcnt and the year alarm register ryrar of the rtc. rcr3 is an 8-bit readable/writable register. bit bit name initial value r/w description 7 yaen 0 r/w year alarm enable when this bit is set to 1, comparison of the year alarm register (ryrar) and the year counter (ryrcnt) is performed. from among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. 6 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 525 of 950 rej09b0079-0200 15.4 operation 15.4.1 initial settings of registers after power-on all the registers should be set after the power is turned on. 15.4.2 setting time figure 15.2 shows how to set the time when the clock is stopped. write 1 to reset and 0 to start in the rcr2 register order is irrelevant write 1 to start in the rcr2 register set seconds, minutes, hour, day, day of the week, month, and year stop clock, reset divider circuit start clock figure 15.2 setting time 15.4.3 reading time figure 15.3 shows how to read the time. if a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. part (a) in figure 15.3 shows the method of reading the time without using interrupts; part (b) in figure 15.3 shows the method using carry interrupts. to keep programming simple, method (a) should normally be used.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 526 of 950 rej09b0079-0200 write 0 to cf in rcr1 note: set af in rcr1 to 1 so that alarm flag is not cleared. write 0 to cie in rcr1 read rcr1 and check cf write 0 to cie in rcr1 carry flag = 1? no yes clear the carry flag disable the carry interrupt read counter register write 1 to cie in rcr1, and write 0 to cf in rcr1 note: set af in rcr1 to 1 so that alarm flag is not cleared. interrupt generated? no yes enable the carry interrupt clear the carry flag disable the carry interrupt read counter register to read the time without using interrupts (b) to use interrupts (a) figure 15.3 reading time
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 527 of 950 rej09b0079-0200 15.4.4 alarm function figure 15.4 shows how to use the alarm function. alarms can be generated using seconds, minutes, hours, day of the week, date, month, year, or any combination of these. set the enb bit or yaen bit in the register on wh ich the alarm is placed to 1, and then set the alarm time in the lower bits. clear the enb bit in the register on which the alarm is not placed to 0. when the clock and alarm times match, 1 is set in the af bit in rcr1. alarm detection can be checked by reading this bit, but normally it is done by interrupt. if 1 is set in the aie bit in rcr1, an interrupt is generated when an alarm occurs. disable interrupt to prevent errorneous interruption.(aie bit in rcr1 is cleared) then write 1. clock running set alarm time set whether to use alarm interrupt always clear, since the flag may have been set while the alarm time was being set. (write 0 to af of rcr1 to clear it. ) clear alarm flag monitor alarm time (wait for interrupt or check alarm flag) figure 15.4 using alarm function
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 528 of 950 rej09b0079-0200 15.4.5 crystal oscillator circuit crystal oscillator circuit constants (recommended values) are shown in table 15.2, and the rtc crystal oscillator circuit in figure 15.5. table 15.2 recommended oscillator circu it constants (recommended values) f osc c in c out 32.768 khz 10 to 22 pf 10 to 22 pf sh7710 extal2 xtal2 xtal c in c out r f r d notes: 1. select either the c in or c out side for frequency adjustment variable capacitor according to requirements such as frequency range, degree of stability, etc. 2. built-in resistance value r f (typ value) = 10 m ? , r d (typ value) = 400 k ? 3. c in and c out values include stray capacitance due to the wiring. take care when using a ground plane. 4. the crystal oscillation settling time depends on the mounted circuit constants, stray capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. place the crystal resonator and load capacitors c in and c out as close as possible to the chip. (correct oscillation may not be possible if there is externally induced noise in the extal2 and xtal2 pins.) 6. ensure that the crystal resonator connection pin (extal2, xtal2) wiring is routed as far away as possible from other power lines (except gnd) and signal lines. figure 15.5 example of crys tal oscillator ci rcuit connection
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 529 of 950 rej09b0079-0200 15.5 usage notes 15.5.1 register writing during rtc count the following rtc registers cannot be written to during an rtc count (while the start bit = 1 in rcr2). rseccnt, rmincnt, rhrcnt, rd aycnt, rwkcnt, rmoncnt, ryrcnt the rtc count must be stopped before writing to any of the above registers. 15.5.2 use of real time clock (rtc) periodic interrupts the method of using the periodic interrupt function is shown in figure 15.6. a periodic interrupt can be generated periodically at the interval set by the periodic interrupt flag (pes0 ? ? set pes0 to pes2, and clear pef to 0, in rcr2 clear pef to 0 set pes, clear pef elapse of time set by pes clear pef figure 15.6 using periodic interrupt function 15.5.3 transition to standby mode after setting register when a transition to standby mode is made after registers in the rtc are set, sometimes counting is not performed correctly. in case the registers are set, be sure to make a transition to standby mode after waiting for two rtc clocks or more.
section 15 realtime clock (rtc) rev. 2.00 dec. 07, 2005 page 530 of 950 rej09b0079-0200 15.5.4 usage note about rtc power supply rtc in this lsi does not operate even if vccq-rtc is turned on. the crystal oscillator circuit for rtc operates with vccq-rtc. the control circuit and the rt c counter operate with vcc (common to the internal circu it). therefore, all power supplies other than vccq-rtc should always be turned on even if only rtc operates.
section 16 serial communication interface with fifo (scif) scis3c3a_000020020900 rev. 2.00 dec. 07, 2005 page 531 of 950 rej09b0079-0200 section 16 serial communi cation interface with fifo (scif) this lsi has a two-channel seri al communication inte rface with on-chip fifo buffers (serial communication interface with fi fo: scif). the scif can perform asynchronous and clock synchronous serial communication. the scif provides a 16-stage fifo register for both transmission and reception, enabling fast, efficient, and continuous communication. 16.1 features the scif features are listed below. ? ? ? ?
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 532 of 950 rej09b0079-0200 ? ? ? ? ? cts0 / cts1 and rts0 / rts1 ) ? ? ? ?
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 533 of 950 rej09b0079-0200 module data bus bus interface scfrdr_n (16-stage) scrsr_n rxdn txdn scifnck scftdr_n (16-stage) sctsr_n sclsr_n scfcr_n scfsr_n scscr_n scsmr_n scbrr_n baud rate generator transmission/ reception control clock external clock p p /4 p /16 p /64 txin rxin scifn scrsr_n: scfrdr_n: sctsr_n: scftdr_n: scsmr_n: scscr_n: [legend] receive shift register receive fifo data register transmit shift register transmit fifo data register serial mode register serial control register scfsr_n: scbrr_n: scfcr_n: scfdr_n: sclsr_n: n: serial status register bit rate register fifo control register fifo data count register line status register 0, 1 scfdr_n ctsn rtsn brin parity generation parity check internal data bus erin figure 16.1 block diagram of scif
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 534 of 950 rej09b0079-0200 16.2 input/output pins table 16.1 shows the scif pin configuration. table 16.1 pin configuration channel pin name a bbreviation i/o function 0 serial clock pin scif0ck input/output clock input/output receive data pin rxd0 input receive data input transmit data pin txd0 ou tput transmit data output modem control pin cts0 input transmission clear modem control pin rts0 output transmit request 1 serial clock pin scif1ck input/output clock input/output receive data pin rxd1 input receive data input transmit data pin txd1 ou tput transmit data output modem control pin cts1 input transmission clear modem control pin rts1 output transmit request note: these pins function as serial pins by making the scif operation settings with the c/ a bit in scsmr, te, re, cke1, and cke0 bits in scscr, and mce bit in scfcr.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 535 of 950 rej09b0079-0200 16.3 register descriptions the scif has the following regist ers. for details on addresses an d access sizes of these registers, see section 24, list of registers. channel 0: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 536 of 950 rej09b0079-0200 16.3.1 receive shift register (scrsr) scrsr is the register used to receive serial data. the scif sets serial data input from the rxd pin in scrsr in the order received, starting with the lsb (bit 0), and converts it to parallel data. wh en one byte of data has been received, it is transferred to the recei ve fifo data register scfrdr, automatically. scrsr cannot be directly read or written to by the cpu. 16.3.2 receive fifo da ta register (scfrdr) scfrdr is a 16-stage fifo register that stores received serial data. when the scif has received one byte of serial da ta, it transfers the receive d data from scrsr to scfrdr where it is stored, and completes the receive operation. scrsr is then enabled for reception, and consecutive receive operations can be performed until the receive fifo data register is full (16 data bytes). scfrdr is a read-only register, and cannot be written to by the cpu. if a read is performed when there is no receive data in the receive fifo data register, an undefined value will be returned. when the r eceive fifo data register is fu ll of receive data, subsequent serial data is lost. the contents of scfrdr are undefined after a power-on reset or manual reset.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 537 of 950 rej09b0079-0200 16.3.3 transmit shift register (sctsr) sctsr is the register used to transmit serial data. to perform serial data transmission, the scif first transfers transmit data from scftdr to sctsr, then sends the data sequentially to the txd pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from scftdr to sctsr, and transmission started, automatically. sctsr cannot be directly read or written to by the cpu. 16.3.4 transmit fifo data register (scftdr) scftdr is an 8-bit 16-stage fifo data register that stores data for serial transmission. if sctsr is empty when transmit data has been written to scftdr, the scif transfers the transmit data written in scftdr to sctsr and starts serial transmission. scftdr is a write-only register, and cannot be read by the cpu. the next data cannot be written when scftdr is filled with 16 bytes of transmit data. data written in this case is ignored. the contents of scftdr are undefined after a power-on reset or manual reset. 16.3.5 serial mode register (scsmr) scsmr is a 16-bit register used to set the scif ?s serial communication format and select the clock source of the baud rate generator. scsmr can be read or written to by the cpu at all times. scsmr is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state, and retains its contents.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 538 of 950 rej09b0079-0200 bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 c/ a 0 r/w communication mode selects asynchronous mode or clock synchronous mode as the scif operating mode. 0: asynchronous mode 1: clock synchronous mode 6 chr 0 r/w character length selects 7 or 8 bits as the asynchronous mode data length. in clock synchronous mode, a fixed data length of 8 bits is used regardless of the chr setting. 0: 8-bit data 1: 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of the transmit fifo data register (scftdr) is not transmitted. 5 pe 0 r/w parity enable in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in clock synchronous mode, parity bit addition and checking is not performed, regardless of the pe bit setting. 0: parity bit addition and checking disabled 1: parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 539 of 950 rej09b0079-0200 bit bit name initial value r/w description 4 o/ e 0 r/w parity mode selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking in asynchronous mode. the o/ e bit setting is invalid in clock synchronous mode, and when parity addition and checking is disabled in asynchronous mode. 0: even parity * 1 1: odd parity * 2 notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 540 of 950 rej09b0079-0200 bit bit name initial value r/w description 3 stop 0 r/w stop bit length selects 1 or 2 bits as the stop bit length. the stop bit setting is only valid in asynchronous mode. when clock synchronous mode is set, the stop bit setting is invalid since stop bits are not added. 0: 1 stop bit * 1 1: 2 stop bits * 2 notes: 1. in transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. in transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 0 cks1 cks0 0 0 r/w r/w clock select 1 and 0 select the clock source for the on-chip baud rate generator. 00: p 01: p /4 10: p /16 11: p /64
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 541 of 950 rej09b0079-0200 16.3.6 serial control register (scscr) scscr performs enabling or disabling of the scif transfer operations and interrupt requests, and selection of the serial clock source. scscr can be read or written to by the cpu at all times. scscr is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state, and retains its contents. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 tie 0 r/w transmit interrupt enable enables or disables gener ation of a transmit-fifo- data-empty interrupt (txi) request when the tdfe flag in scfsr is set to 1 after the serial transmit data is transferred from scftdr to sctsr and the number of data bytes in the transmit fifo register is equal to or below the trigger set number. 0: transmit-fifo-data-empt y interrupt (txi) request disabled * 1: transmit-fifo-data-empt y interrupt (txi) request enabled note: * txi interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to scftdr, reading 1 from the tdfe flag, then clearing it to 0, or by clearing the tie bit to 0.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 542 of 950 rej09b0079-0200 bit bit name initial value r/w description 6 rie 0 r/w receive interrupt enable enables or disables generation of a receive-data-full interrupt (rxi) request when the rdf flag or dr flag in scfsr is set to 1, re ceive-error interrupt (eri) request when the er flag in scfsr is set to 1, or break-interrupt (bri) request when the brk flag in scfsr or the orer flag in sclsr is set to 1. 0: receive-data-full interrupt (rxi) request, receive- error interrupt (eri) request, and break-interrupt (bri) request disabled * 1: receive-data-full interrupt (rxi) request, receive- error interrupt (eri) request, and break-interrupt (bri) request enabled note: * an rxi request can be cleared by reading 1 from the rdf flag or dr flag, then clearing the flag to 0, or by clearing the rie bit to 0. the eri and bri requests can be cleared by reading 1 from the er, brk, or orer flag, then clearing the flag to 0, or clearing the rie and reie bits to 0. 5 te 0 r/w transmit enable enables or disables the start of serial transmission by the scif. 0: transmission disabled 1: transmission enabled * note: * scsmr and scfcr settings must be made, the transmit format decided, and the transmit fifo reset, before the te bit is set to 1.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 543 of 950 rej09b0079-0200 bit bit name initial value r/w description 4 re 0 r/w receive enable enables or disables the start of serial reception by the scif. 0: reception disabled * 1 1: reception enabled * 2 notes: 1. clearing the re bit to 0 does not affect the dr, er, brk, rdf, fer, per, and orer flags, which retain their state. 2. scsmr and scfcr settings must be made, the receive format decided, and the receive fifo reset, before the re bit is set to 1. 3 reie 0 r/w receive error interrupt enable enables or disables generation of receive-error interrupt (eri) request and break interrupt (bri) request. the reie bit setting is available when the rie bit is cleared to 0. 0: receive-error interrupt (eri) request and break interrupt (bri) request disabled * 1: receive-error interrupt (eri) request and break interrupt (bri) request enabled note: * a receive-error interrupt (eri) request and break interrupt (bri) request can be cleared by reading 1 from the er, brk, and orer flags, then clearing the flags to 0, or by clearing the rie and reie bits to 0. even if the rie bit is cleared to 0, setting the reie bit to 1 enables generation of the eri and bri requests. this setting is achieved to notify the eri and bri requests to the interrupt controller at the dmac transfer. 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 544 of 950 rej09b0079-0200 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 1 and 0 select the scif clock source and enable or disable clock output from the scifnck pin. the combination of the cke1 bit and cke0 bit determines whether the scifnck pin is set as a serial clock output pin or a serial clock input pin. the setting of the cke0 bit is available in internal clock operation (cke1 = 0). in the case of external clock operation (cke1 = 1), the setting of the cke0 bit is not available. the cke1 and cke0 bits must be set before the scif operating mode is selected by scsmr. ? asynchronous mode 00: internal clock/scifnck pin functions as input pin (input signal ignored) 01: internal clock/scifnck pin functions as clock output * 2 1- * 1 : external clock/scifnck pin functions as clock input * 3 ? clock synchronous mode 00: internal clock/scifnck pin functions as synchronous clock output 01: internal clock/scifnck pin functions as synchronous clock output 1- * 1 : external clock/scifnck pin functions as synchronous clock input notes: 1. when cke1 = 1, the value of cke0 is don?t care. 2. the output clock frequency is 16 times the bit rate. 3. the input clock frequency is 16 times the bit rate.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 545 of 950 rej09b0079-0200 16.3.7 serial status register (scfsr) scfsr is a 16-bit register. the lower 8 bits sp ecify the status flags that indicate the scif operating status. the upper 8 bits indicate the receive er ror number of data in the receive-fifo register. scfsr can be read or written to by the cpu at all times. however, 1 cannot be written to the er, tend, tdfe, brk, rdf, and dr flags. also note th at in order to clear these flags to 0, they must be read as 1 beforehand. the fer and per flags are read-onl y flags and cannot be modified. scfsr is initialized to h'0060 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state, and retains its contents. bit bit name initial value r/w description 15 14 13 12 per3 per2 per1 per0 0 0 0 0 r r r r parity error number 3 to 0 indicate the number of dat a bytes, in which parity errors are generated, in receive data stored in scfrdr. after setting the er bit in scfsr, the values of bits 15 to 12 indicate the number of parity error generated data. when all 16 bytes of receive data in scfrdr has parity errors, the per3 to per0 bits indicate 0. 11 10 9 8 fer3 fer2 fer1 fer0 0 0 0 0 r r r r framing error number 3 to 0 indicate the number of dat a bytes, in which framing errors are generated, in receive data stored in scfrdr. after setting the er bit in scfsr, the values of bits 11 to 8 indicate the number of framing error generated data. when all 16 bytes of receive data in scfrdr has framing errors, the fer3 to fer0 bits indicate 0.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 546 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 er 0 r/(w) * receive error indicates that a framing error or parity error occurred during reception. * 1 0: no framing error or parity error occurred during reception [clearing conditions] ? power-on reset or manual reset ? when 0 is written to er after reading er = 1 1: a framing error or parity error occurred during reception [setting conditions] ? when the scif checks w hether the stop bit at the end of the receive dat a is 1 when reception ends, and the stop bit is 0 * 2 ? when, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in scsmr notes: 1. the er flag is not affected and retains its previous state when the re bit in scscr is cleared to 0. when a receive error occurs, the receive data is still transferred to scfrdr, and reception continues. the fer and per bits in scfsr can be used to determine whether there is a receive error in the data read from scfrdr. 2. when the stop length is 2 bits, only the first stop bit is checked for a value of 1; the second stop bit is not checked.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 547 of 950 rej09b0079-0200 bit bit name initial value r/w description 6 tend 1 r/(w) * transmit end indicates that there is no valid data in scftdr when the last bit of the transmit character is sent, and transmission has been ended. 0: transmission is in progress [clearing conditions] ? when the tend flag is cleared to 0 after the transmit data is written to scftdr and tend = 1 is read ? when data is written to scftdr by the dmac 1: transmission has been ended [setting conditions] ? power-on reset or manual reset ? the te bit in scscr is cleared to 0 ? when there is no transmit data in scftdr on transmission of the last bit of 1-byte serial transmit character
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 548 of 950 rej09b0079-0200 bit bit name initial value r/w description 5 tdfe 1 r/(w) * transmit fifo data empty indicates that data has been transferred from scftdr to sctsr, the number of data bytes in scftdr has been equal to or below the transmit trigger data number set by bits ttrg1 and ttrg0 in scfcr, and new transmit data can be written to scftdr. 0: a number of transmit data bytes exceeding the transmit trigger set number have been written to scftdr [clearing conditions] ? when transmit data exceeding the transmit trigger set number is written to scftdr, and 0 is written to the tdfe bit after reading tdfe = 1 ? when transmit data exceeding the transmit trigger set number is written to scftdr by the dmac 1: the number of transmit data bytes in scftdr does not exceed the transmit trigger set number [setting conditions] ? power-on reset or manual reset ? when the number of scftdr transmit data bytes is equal to or below the transmit trigger set number as the result of a transmit operation * note: * as scftdr is a 16-byte fifo register, the maximum number of bytes that can be written when tdfe = 1 is 16 ? (transmit trigger set number). data written in excess of this will be ignored. the number of data bytes in scftdr is indicated by the upper bits in scfdr.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 549 of 950 rej09b0079-0200 bit bit name initial value r/w description 4 brk 0 r/(w) * break detect in asynchronous mode, indicates that a receive data break signal has been detected or not. 0: a break signal has not been received [clearing conditions] ? power-on reset or manual reset ? when 0 is written to brk after reading brk = 1 1: a break signal has been received * [setting condition] when data with a framing error is received, followed by the space ?0? level (low level) for at least one frame length note: * when a break is detected, the receive data (h'00) following detection is not transferred to scfrdr. when the break ends and the receive signal returns to mark ?1?, receive data transfer is resumed. 3 fer 0 r framing error in asynchronous mode, indicates that there is a framing error or not in the data read from scfrdr. 0: there is no framing erro r in the receive data read from scfrdr [clearing conditions] ? power-on reset or manual reset ? when there is no framing error in scfrdr read data 1: there is a framing error in the receive data read from scfrdr [setting condition] when there is a framing error in scfrdr read data
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 550 of 950 rej09b0079-0200 bit bit name initial value r/w description 2 per 0 r parity error in asynchronous mode, indicates that there is a parity error or not in the data read from scfrdr. 0: there is no parity error in the receive data read from scfrdr [clearing conditions] ? power-on reset or manual reset ? when there is no parity error in scfrdr read data 1: there is a parity error in the receive data read from scfrdr [setting condition] when there is a parity error in scfrdr read data
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 551 of 950 rej09b0079-0200 bit bit name initial value r/w description 1 rdf 0 r/(w) * receive fifo data full indicates that the received data has been transferred from scrsr to scfrdr, and the number of receive data bytes in scfrdr is equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in scfcr. 0: the number of receive data bytes in scfrdr is less than the receive trigger set number [clearing conditions] ? power-on reset or manual reset ? when scfrdr is read until the number of receive data bytes in scfrdr is less than the receive trigger set number, and 0 is written to rdf after reading rdf = 1 ? when scfrdr is read by the dmac until the number of receive data bytes in scfrdr is less than the receive trigger set number 1: the number of receive data bytes in scfrdr is equal to or greater than the receive trigger set number [setting condition] when scfrdr contains at least the receive trigger set number of receive data bytes * note: * scfrdr is a 16-byte fifo register. when rdf = 1, at least the receive trigger set number of data bytes can be read. if data is read when scfrdr is empty, an undefined value will be returned. the number of receive data bytes in scfrdr is indicated by the lower bits in scfdr.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 552 of 950 rej09b0079-0200 bit bit name initial value r/w description 0 dr 0 r/(w) * receive data ready in asynchronous mode, indicates that there are fewer than the receive trigger set number of data bytes in scfrdr, and no further data has arrived for at least 15 etu after t he stop bit of the last data received. 0: reception is in progress or has ended successfully and there is no receive data left in scfrdr [clearing conditions] ? power-on reset or manual reset ? when all the receive data in scfrdr has been read, and 0 is written to dr after reading dr = 1 ? when all the receive data in scfrdr is read by the dmac 1: no further receive data has arrived [setting condition] when scfrdr contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received * note: * corresponds to 1.5 frame time when the format of 8-bit length and 1 stop bit is used. etu: elementary time unit (time for transfer of 1 bit) note: * only 0 can be written for clearing the flags.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 553 of 950 rej09b0079-0200 16.3.8 bit rate register (scbrr) scbrr is an 8-bit register that sets the serial tr ansfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in scsmr. scbrr can be read or written to by the cpu at all times. scbrr is initialized to h'ff by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state, and retains its contents. the scbrr setting is found from the following equation. asynchronous mode: n = p 64 2 2n?1 b 10 6 ? 1 clock synchronous mode: n = p 8 2 2n?1 b 10 6 ? 1 where b: bit rate (bits/s) n: scbrr setting for baud rate generator (0 n 255) p : peripheral module operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see table 16.2 for the relati on between n and the clock.) table 16.2 relationship between n and clock scsmr setting n clock cks1 cks0 0 p 0 0 1 p /4 0 1 2 p /16 1 0 3 p /64 1 1 the bit rate error in asynchronous mode is found from the following equation:
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 554 of 950 rej09b0079-0200 error (%) = ? 1 100 (n + 1) b 64 2 2n?1 p 10 6 ? ? ? ? ? ? 16.3.9 fifo control register (scfcr) scfcr performs data count resetting and trigger da ta number setting for the transmit and receive fifo registers, and also contai ns a loopback test enable bit. scfcr can be read or written to by the cpu at all times. scfcr is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state, and retains its contents. bit bit name initial value r/w description 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 rstrg2 rstrg1 rstrg0 0 0 0 r/w r/w r/w rts output active trigger 2 to 0 the rts signal goes high when the number of receive data bytes in scfrdr is equal to or greater than the trigger set number shown in below. rts active trigger: 000: 15 001: 1 010: 4 011: 6 100: 8 101: 10 110: 12 111: 14
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 555 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 6 rtrg1 rtrg0 0 0 r/w r/w receive fifo data number trigger 1 and 0 set the number of receive data bytes that sets the rdf flag in scfsr. the rdf flag is set when the number of receive data bytes in scfrdr is equal to or greater than the trigger set number shown in below. asynchronous mode clock synchronous mode 00: 1 00: 1 01: 4 01: 2 10: 8 10: 8 11: 14 11: 14 5 4 ttrg1 ttrg0 0 0 r/w r/w transmit fifo data number trigger 1 and 0 set the number of remaining transmit data bytes that sets the tdfe flag in scfsr. the tdfe flag is set when, as the result of a transmit operation, the number of transmit data bytes in scftdr is equal to or below the trigger set number shown in below. 00: 8 (8) 01: 4 (12) 10: 2 (14) 11: 0 (16) note: the values in parentheses are the number of empty bytes in scftdr when the flag is set. 3 mce 0 r/w modem control enable enables modem control signals cts and rts . this bit is valid only in asynchronous mode. 0: modem signal disabled * 1: modem signal enabled note: * cts is fixed at active 0 regardless of the input value, and rts is also fixed at 0.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 556 of 950 rej09b0079-0200 bit bit name initial value r/w description 2 tfrst 0 r/w transmit fifo data register reset invalidates the transmit data in the transmit fifo data register and resets it to the empty state. 0: reset operation disabled * 1: reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset. 1 rfrst 0 r/w receive fifo data register reset invalidates the receive data in the receive fifo data register and resets it to the empty state. 0: reset operation disabled * 1: reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset. 0 loop 0 r/w loopback test internally connects the transmit output pin (txd) and receive input pin (rxd), and rts pin and cts pin, enabling loopback testing. 0: loopback test disabled 1: loopback test enabled 16.3.10 fifo data count register (scfdr) scfdr is a 16-bit register that indicates the number of data bytes stored in scftdr and scfrdr. bits 12 to 8 show the number of transmit data bytes in scftdr, and bits 4 to 0 show the number of receive data bytes in scfrdr. scfdr can be read by the cpu at all times. scfdr is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state, and retains its contents.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 557 of 950 rej09b0079-0200 bit bit name initial value r/w description 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 10 9 8 t4 t3 t2 t1 t0 0 0 0 0 0 r r r r r bits 12 to 8 in scfdr show the number of untransmitted data bytes in scftdr. a value of h'00 means that there is no transmit data, and a value of h'10 means that scftdr is full of transmit data. 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 3 2 1 0 r4 r3 r2 r1 r0 0 0 0 0 0 r r r r r bits 4 to 0 in scfdr show the number of receive data bytes in scfrdr. a value of h'00 means that there is no receive data, and a value of h'10 means that scfrdr is full of receive data.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 558 of 950 rej09b0079-0200 16.3.11 line status register (sclsr) sclsr is a 16-bit register that indicates whether an overrun error occurs or not during reception. bit bit name initial value r/w description 15 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 orer 0 r/(w) * overrun error indicates that an overrun error occurred during reception and reception is ended abnormally. 0: reception is in progre ss, or reception has ended successfully * 1 [clearing conditions] ? power-on reset or manual reset ? when 0 is written to orer after reading orer = 1 1: an overrun error occurred during reception * 2 [setting condition] when serial reception is completed while the receive fifo is full notes: 1. the orer flag is not affected and retains its previous state when the re bit in scscr is cleared to 0. 2. the receive data prior to the overrun error is retained in scfrdr, and the data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1. note: * only 0 can be written to clear the flag.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 559 of 950 rej09b0079-0200 16.4 operation 16.4.1 overview the scif can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character, and in clock synchronous mode, in which synchronization is achieved with clock pulses. 16-stage fifo buffers are provided for both transmission and reception, reducing the cpu overhead and enabling fast, continuous communication to be performed. also, the rts and cts signals are included as modem control signals. transfer format is selected by scsmr. this is shown in table 16.3. the scif clock source is determined by the combination of the c/ a bit in scsmr and the cke1 and cke0 bits in scscr. this is shown in table 16.4. asynchronous mode ? ? ? ? ? ? ? ?
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 560 of 950 rej09b0079-0200 table 16.3 scsmr settings for s erial transfer format selection scsmr settings the scif transfer format bit 7: c/ a bit 6: chr bit 5: pe bit 3: stop mode data length parity bit stop bit length 0 0 0 0 asynchronous mode 8-bit data no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 1 * * * clock synchronous mode 8-bit data no no table 16.4 scsmr and scscr settings fo r the scif clock source selection scsmr scscr bit 7: c/ a bit 1: cke1 bit 0: cke0 mode clock source scifnck pin function 0 scif does not use the scifnck pin 0 1 internal outputs a clock with frequency 16 times the bit rate 0 0 1 1 asynchronous mode external inputs a clock with frequency 16 times the bit rate 0 0 1 internal outputs the synchronous clock 0 1 1 1 clock synchronous mode external inputs the synchronous clock
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 561 of 950 rej09b0079-0200 16.4.2 serial operation in asynchronous mode in asynchronous mode, each transmitted or received ch aracter begins with a start bit and ends with a stop bit. serial communicati on is synchronized one character at a time. figure 16.2 shows the general format of asynchronous serial communication. in asynchronous serial communication, the communication line is normally held in the mark (high) state. the scif monitors the line and starts serial communicat ion when the line goes to the space (low) state, indicating a start bit. one serial communication ch aracter consists of a start bit (low), data (lsb first), parity bit (high/low), an d stop bit (high), in this order. in asynchronous mode, the scif synchronizes at the falling edge of the start bit durin g reception. the scif samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. therefore, communication data is la tched at the center of each bit. d0 d1 d2 d3 d4 d5 d6 d7 0/1 0 11 1 1 start bit parity bit stop bit 1 bit 7 bits or 8 bits 1 bit or no bit 1 bit or 2 bits one unit of communication data (character or frame) idle state (mark state) transmit/receive data serial data figure 16.2 data format in asynchronous communication (example of 8-bit data with parity and 2 stop bits)
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 562 of 950 rej09b0079-0200 data transfer format: table 16.5 shows the tran sfer formats that can be used in asynchronous mode. any of 8 transfer fo rmats can be selected accord ing to the scsmr settings. table 16.5 serial transfer formats scsmr settings serial transf er format and frame length chr pe stop 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 s 8-bit data stop 1 s 8-bit data stop stop 1 0 s 8-bit data p stop 1 s 8-bit data p stop stop 1 0 0 s 7-bit data stop 1 s 7-bit data stop stop 1 0 s 7-bit data p stop 1 s 7-bit data p stop stop s: start bit stop: stop bit p: parity bit clock: the scif transfer clock is set by the c/ a bit in scsmr and the cke1 and cke0 bits in scscr. for details, see table 16.4. when an external clock is input to the scifnck pin, the clock with frequency 16 times the bit rate must be input. when the scif operates on an internal clock, it can output a clock from the scifnck pin. at this time output clock frequency is 16 times the bit rate.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 563 of 950 rej09b0079-0200 data transfer operations: the scif initialization: before transmitting and receiving data , it is necessary to clear the te and re bits in scscr to 0, then initialize the scif as described below. when the transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when th e te bit is cleared to 0, sctsr is initialized. note that clearing the te and re bits to 0 does not change the contents of scfsr, scftdr, or scfrdr. the te bit should be cleared to 0 after all transmit data has been sent and the tend bit in scfsr has been set to 1. clearing to 0 can also be performed during transmission, but the data being transmitted will go to the high-impedance stat e after the clearance. before setting te to 1 again to start transmission, the tfrst bit in scfcr should first be set to 1 to reset scftdr. when an external clock is used, the clock should not be stopped during operation including initialization because its operation becomes unreliable. figure 16.3 shows a sample the scif initialization flowchart.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 564 of 950 rej09b0079-0200 clear te and re bits in scscr to 0 set tfrst and rfrst bits in scfcr to 1 set c/ a bit in scsmr to 0, and set transfer format set rtrg1, rtrg0, ttrg1, and ttrg0 bits in scfcr. clear tfrst and rfrst bits to 0 set te and re bits in scscr to 1, and set rie, tie, and reie bits set value in scbrr set cke1 and cke0 bits in scscr to b'00 (internal clock/ scifnck pin is input pin (input signal is ignored)) (leaving te, re, tie, and rie bitscleared to 0) 1. set the clock selection in scscr. be sure to clear bits rie, tie, te, and re to 0. 2. set the transfer format in scsmr. 3. write a value corresponding to the bit rate into scbrr. (not necessary if an external clock is used.) 4. wait at least one bit interval, then set the te bit or re bit in scscr to 1. also set the rie, tie, and reie bits. setting the te and re bits enables the txd and rxd pins to be used. initialization end 1-bit interval elapsed? no wait yes figure 16.3 sample the sc if initialization flowchart serial data transmission: figure 16.4 shows a sample flow chart for serial transmission. use the following procedure for serial data transmission after enabling the scif for transmission.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 565 of 950 rej09b0079-0200 read tdfe bit in scfsr read tend bit in scfsr clear port dr to 0 clear te bit in scscr to 0 specify txd pin as output port by pfc write (16 ? transmit trigger set number) bytes of transmit data to scftdr, read 1 from tdfe bit and tend flag in scfsr, then clear to 0 1. scif status check and transmit data write: read the serial status register (scfsr) and check that the tdfe flag is set to 1, then write transmit data to scftdr, read 1 from the tdfe and tend flags, then clear these flags to 0. the number of data bytes that can be written is 16 ? (transmit trigger set number). 2. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, then write data to scftdr, and then clear the tdfe bit to 0. 3. break output at the end of serial transmission: to output a break in serial transmission, clear the port data register (dr) to 0 before clearing the te bit in scscr to 0, and then specify the txd pin as an output port by the pfc. in steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in scftdr indicated by the upper 8 bits of scfdr. start of transmission end of transmission tdfe = 1? no yes all data transmitted? no yes tend = 1? no yes break output? no yes figure 16.4 sample serial transmission flowchart
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 566 of 950 rej09b0079-0200 in serial transmission, the scif operates as described below. 1. when data is written into scftdr, the scif transfers the data from scftdr to sctsr and starts transmitting. confirm that the tdfe flag in scfsr is set to 1 before writing transmit data to scftdr. the number of data bytes that can be written is at least 16 ? (transmit trigger set number). 2. when data is transferred from scftdr to sctsr and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr. when the number of transmit data bytes in scftdr falls to or below the transmit trigger number set in scfcr, the tdfe flag is set. if the tie bit in scscr is set to 1 at this time, a transmit-fifo- data-empty interrupt (txi) request is generated. the serial transmit data is sent from the txd pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit: one parity bit (even or odd parity) is output. (a format in which a parity bit is not output can also be selected.) d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the scif checks the scftdr transmit data at the timing for sending the stop bit. if data is present, the data is transferred from scftdr to sctsr, the stop bit is sent, and then serial transmission of the next frame is started. if there is no transmit data, the tend flag in scfsr is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 567 of 950 rej09b0079-0200 figure 16.5 shows an example of the operation for transmission in asynchronous mode. 01 1 1 0/1 0 1 tdfe tend parity bit parity bit serial data start bit start bit data data stop bit stop bit idle state (mark state) txi interrupt request data written to scftdr and tdfe flag read as 1 and then cleared to 0 by txi interrupt handler one frame d0 d1 d7 d0 d1 d7 0/1 txi interrupt request figure 16.5 example of transmit operation (example of 8-bit data with parity and 1 stop bit)
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 568 of 950 rej09b0079-0200 serial data reception: figures 16.6 and 16.7 show a sample flowchart for serial reception. use the following procedure for serial data r eception after enab ling the scif for reception. read er, dr, and brk flags in scfsr and orer flag in sclsr read rdf flag in scfsr read receive data from scfrdr, and clear rdf flag in scfsr to 0 clear re bit in scscr to 0 1. receive error handling and break detection: read the dr, er, and brk flags in scfsr and orer flag in sclsr to identify any error, perform the appropriate error handling, then clear the dr, er, brk, and orer flags to 0. in the case of a framing error, a break can also be detected by reading the value of the rxd pin. 2. scif status check and receive data read: read scfsr and check that rdf = 1, then read the receive data in scfrdr, read 1 from the rdf flag, and then clear the rdf flag to 0. the transition of the rdf flag from 0 to 1 can also be identified by an rxi interrupt. 3. serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of data bytes from scfrdr, read 1 from the rdf flag, and then clear the rdf flag to 0. the number of receive data bytes in scfrdr can be ascertained by reading the lower bits of scfdr. start of reception end of reception er, dr, brk, or orer = 1? yes no rdf = 1? no yes all data received? no yes error handling figure 16.6 sample seri al reception flowchart (1)
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 569 of 950 rej09b0079-0200 receive error handling break handling read receive data in scfrdr clear dr, er, and brk flags in scfsr and orer flag in sclsr to 0 1. whether a framing error or parity error has occurred in the receive data read from scfrdr can be ascertained from the fer and per bits in scfsr. 2. when a break signal is received, receive data is not transferred to scfrdr while the brk flag is set. however, note that the last data in scfrdr is h'00 and the break data in which a framing error occurred is stored. error handling end er = 1? no yes overrun error handling no yes brk = 1? no yes dr = 1? no yes orer = 1? figure 16.7 sample seri al reception flowchart (2)
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 570 of 950 rej09b0079-0200 in serial reception, the scif operates as described below. 1. the scif monitors the communication line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the scif carries out the following checks. a. stop bit check: the scif checks whether the st op bit is 1. if there are two stop bits, only the first is checked. b. the scif checks whether receive data can be transferred from scrsr to scfrdr. c. overrun error check: the scif checks that th e orer flag is cleared to 0 and an overrun error does not occur. d. break check: the scif checks that the brk fl ag is 0, indicating that the break state is not set. if all the above checks are passed, the receive data is stored in scfrdr. note: reception continues when a receive error (a framing error or parity error) occurs. 4. if the rie bit in scscr is set to 1 when the rdf flag or dr flag changes to 1, a receive- fifo-data-full interrupt (rxi) request is generated. if the rie bit or reie bit in scs cr is set to 1 when the er flag changes to 1, a receive-error interrupt (eri) request is generated. if the rie bit or reie bit in scscr is set to 1 when the brk flag or orer flag changes to 1, a break reception interrupt (bri) request is generated. figure 16.8 shows an example of the operation for reception in asynchronous mode.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 571 of 950 rej09b0079-0200 rdf fer eri interrupt request generated by receive error one frame data read and rdf flag read as 1 then cleared to 0 by rxi interrupt handler rxi interrupt request 01 1 1 0/1 0 1 parity bit parity bit serial data start bit start bit data data stop bit stop bit idle state (mark state) d0 d1 d7 d0 d1 d7 0/1 figure 16.8 example of scif receive operation (example of 8-bit data with parity and 1 stop bit) modem function: when using a modem function, transmission can be stopped and started again according to the cts input value. when the cts is set to 1 during transmission, the data enters a mark state after transmitting one frame. when cts is set to 0, the next transmit data is output starting with a start bit. cts transmission stops when cts goes high transmission starts again when cts goes low 0 d0 d1 d6 d7 0/1 0 d0 d1 d6 d7 0/1 start bit transmit data txd parity bit stop bit start bit figure 16.9 cts control operation
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 572 of 950 rej09b0079-0200 when using a modem function and the receive fifo (scfrdr) is at leas t the number of the rts output trigger, the rts signal goes high. rts rts goes high when receive data is at least number of rts output trigger 0d0d1 d6d7 0/1 start bit receive data rxd parity bit stop bit rts goes low when receive data is less than number of rts output trigger figure 16.10 rts control operation 16.4.3 serial operation in clock synchronous mode in clock synchronous mode, the scif transmits and receives data synchronizing with clock pulses. this mode is suitable for high-speed serial communication. in the scif, the transmitter and receiver are independent. therefor e, by sharing the same clock, full-duplex communication can be performed. figure 16.11 shows the general format of clock synchronous serial communication. one unit of transfer data (character or frame) serial clock serial data note: * high except in continuous transmission/reception lsb bit 0 msb * * don?t care don?t care bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 figure 16.11 data format in clock synchronous communication in clock synchronous serial communication, data on the communication line is output from one fall of the serial clock to the next. data is guar anteed valid at the rise of the serial clock. in serial communication, each char acter is output starting with th e lsb and ending with the msb. after the msb is output, the communication line remains in the state of the msb.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 573 of 950 rej09b0079-0200 in clock synchron ous mode, the scif receives da ta in synchronization with the rise of the serial clock. data transfer format: a fixed 8-bit data format is used. no parity bit is added. clock: an internal clock generated by the on-chip baud rate generator or an external synchronous clock input from the scifnck pin can be se lected, according to the setting of the c/ a bit in scsmr and bits cke1 and cke0 in scscr. for details, see table 16.4. when the scif is operated on an internal clock, synchronous clock is output from the scifnck pin. eight serial clock pulses are output in the transfer of one ch aracter, and when no transmission/reception is performed the clock is fixe d high. if an internal clock is selected when only reception is performed, clock pulse is output co ntinuously until the numb er of data bytes in the receive fifo reaches the receive trigger set number while the re bit in scscr is 1. data transfer operations: the scif initialization: before transmitting and receiving da ta, it is necessary to clear the te and re bits in scscr to 0, then initialize the scif as described below. when the mode, communication format etc., is changed, the te and re bits must be cleared to 0 before making the change using the following proc edure. when the te bit is cleared to 0, sctsr is initialized. note that the rdf, per, fer, and orer flags and contents of scfrdr are retained even if the re bit is cleared to 0.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 574 of 950 rej09b0079-0200 figure 16.12 shows a sample the scif initialization flowchart. wait start initialization keep the te and re bits cleared to 0 until initialization has been completed. set the cke1 and cke0 bits. set the transfer or receive format in scsmr. write a value corresponding to the bit rate in scbrr. (not necessary if an external clock is used.) after this setting wait for at least 1-bit interval. set the external pins. specifies the pins as rxd input in reception and txd output in transmission. set the scifnck input/output according to the cke1 and cke0 settings. set the te bit or re bit in scscr to 1. also, set the tie, rie, and reie bits. at this time, the txd, rxd, and scifnck pins can be used. in transmission, the txd pin is in the mark state. when reception in clock synchronous mode and synchronous clock output (clock master) are selected, a clock is output from the scifnck pin. 1. 2. 3. 4. 5. 6. set transmit or receive format in scsmr set tfrst and rfrst bits in scfcr to 1 and clear buffer of fifo read brk, dr, and er flags in scfsr and clear the flags by writing 0 no yes set value in scbrr clear te and re bits in scscr to 0 set te and re bits in scscr to 1 and set rie, tie, and reie bits set rtrg1, rtrg0, ttrg1, and ttrg0 bits in scfcr. clear tfrst and rfrst bits to 0. 1-bit interval elapsed? end set cke1 and cke0 bits in scscr (te, re, tie, and rie bits are cleared to 0) set external pins (scifnck, txd, rxd) figure 16.12 sample the scif initialization flowchart
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 575 of 950 rej09b0079-0200 serial data transmission: figure 16.13 shows a sample flowch art for serial transmission. use the following procedure for serial data transmi ssion after enabling the scif for transmission. no yes start transmission read tdfe bit in scfsr write transmit data in scftdr and clear tdfe and tend bits in scfsr to 0 no yes no yes read tend bit in scfsr clear te bit in scscr to 0 tdfe = 1? all data transmitted? tend = 1? end transmission initialization scif initialization: see figure 16.3, sample scif initialization flowchart. scif status check and transmit data write: read scfsr, check that the tdfe flag is set to 1, then write transmit data in scftdr and clear the tdfe flag to 0. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, then write data in scftdr and clear the tdfe flag to 0. 1. 2. 3. figure 16.13 sample serial transmission flowchart in serial transmission, the scif operates as described below. 1. when data is written into scftdr, the scif transfers the data from scftdr to scftsr and starts transmitting. confirm that the tdfe flag in scfsr is set to 1 before writing transmit data to scftdr. the number of data bytes that can be written is at least 16 ?
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 576 of 950 rej09b0079-0200 2. when data is transferred from scftdr to sctsr and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr. when the number of transmit data bytes in scftdr falls to or below the transmit trigger number set in scfcr, the tdfe flag is set. if the tie bit in scscr is set to 1 at this time, a transmit-fifo- data-empty interrupt (txi) request is generated. if and external clock is specified, the scif outputs data in synchronization with the input clock. serial transmit data is output in order from lsb to msb from the txd pin. 3. the scif checks the scftdr transmit data at the timing for sending the last bit. if data is present, the data is transferred from scftdr to sctsr, the stop bit is sent, and then serial transmission of the next frame is started. if there is no transmit data, the tend flag in scfsr is set to 1, the stop bit is sent, and then the state of the txd pin is held. 4. after serial transmission has completed, the scifnck pin is fixed to high. figure 16.14 shows an example of the scif transmit operation. serial clock serial data tdfe lsb bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 msb tend txi request 1 frame txi request txi handling routine writes data in scftdr and clears the tdfe flag to 0 figure 16.14 example of th e scif transmit operation
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 577 of 950 rej09b0079-0200 serial data reception: figures 16.15 and 16.16 show sample flowcharts for serial reception. use the following procedure for serial data r eception after enabling th e scif for reception. to change the operating mode from asynchronous mode to clock synchronous mode without initialization, be sure to confirm that the flags orer, per3 to per0, and fer3 to fer0 are cleared to 0. yes no start reception end reception no yes read rdf flag in scfsr clear re bit in scscr to 0 read orer flag in sclsr error handling read receive data from scfrdr and clear rdf flag in scfsr to 0 no yes orer = 1? rdf = 1? all data received? initialization scif initialization: see figure 16.3, sample scif initialization flowchart. receive error handling: if a receive error occurs, read the orer flag in sclsr, then after executing the necessary error handling, clear the orer flag to 0. serial reception cannot be continued while the orer flag is set to 1. scif status check and receive data read: read scfsr, check that the rdf flag is set to 1, then read receive data in scfrdr and clear the rdf flag to 0. notification that the rdf flag has changed from 0 to 1 can also be given by the rxi. serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of data bytes from scfrdr, read 1 from the rdf flag, and then clear the rdf flag to 0. the number of receive data in scfrdr can be ascertained by reading the lower bits of scfdr. however, if the dmac is activated by the rxi and the value is read from scfrdr, the rdf flag is cleared automatically. 1. 2. 3. 4. figure 16.15 sample serial reception flowchart
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 578 of 950 rej09b0079-0200 error handling clear orer flag in sclsr to 0 no yes overrun error handling orer = 1? end figure 16.16 sample serial reception flowchart in serial reception, the scif operates as described below. 1. the scif internally initializes in synchronizat ion with the synchronous clock input or output. 2. the scif stores receive data in scrsr in or der from lsb to msb. af ter reception, the scif checks whether receive data can be transmitte d from scrsr to scfrdr. if this check is passed, the scif stores the receive data in scfrdr . if an overrun error is detected by an error check, following reception can not be performed. 3. if the rdf flag is set to 1 and the rie bit in scscr is set to 1, the scif requests a receive- fifo-data-full interrupt (rxi). if the orer flag is set to 1 and the rie bit or reie bit in scscr is set to 1, the scif requests a break interrupt (bri).
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 579 of 950 rej09b0079-0200 figure 16.17 shows an example of the scif receive operation. 1 frame bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 lsb msb serial clock serial data rdf orer bri request generated by overrun error rxi handling routine reads data of scfrdr and clears rdf flag to 0 rxi request rxi request figure 16.17 example of the scif receive operation
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 580 of 950 rej09b0079-0200 simultaneous serial data transmission and reception: figure 16.18 shows a sample flowchart for simultaneous serial tran smission and reception. before performing simultaneous serial data transmission and reception according to the processes described below, specify the scif as the transmit/receive enable state.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 581 of 950 rej09b0079-0200 yes no start transmission and reception end no yes read rdf flag in scfsr clear te and re bits in scscr to 0 read orer flag in sclsr error handling read receive data in scfrdr and clear rdf flag in scfsr to 0 no yes orer = 1? rdf = 1? all data received? no yes tdfe = 1? read tdfe flag in scfsr initialization scif initialization: see figure 16.3, sample scif initialization flowchart. scif status check and receive data write: read scfsr, check that the tdfe flag is set to 1, then write transmit data in scftdr and clear the tdfe flag to 0. notification that the tdfe flag has changed from 0 to 1 can also be given by the txi. receive error handling: if a receive error occurs, read the orer flag in sclsr, then after executing the necessary error handling, clear the orer flag to 0. serial reception cannot be continued while the orer flag is set to 1. scif status check and receive data read: read scfsr, check that the rdf flag is set to 1, then read receive data from scfrdr and clear the rdf flag to 0. notification that the rdf flag has changed from 0 to 1 can also be given by the rxi. serial transmission/reception continuation procedure: to continue serial reception, before the msb of the current frame is received, read the rdf flag and scfrdr and clear the rdf flag to 0. also, check that the tdfe flag is set to 1 and data can be written before transmitting the msb of the current frame. futhermore, write data in scftdr and clear the tdfe flag to 0. 1. 2. 3. 4. 5. note: when switching from transmission or reception to simultaneous transmission and reception, clear the te and re bits to 0, then set the both bits to 1 simultaneously. write transmit data in scftdr and read tdfe flag in scfsr figure 16.18 sample serial data transmission/reception flowchart
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 582 of 950 rej09b0079-0200 16.5 scif interrupt sources and dmac the scif supports four interrupt sources?transmit-fifo-data-empty interrupt (txi), receive- error interrupt (eri), receive-fifo-data-full interrupt (rxi), and break interrupt (bri). table 16.6 shows the interrupt sources and their order of prio rity. for priorities and the relationship with non- the scif interrupts, see section 4, exception handling. the interrupt sources can be enabled or disabled by means of the tie, rie, and reie bits in scscr. a separate interrupt request is sent to the interrupt controller for each of these interrupt sources. when the txi is enabled by the tie bit, if the tdfe flag in scfsr is set to 1, a txi request and a transmit-fifo-data- empty dma transfer request are generate d. when the txi is disabled by the tie bit, if the tdfe flag is set to 1, only th e transmit-fifo-dat a-empty dma transfer request is generated. the dmac can be activated and data transfer performed on generation of the transmit- fifo-data-empty dma transfer request. when the rxi is enabled by the rie bit, if the rdf flag or dr flag in scfsr is set to 1, an rxi request and a receive-fifo-data-full dma transf er request are generated. when the rxi is disabled by the rie bit, if the rdf flag or dr flag is set to 1, only the receive-fi fo-data-full dma transfer request is generated. the dmac can be activated and data transfer performed on generation of the receive-fifo-data-full dma transf er request. the generation of the rxi and the receive-fifo-data-full dma transf er requests by setting the dr flag to 1 occurs only in asynchronous mode. when the brk flag in scfsr or the orer flag in sclsr is set to 1, a bri request is generated. when using the dmac for transmission/reception, set and enable the dmac before making the scif settings. see section 13, direct memory access controller (dmac), for details on the dmac setting procedure. also set the rxi and txi requests not to be output to the interrupt controller. if the interrupt requests are set to be generated, the interrupt requests to the interrupt controller are cleared by the dmac regardless of the interrupt handling program. when the rie bit is cleared to 0 and the reie b it is set to 1 in scscr, the eri or bri request can be generated without generating the rxi reques t. note that the txi indicates that writing the transmit data is enabled, while the rxi indicates that the receive data is in scfrdr.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 583 of 950 rej09b0079-0200 table 16.6 the scif interrupt sources interrupt source description dmac activation priority on reset release eri interrupt initiated by receive error (er) not possible high rxi interrupt initiated by receive fifo data full (rdf) or data ready (dr) * possible bri interrupt initiated by break (brk) or overrun error (orer) not possible txi interrupt initiated by transmit fifo data empty (tdfe) possible low note: * the rxi by the dr is enabled only in asynchronous mode. see section 4, exception handling, for prio rities and the relationship with non-the scif interrupts. 16.6 usage notes note the following when using the scif. scftdr writing and tdfe flag: the tdfe flag in scfsr is set when the number of transmit data bytes written in scftdr has fallen to or below the transmit trigger number set by bits ttrg1 and ttrg0 in scfcr. after the tdfe flag is set, transmit data up to the number of empty bytes in scftdr can be written, allowing efficient continuous transmission. however, if the number of data bytes written in scftdr is equal to or less than the transmit trigger number, the tdfe flag will be set to 1 agai n after being read as 1 and cleared to 0. tdfe clearing should therefore be carri ed out when scftdr contains more than the transmit trigger number of transmit data bytes. the number of transmit data bytes in scftdr can be found from bits 12 to 8 in scfdr. scfrdr reading and rdf flag: the rdf flag in scfsr is set when the number of receive data bytes in scfrdr has become equal to or great er than the receive trig ger number set by bits rtrg1 and rtrg0 in scfcr. after the rdf flag is set, receive da ta equivalent to the trigger number can be read from scfrdr, a llowing efficient co ntinuous reception. however, if the number of data bytes in scfrdr is still equal to or greater than the trigger number after a read, the rdf flag will be set to 1 again if it is cleared to 0. the rdf flag should therefore be cleared to 0 after being read as 1 after all receive data has been read. the number of receive data bytes in scfrdr can be found from bits 4 to 0 in scfdr.
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 584 of 950 rej09b0079-0200 break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the br eak state the input from the rxd pin consists of all 0s, so the fer flag is set and the parity error flag (per) may also be set. although the scif stops tr ansferring receive data to scfrdr after receiving a break, the receive operation continues. receive data sampling timi ng and receive margin in asynchronous mode: in asynchronous mode, the scif operates on a base clock with a frequency of 16 times the transfer rate. in reception, the scif synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. the timing is shown in figure 16.19. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 base clock 16 clocks 8 clocks ?7.5 clocks +7.5 clocks start bit d0 d1 receive data (rxd) synchronization sampling timing data sampling timing figure 16.19 receive data sampling timing in asynchronous mode the receive margin in asynchron ous mode can therefore be expres sed as shown in equation (1). m = 0.5 ? ? (l ? 0.5)f ? (1 + f) 100% d ? 0.5 n 1 2n ..................... (1) m: receive margin (%) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 585 of 950 rej09b0079-0200 from equation (1), if f = 0 and d = 0.5, the receive margin is 46.8 75%, as given by equation (2). when d = 0.5 and f = 0: m = (0.5 ? 1/(2 16)) 100% = 46.875% ........................................... (2) this is a theoretical value. a reasonable margin to allow in system designs is 20% to 30%. notes on dmac usage: to use an external clock source for a synchronous clock, the external clock should be input after scftdr has been updated by the dmac and then five cycles or more of a peripheral operating clock has passed. if a transmit clock is input within four cycles after scftdr has updated, erroneous operation may occur (figure 16.20). d0 d1 scifnck txd tdfe d2 d3 d4 d5 d6 d7 t note: to operate on an external clock, specify t as 4 cycles or more of a peripheral operating clock. figure 16.20 sample transfer of synchronous clock by dmac
section 16 serial communication interface with fifo (scif) rev. 2.00 dec. 07, 2005 page 586 of 950 rej09b0079-0200
section 17 serial i/o with fifo (siof) scis3f0c_000020020900 rev. 2.00 dec. 07, 2005 page 587 of 950 rej09b0079-0200 section 17 serial i/o with fifo (siof) this lsi includes a two-channel clocked synchronous serial i/o module with fifo (siof) which can be directly connected to the audio code c. the functions of the siof0 and siof1 are common. 17.1 features the features of the siof are described below. ? serial transfer sixteen-stage 32-bit fifos (transmission/reception independently) supports 8-bit data/16-bit data/16-bit stereo audio input/output msb or lsb first for data transmission/reception supports a maximum of 48-khz sampling rate synchronization by either frame synchronization pulse or left/right channel switch supports codec control data interface connectable to every a-law or -law codec linear audio chip manufactured by any company supports both master and slave modes ? serial clock an external pin input or internal clock (p _clk) can be selected as the clock source. ? interrupts following four interrupts can be requested independently. transmission interrupt reception interrupt error interrupt control interrupt ? dma transfer supports dma transfer by a transfer request for transmission/reception
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 588 of 950 rej09b0079-0200 17.1.1 block diagram figure 17.1 shows a block diagram of the siof. control register 16 32 transmit fifo (32 bits 16 stages) receive fifo (32 bits 16 stages) bus i/f p_clk rxd_sio txd_sio sck_sio siofsync 32 32 32 pp-bus s/p receive control data transmit control data 32 32 timing control eri rxi txi cci siomclk baud rate generator p/s 1/nmclk figure 17.1 block diagram of siof
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 589 of 950 rej09b0079-0200 17.2 input/output pins the pin configuration of the siof0/1 is shown in table 17.1. table 17.1 pin configuration channel name abbreviation i/o function clock input pin siomclk0 input master clock input communication clock pin sck_sio0 input/ output serial clock (common to transmission/reception) frame synchronous pin siofsync0 input/ output frame synchronous signal (common to transmission/reception) transmit data pin txd_sio0 output transmit data 0 receive data pin rxd_ sio0 input receive data clock input pin siomclk1 input master clock input communication clock pin sck_sio1 input/ output serial clock (common to transmission/reception) frame synchronous pin siofsync1 input/ output frame synchronous signal (common to transmission/reception) transmit data pin txd_sio1 output transmit data 1 receive data pin rxd_sio1 input receive data
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 590 of 950 rej09b0079-0200 17.3 register descriptions the siof has the following regist ers. for the addresses and access si ze of these registers, refer to section 24, list of registers. 1. channel 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 591 of 950 rej09b0079-0200 17.3.1 siof mode register (simdr) simdr is a register that sets the siof0/1 operating mode. simdr is initialized by a power-on reset or manual reset. bit bit name initial value r/w description 15 14 trmd1 trmd0 0 0 r/w r/w transfer mode selects transfer mode. 00: slave mode 1 01: slave mode 2 10: master mode 1 11: master mode 2 note: for the operation in each mode, see section 17.4.3, transfer data format. 13 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 12 redg 0 r/w receive data sampling edge the txd_sio signal is transmitted at the opposite edge where the rxd_sio signal is sampled (see figure 17.4). 0: rxd_sio is sampled at the falling edge of sck_sio 1: rxd_sio is sampled at the rising edge of sck_sio note: this bit is valid in master mode 1 and master mode 2.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 592 of 950 rej09b0079-0200 bit bit name initial value r/w description 11 10 9 8 fl3 fl2 fl1 fl0 0 0 0 0 r/w r/w r/w r/w frame length 00xx: slot length is 8 bits and frame length is 8 bits 0100: slot length is 8 bits and frame length is 16 bits 0101: slot length is 8 bits and frame length is 32 bits 0110: slot length is 8 bits and frame length is 64 bits 0111: slot length is 8 bits and frame length is 128 bits 10xx: slot length is 16 bits and frame length is 16 bits 1100: slot length is 16 bits and frame length is 32 bits 1101: slot length is 16 bits and frame length is 64 bits 1110: slot length is 16 bits and frame length is 128 bits 1111: slot length is 16 bits and frame length is 256 bits notes: 1. when slot length is specified as 8 bits, control data cannot be transmitted or received. 2. when lsb is first transmitted or received, control data cannot be transmitted or received. x: don't care 7 txdiz 0 r/w high-impedance output when transmission is invalid specifies high-impedance output when transmission is invalid. 0: high output (1 output) when invalid 1: high-impedance output when invalid note: invalid means when disabled, and when a slot that is not assigned as transmit data or control data is being transmitted. 6 lsbf 0 r/w lsb-first transmission/reception selects the bit order of a transmit/receive frame. 0: msb-first 1: lsb-first 5 rcim 0 r/w receive control data interrupt mode selects the set timing of the rcrdy bit in sistr. 0: sets the rcrdy bit in sistr when the contents of sircr change. 1: sets the rcrdy bit in sistr each time when sircr receives control data.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 593 of 950 rej09b0079-0200 bit bit name initial value r/w description 4 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17.3.2 serial clock select register (siscr) siscr is used to set the baud rate generator operation. siscr can be specified when the trmd1 and trmd0 bits in simdr are specified as b bit bit name initial value r/w description 15 mssel 1 r/w master clock source selection the master clock is the clock input to the baud rate generator. 0: uses the siomclk pin input signal as the master clock 1: uses pclk as the master clock 14 msimm 1 r/w master clock direct selection 0: uses the baud rate generat or output clock as the clock source 1: uses the master clock itself as the clock source 13 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 12 11 10 9 8 brps4 brps3 brps2 brps1 brps0 0 0 0 0 0 r/w r/w r/w r/w r/w baud rate generator?s prescalar setting (brps) set the master clock division ratio brps. 00000: ( 1/32) 00001: ( 1/1) 00010: ( 1/2) 11111: ( 1/31) 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 594 of 950 rej09b0079-0200 bit bit name initial value r/w description 2 1 0 brdv2 brdv1 brdv0 0 0 0 r/w r/w r/w baud rate generator?s division ratio setting (brdv) set the frequency division ratio brdv for the output stage of the baud rate generator. the final frequency division ratio of the baud rate generator is determined by brps brdv (maximum 1/1024). 000: prescalar output 1/2 001: prescalar output 1/4 010: prescalar output 1/8 011: prescalar output 1/16 100: prescalar output 1/32 note: other than above is reserved (setting prohibited). 17.3.3 serial transmit data assign register (sitdar) sitdar is used to specify the position of the tr ansmit data in a frame (slot number). sitdar is initialized by a power-on reset and software reset. bit bit name initial value r/w description 15 tdle 0 r/w transmit left channel data enable 0: disables left channel data transmission 1: enables left channel data transmission 14 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 10 9 8 tdla3 tdla2 tdla1 tdla0 0 0 0 0 r/w r/w r/w r/w transmit left channel data assigns specify the position of left-channel data in transmit frame as b 0000 to b 1110. transmit data for the left channel is specified in bits sitdl15 to sitdl0 in sitdr. note: if the tdla3 to tdla0 bits are set to b 1111, operation is not guaranteed. 7 tdre 0 r/w transmit right channel data enable 0: disables right channel data transmission 1: enables right channel data transmission
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 595 of 950 rej09b0079-0200 bit bit name initial value r/w description 6 tlrep 0 r/w transmit left channel repeat this bit setting is valid when the tdre bit is set to 1. when this bit is set to 1, settings of bits sitdr15 to sitdr0 in sitdr are ignored. 0: transmits data specified in the sitdr bit in sitdr as right channel data. 1: repeatedly transmits data s pecified in the sitdl bit in sitdr as right channel data 5 4 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 tdra3 tdra2 tdra1 tdra0 0 0 0 0 r/w r/w r/w r/w transmit right channel data assigns specify the position of right-channel data in transmit frame as b 0000 to b 1110. transmit data for the right channel is specified in bits sitdr 15 to sitdr0 in sitdr. note: if the tdra3 to tdra0 bits are set to b 1111, operation is not guaranteed. 17.3.4 serial receive data assign register (sirdar) sirdar is used to specify the po sition of the receive data in a frame. sirdar is initialized by a power-on reset or software reset. bit bit name initial value r/w description 15 rdle 0 r/w receive left channel data enable 0: disables left channel data reception 1: enables left channel data reception 14 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 596 of 950 rej09b0079-0200 bit bit name initial value r/w description 11 10 9 8 rdla3 rdla2 rdla1 rdla0 0 0 0 0 r/w r/w r/w r/w receive left channel data assigns 3 to 0 specify the position of left-channel data in a receive frame as b 0000 to b 1110. receive data for the left channel is stored in bits sirdl15 to sirdl0 in sirdr. note: if the rdla3 to rdl a0 bits are set to b 1111, operation is not guaranteed. 7 rdre 0 r/w receive right channel data enable 0: disables right channel data reception 1: enables right channel data reception 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 rdra3 rdra2 rdra1 rdra0 0 0 0 0 r/w r/w r/w r/w receive right channel data assigns 3 to 0 specify the position of right-channel data in a receive frame as b 0000 to b 1110. receive data for the right channel is stored in bits sirdr15 to sirdr0 in sirdr. note: if the rdra3 to rdra0 bits are set to b 1111, operation is not guaranteed. 17.3.5 serial control data assign register (sicdar) sicdar is used to specify the position of the co ntrol data in a frame. sicdar can be specified only when the fl3 to fl0 bits in simdr are sp ecified as 1xxx. sicdar is initialized by a power-on reset or software reset. bit bit name initial value r/w description 15 cd0e 0 r/w control channel 0 data enable 0: disables transmission and reception of control channel 0 data 1: enables transmission and reception of control channel 0 data 14 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 597 of 950 rej09b0079-0200 bit bit name initial value r/w description 11 10 9 8 cd0a3 cd0a2 cd0a1 cd0a0 0 0 0 0 r/w r/w r/w r/w control channel 0 data assigns 3 to 0 specify the position of control channel 0 data in a receive or transmit frame as b 0000 to b 1110. transmit data for the control channel 0 data is specified in bits sitc015 to sitc00 in sitcr. receive data for the control channel 0 data is stored in bits sirc015 to sirc00 in sircr. note: if the cd0a3 to cd0 a0 bits are set to b 1111, operation is not guaranteed. 7 cd1e 0 r/w control channel 1 data enable 0: disables transmission and reception of control channel 1 data 1: enables transmission and reception of control channel 1 data 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 cd1a3 cd1a2 cd1a1 cd1a0 0 0 0 0 r/w r/w r/w r/w control channel 1 data assigns 3 to 0 specify the position of control channel 1 data in a receive or transmit frame as b 0000 to b 1110. transmit data for the control channel 1 data is specified in bits sitc115 to sitc10 in sitcr. receive data for the control channel 1 data is stored in bits sirc115 to sirc10 in sircr. note: if the cd1a3 to cd1 a0 bits are set to b 1111, operation is not guaranteed.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 598 of 950 rej09b0079-0200 17.3.6 siof control register (sictr) sictr is used to set the siof operating stat e. sictr is initialized by a power-on reset or software reset. bit bit name initial value r/w description 15 scke 0 r/w serial clock output enable this bit is valid in master mode . if this bit is set to 1, the siof initializes the baud rate generator and initiates the operation. at the same time , the siof outputs the clock generated in the baud rate generator to the sck_sio pin. 0: disables the sck_sio output (outputs 0) 1: enables the sck_sio output 14 fse 0 r/w frame synchrono us signal output enable this bit is valid in master mode . if this bit is set to 1, the siof initializes the frame counter and initiates the operation. 0: disables the siofsync output (outputs 0) 1: enables the siofsync output 13 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 txe 0 r/w transmission enable this bit setting becomes valid at the start of the next frame (at the rising edge of the siofsync signal) and when valid data is stored in the transmit fifo. when the 1 setting for this bit becomes valid, the siof issues a transmission transfer request according to the setting of the tfwm bit in sifctr. when transmit data is stored in the transmit fifo, transmission of data from the txd_sio pin begins. this bit is initialized by a transmit reset. 0: disables data transmission from txd_sio (outputs 1) 1: enables data transmission from txd_sio
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 599 of 950 rej09b0079-0200 bit bit name initial value r/w description 8 rxe 0 r/w reception enable this bit setting becomes valid at the start of the next frame (at the rising edge of the siofsync signal). when the 1 setting for this bit becomes valid, the siof begins the reception of data from the rxd_sio pin. when receive data is stored in rece ive fifo, the siof issues a reception transfer request according to the setting of the rfwm bit in sifctr. this bit is initialized by a receive reset. 0: disables data reception from rxd_sio 1: enables data reception from rxd_sio 7 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 txrst 0 r/w transmission reset this bit setting becomes valid immediately. when the 1 setting for this bit becomes valid, the siof immediately sets transmit data from the txd_sio pin to 1, and initializes the transmission data register and transmission- related status register. the following are initialized. ? sitdr ? transmit fifo write/read pointer ? tcrdy, tfemp, and tdreq bits in sistr ? txe bit as the siof is cleared automat ically at the completion of reset operation, this bit is always read as 0. 0: transmission operation is not reset 1: resets transmission operation
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 600 of 950 rej09b0079-0200 bit bit name initial value r/w description 0 rxrst 0 r/w reception reset this bit setting becomes valid immediately. when the 1 setting for this bit becomes valid, the siof immediately disables reception from the rxd_sio pin, and initializes the reception data register and reception-related status register. the following are initialized. ? sirdr ? receive fifo write/read pointer ? rcrdy, rfful, and rdreq bits in sistr ? rxe bit as the siof is cleared automat ically at the completion of reset operation, this bit is always read as 0. 0: reception operation is not reset 1: resets reception operation
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 601 of 950 rej09b0079-0200 17.3.7 siof fifo control register (sifctr) sifctr is used to indicate the area available fo r the transmit/receive fifo transfer. sifctr is initialized by a power-on reset or software reset. bit bit name initial value r/w description 15 14 13 tfwm2 tfwm1 tfwm0 0 0 0 r/w r/w r/w transmit fifo watermark a transfer request to the transmit fifo is issued by the tdreq bit in sistr. the transmit fifo is always used as 16 stages of fifo regardless of these bit settings. 000: issue a transfer request when 16 stages of transmit fifo are empty. 001: reserved (setting prohibited) 010: reserved (setting prohibited) 011: reserved (setting prohibited) 100: issue a transfer request when 12 or more stages of transmit fifo are empty. 101: issue a transfer request when 8 or more stages of transmit fifo are empty. 110: issue a transfer request when 4 or more stages of transmit fifo are empty. 111: issue a transfer request when 1 or more stages of transmit fifo are empty. 12 11 10 9 8 tfua4 tfua3 tfua2 tfua1 tfua0 1 0 0 0 0 r r r r r transmit fifo usable area indicate the number of words that can be transferred by the cpu or dmac as b 00000 to b 10000.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 602 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 6 5 rfwm2 rfwm1 rfwm0 0 0 0 r/w r/w r/w receive fifo watermark a transfer request to the receive fifo is issued by the rdreq bit in sistr. the receive fifo is always used as 16 stages of fifo regardless of these bit settings. 000: issue a transfer request when 1 stage or more of receive fifo are valid. 001: reserved (setting prohibited) 010: reserved (setting prohibited) 011: reserved (setting prohibited) 100: issue a transfer request when 4 or more stages of receive fifo are valid. 101: issue a transfer request when 8 or more stages of receive fifo are valid. 110: issue a transfer request when 12 or more stages of receive fifo are valid. 111: issue a transfer request w hen 16 stages of receive fifo are valid. 4 3 2 1 0 rfua4 rfua3 rfua2 rfua1 rfua0 0 0 0 0 0 r r r r r receive fifo usable area indicate the number of words that can be transferred by the cpu or dmac as b 00000 to b 10000.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 603 of 950 rej09b0079-0200 17.3.8 siof status register (sistr) sistr shows the siof state. each of the bits of this register becomes an siof interrupt source when the corresponding bit in siier is set to 1. sistr is initialized by a power-on reset or software reset. bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 tcrdy 0 r transmit control data ready this bit indicates a state of t he siof. if sitcr is written, the siof clears this bit. this bit is valid when the txe bit in sictr is set to 1. if the issue of interrupts by this bit is enabled, the siof issues a control interrupt. if sitcr is written when this bit is cleared to 0, sitcr is over-written and the previous contents of sitcr are not out put from the txd_sio pin. 0: indicates that a write to sitcr is disabled 1: indicates that a write to sitcr is enabled note: when using this bit, see 2 in section 17.5, usage notes. 13 tfemp 0 r transmit fifo empty this bit indicates a state; if si tdr is written, the siof clears this bit. this bit is valid when the txe bit in sictr is 1. if the issue of interrupts by this bit is enabled, the siof issues a control interrupt. 0: indicates that transmit fifo is not empty 1: indicates that transmit fifo is empty 12 tdreq 0 r transmit data transfer request a transmit data transfer request is issued when the empty space in the transmit fifo exc eeds the size specified by the tfwm bit in sifctr. this bit is valid when the txe bit in sictr is 1. this bit indicates a state of the siof. if the size of empty space in the transmit fifo is less than the size specified by the tfwm bit in sifctr, the siof clears this bit. if the issue of interrupts by this bit is enabled, the siof issues a transmit interrupt. 0: no transfer request 1: transfer request
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 604 of 950 rej09b0079-0200 bit bit name initial value r/w description 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 rcrdy 0 r receive control data ready this bit indicates a state of the siof. if sircr is read, the siof clears this bit. this bit is valid when the rxe bit in sictr is set to 1. if the issue of interrupts by this bit is enabled, the siof issues a control interrupt. if sircr is written when this bit is set to 1, sircr is modified by the latest data. 0: indicates that sircr stores no valid data 1: indicates that sircr stores valid data 9 rfful 0 r receive fifo full this bit indicates a state. if sirdr is read, the siof clears this bit. this bit is valid when the rxe bit in sictr is 1. if the issue of interrupts by this bit is enabled, the siof issues a control interrupt. 0: receive fifo not full 1: receive fifo full 8 rdreq 0 r receive data transfer request a receive data transfer request is issued when the valid space in the receive fifo exc eeds the size specified by the rfwm bit in sifctr. this bit is valid when the rxe bit in sictr is 1. this bit indicates a state the siof. if the size of valid space in the receive fifo is less than the size specified by the rfwm bit in sifctr, the siof clears this bit. if the issue of interrupts by this bit is enabled, the siof issues a receive interrupt. 0: indicates that the size of valid space in the receive fifo does not exceed the size specified by the rfwm bit in sifctr. 1: indicates that the size of valid space in the receive fifo exceeds the size specified by the rfwm bit in sifctr. 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 605 of 950 rej09b0079-0200 bit bit name initial value r/w description 4 fserr 0 r/w frame synchronization error a frame synchronization error occurs when the next frame synchronization timing appears before the previous data or control data transfers have been completed. if a frame synchronization erro r occurs, the siof performs transmission or reception for slots that can be transferred. this bit is valid when the txe or rxe bit in sictr is 1. when 1 is written to this bit, the cont ents are cleared. if the issue of interrupts by this bit is enabled, the siof issues an error interrupt. 0: indicates that no frame synchronization error occurs 1: indicates that a frame synchronization error occurs 3 tfovr 0 r/w transmit fifo overrun transmit fifo overrun means that there has been an attempt to write to sitdr when the transmit fifo is full. when a transmit overrun occurs, written data is ignored. this bit is valid when the txe bit in sictr is 1. when 1 is written to this bit, the content s are cleared. if the issue of interrupts by this bit is enabled, the siof issues an error interrupt. 0: no transmit fifo overrun 1: transmit fifo overrun 2 tfudr 0 r/w transmit fifo underrun transmit fifo underrun means that loading for transmission has occurred when the transmit fifo is empty. when a transmit underrun occurs, the siof repeatedly sends the previous transmit data. this bit is valid when the txe bit in sictr is 1. when 1 is written to this bit, the content s are cleared. if the issue of interrupts by this bit is enabled, the siof issues an error interrupt. 0: no transmit fifo underrun 1: transmit fifo underrun
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 606 of 950 rej09b0079-0200 bit bit name initial value r/w description 1 rfudr 0 r/w receive fifo underrun receive fifo underrun means that reading of sirdr has occurred when the receive fifo is empty. when a receive underrun occurs, the value of data read from sirdr is not guaranteed. this bit is valid when the rxe bit in sictr is 1. when 1 is written to this bit, the content s are cleared. if the issue of interrupts by this bit is enabled, the siof issues an error interrupt. 0: no receive fifo underrun 1: receive fifo underrun 0 rfovr 0 r/w receive fifo overrun receive fifo overrun means that writing has occurred when the receive fifo is full. when a receive overrun occurs, the siof indicates the overrun, and receive data is lost. this bit is valid when the rxe bit in sictr is 1. when 1 is written to this bit, the content s are cleared. if the issue of interrupts by this bit is enabled, the siof issues an error interrupt. 0: no receive fifo overrun 1: receive fifo overrun
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 607 of 950 rej09b0079-0200 17.3.9 siof interrupt enable register (siier) siier is a used to enable the issue of siof interrup ts. when each of the bits of this register is set to 1, and the corresponding bit of the sistr is se t to 1, the siof issues an interrupt. siier is initialized by a power-on reset or software reset. bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 tcrdye 0 r/w transmit control data ready enable 0: disables interrupts due to transmit control data ready 1: enables interrupts due to transmit control data ready (control interrupt) 13 tfempe 0 r/w transmit fifo empty enable 0: disables interrupts due to transmit fifo empty 1: enables interrupts due to transmit fifo empty (control interrupt) 12 tdreqe 0 r/w transmit data transfer request enable 0: disables interrupts due to transmit data transfer requests 1: enables interrupts due to transmit data transfer requests (transmit interrupt) 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 rcrdye 0 r/w receive control data ready enable 0: disables interrupts due to receive control data ready 1: enables interrupts due to receive control data ready (control interrupt) 9 rffule 0 r/w receive fifo full enable 0: disables interrupts due to receive fifo full 1: enables interrupts due to receive fifo full (control interrupt)
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 608 of 950 rej09b0079-0200 bit bit name initial value r/w description 8 rdreqe 0 r/w receive data transfer request enable 0: disables interrupts due to re ceive data transfer requests 1: enables interrupts due to receive data transfer requests (receive interrupt) 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 fserre 0 r/w frame synchronization error enable 0: disables interrupts due to frame synchronization error 1: enables interrupts due to frame synchronization error (error interrupt) 3 tfovre 0 r/w transmit fifo overrun enable 0: disables interrupts due to transmit fifo overrun 1: enables interrupts due to transmit fifo overrun (error interrupt) 2 tfudre 0 r/w transmit fifo underrun enable 0: disables interrupts due to transmit fifo underrun 1: enables interrupts due to transmit fifo underrun (error interrupt) 1 rfudre 0 r/w receive fifo underrun enable 0: disables interrupts due to receive fifo underrun 1: enables interrupts due to receive fifo underrun (error interrupt) 0 rfovre 0 r/w receive fifo overrun enable 0: disables interrupts due to receive fifo overrun 1: enables interrupts due to receive fifo overrun (error interrupt)
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 609 of 950 rej09b0079-0200 17.3.10 serial transmit data register (sitdr) sitdr is used to specify the siof transmit data. th e setting data for this register is stored in the transmit fifo. sitdr is initialized by a power-on reset, software reset, or transmit reset. bit bit name initial value r/w description 31 to 16 sitdl15 to sitdl0 all 0 w left channel transmit data specify data to be output from the txd_sio pin as left channel data. the position of the left channel data in the transmission frame is specified by the tdla bit in sitdar. these bits are valid only when the tdle bit in sitdar is set to 1. 15 to 0 sitdr15 to sitdr0 all 0 w right channel transmit data specify data to be output from the txd_sio pin as right channel data. the position of the right channel data in the transmission frame is specified by the tdra bit in sitdar. these bits are valid only when the tdle bit and tlrep bit in sitdar are set to 1 and cleared to 0, respectively.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 610 of 950 rej09b0079-0200 17.3.11 serial receive data register (sirdr) sirdr is used to read receive da ta of the siof. sirdr stores data in the receive fifo. sirdr is initialized by a power-on reset, software reset, or receive reset. bit bit name initial value r/w description 31 to 16 sirdl15 to sirdl0 all 0 r left channel receive data store data received from the rxd_sio pin as left channel data. the position of the left channel data in a receive frame is specified by the rdla bit in sirdar. these bits are valid only when the rdle bit in sirdar is set to 1. 15 to 0 sirdr15 to sirdr0 all 0 r right channel receive data store data received from the rxd_sio pin as right channel data. the position of the right channel data in the reception frame is specified by the rdra bit in sirdar. these bits are valid only when the rdre bit in sirdar is set to 1.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 611 of 950 rej09b0079-0200 17.3.12 serial transmit co ntrol data register (sitcr) sitcr is used to specify the siof transmit cont rol data. sitcr can be specified only when the fl3 to el0 bits in simdr are specified as 1x xx. sitcr is initialized by a power-on reset, software reset, or transmit reset. bit bit name initial value r/w description 31 to 16 sitc015 to sitc00 all 0 w control channel 0 transmit data specify data to be output from the txd_sio pin as control channel 0 transmit data. the position of the control channel 0 data in the transmission or reception frame is specified by the cd0a bit in sicdar. these bits are valid only when the cd0e bit in sicdar is set to 1. 15 to 0 sitc115 to sitc10 all 0 w control channel 1 transmit data specify data to be output from the txd_sio pin as control channel 1 transmit data. the position of the control channel 1 data in the transmission or reception frame is specified by the cd1a bit in sicdar. these bits are valid only when the cd1e bit in sicdar is set to 1.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 612 of 950 rej09b0079-0200 17.3.13 serial receive cont rol data register (sircr) sircr is used to store the siof receive control data. sircr can be specified only when the fl3 to fl0 bits in simdr are specified as 1xxx. sircr is initialized by a power-on reset, software reset, or receive reset. bit bit name initial value r/w description 31 to 16 sirc015 to sirc00 all 0 r control channel 0 receive data store data received from t he rxd_sio pin as control channel 0 receive data. t he position of the control channel 0 data in the transmission or reception frame is specified by the cd0a bit in sicdar. these bits are valid only when the cd0e bit in sicdar is set to 1. 15 to 0 sirc115 to sirc10 all 0 r control channel 1 receive data store data received from t he rxd_sio pin as control channel 1 receive data. t he position of the control channel 1 data in the transmission or reception frame is specified by the cd1a bit in sicdar. these bits are valid only when the cd1e bit in sicdar is set to 1.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 613 of 950 rej09b0079-0200 17.4 operation 17.4.1 serial clocks master/slave modes: the following modes are available as the siof clock mode. ? ? 1/2 to 1/1024mclk master oe brg siomclk p_clk sck_sio e timing control figure 17.2 serial clock supply
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 614 of 950 rej09b0079-0200 table 17.2 shows an example of serial clock frequency. table 17.2 siof serial clock frequency sampling rate frame length 8 khz 44.1 khz 48 khz 96 khz 32 bits 256 khz 1.4112 mhz 1.536 mhz 3.072 mhz 64 bits 512 khz 2.8224 mhz 3.072 mhz ? 128 bits 1.024 mhz 5.6648 mhz 6.144 mhz ? 256 bits 2.048 mhz 11.2896 mhz 12.288 mhz ? 17.4.2 serial timing siofsync: the siofsync is a frame synchronous sign al. depending on the transfer mode, it has the following two functions. ? ?
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 615 of 950 rej09b0079-0200 (a) synchronous pulse 1 frame first bit data (msb) 1 frame 1/2 frame length no delay 1-bit delay 1/2 frame length (b) l/r sck_sio siofsync txd_sio rxd_sio sck_sio siofsync txd_sio rxd_sio first bit of left channel data (msb) first bit of right channel data (msb) figure 17.3 serial data synchronization timing transmit/receive timing: the txd_sio transmission timing and rxd_sio reception timing relative to the sck_sio signal can be set as the sampling timing in the following two ways. the transmit/receive timing is set using the redg bit in simd r. in slave mode 1 and slave mode 2, only falling-edge sampling is available. ? ?
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 616 of 950 rej09b0079-0200 sck_sio siofsync txd_sio rxd_sio sck_sio siofsync txd_sio rxd_sio (a) falling-edge sampling (a) rising-edge sampling reception timing transmission timing reception timing transmission timing figure 17.4 siof transmit/receive timing 17.4.3 transfer data format the siof performs the following transfer. ? ? transfer mode siofsync bit delay control data slave mode 1 synchronous pulse one bit slot position slave mode 2 synchronous pulse one bit secondary fs master mode 1 synchronous pu lse one bit slot position master mode 2 l/r no not supported frame length: the length of the frame to be transferred by the siof is specified by the fl3 to fl0 bits in simdr. table 17.4 shows the relationship between the settings of the fl3 to fl0 bits and frame length.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 617 of 950 rej09b0079-0200 table 17.4 frame length fl3 to fl0 slot length number of bits in a frame transfer data 00xx 8 8 8-bit monaural data 0100 8 16 8-bit monaural data 0101 8 32 8-bit monaural data 0110 8 64 8-bit monaural data 0111 8 128 8-bit monaural data 10xx 16 16 16-bit monaural data 1100 16 32 16-bit monaural/stereo data 1101 16 64 16-bit monaural/stereo data 1110 16 128 16-bit monaural/stereo data 1111 16 256 16-bit monaural/stereo data [legend] x: don't care. slot position: the siof can specify the pos ition of transmit data, receive data, and control data (common to transmission and reception) by slot numbers. the slot nu mber of each data is specified by the following registers. ? ? ? ? ?
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 618 of 950 rej09b0079-0200 figure 17.5 shows the transmit/receive data and the sitdr and si rdr bit alignment. 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 lch.data rch.data (a) 16-bit stereo data data data data (b) 16-bit monaural data (c) 8-bit monaural data (d) 16-bit stereo data (left and right same audio output) data figure 17.5 transmit/receive data bit alignment note: in the figure, only the sh aded areas are transmitted or received as valid data. data in unshaded areas is not tr ansmitted or received. monaural or stereo can be specified for transmit data by the tdle bit and tdre bit in sitdar. monaural or stereo can be specified for receive data by the rdle bit and rdre bit in sirdar. to achieve left and right same audio output while stereo is specified for the transmit data, specify the tlrep bit in sitdar. tables 17.5 and 17.6 show the audio mode specification for transmit data and that for receive data, respectively. to execute 8-bit monaural transmission or reception, use the left channel.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 619 of 950 rej09b0079-0200 table 17.5 audio mode specifi cation for transmit data bit mode tdle tdre tlrep monaural 1 0 x stereo 1 1 0 left and right same audio output 1 1 1 note: x: don't care table 17.6 audio mode speci fication for receive data bit mode rdle rdre monaural 1 0 stereo 1 1 note: left and right same audio mode is not supported in receive data. control data: control data is written to or read from by the following registers. ? ? 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 (a) control data: one channel (b) control data: two channel control data (channel 0) control data (channel 0) control data (channel 1) figure 17.6 control data bit alignment the number of channels in control data is speci fied by cd0e and cd1e bits in sicdar. table 17.7 shows the relationship between the number of channels in control data and bit settings. to use only one channel in control data, use channel 0.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 620 of 950 rej09b0079-0200 table 17.7 setting for number of control data channels bit number of channels cd0e cd1e 1 1 0 2 1 1 17.4.5 control data interface control data performs control command output to the codec and status input from the codec. the siof supports the following tw o control data interface methods. ? ? sck_sio rxd_sio txd_sio siofsync lch.data rch.data setting: trmd = 00 or 10, tdle = 1, rdle = 1, cd0e = 1, redg = 0, tdla3 to tdla0 = 0000, rdla3 to rdla0 = 0000, cd0a3 to cd0a0 = 0001, fl = 1110 (frame length: 128 bits), tdre = 1, rdre = 1, cd1e = 1, tdra3 to tdra0 = 0010, rdra3 to rdra0 = 0010, cd1a3 to cd1a0 = 0011 control channel 0 control channel 0 1 frame slot no.0 slot no.1 slot no.2 slot no.3 figure 17.7 control data interface (slot position)
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 621 of 950 rej09b0079-0200 control by secondary fs (slave mode 2): the codec normally outputs siofsync as synchronization pulse (fs). in this method, th e codec outputs the secondary fs specific to the control data transfer after 1/2 frame time has been passed (not the normal fs output timing) to transmit or receive control data. this method is valid for siof slave mode. the following summarizes the control data inte rface procedure by secondary fs. ? ? ? ? sck_sio rxd_sio txd_sio siofsync lch.data setting: trmd = 01, tdle = 1, rdle = 1, cd0e = 1, redg = 0, tdla3 to tdla0 = 0000, rdla3 to rdla0 = 0000, cd0a3 to cd0a0 = 0000, fl = 1110 (frame length: 128 bits), tdre = 0, rdre =0, cd1e = 0, tdra3 to tdra0 = 0000, rdra3 to rdra0 = 0000, cd1a3 to cd1a0 = 0000 lsb = 1 (secondary fs request) 1 frame 1/2 frame 1/2 frame normal fs normal fs secondary fs control channel 0 slot no.0 slot no.0 figure 17.8 control data interface (secondary fs) 17.4.6 fifo overview: the transmit and receive fi fos of the siof have the following features. ? ? ?
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 622 of 950 rej09b0079-0200 ? ? tfwm2 to tfwm0 number of requested stages transmit request used areas 000 1 empty area is 16 stages 100 4 empty area is 12 stages or more 101 8 empty area is 8 stages or more 110 12 empty area is 4 stages or more smallest 111 16 empty area is 1 stage or more largest table 17.9 conditions to issue receive request rfwm2 to rfwm0 number of requested stages receive request used areas 000 1 valid data is 1 stage or more 100 4 valid data is 4 stages or more 101 8 valid data is 8 stages or more 110 12 valid data is 12 stages or more smallest 111 16 valid data is 16 stages largest the number of stages of the fifo is always sixteen even if the data area or empty area exceeds the above stage number. accordingly, an overrun error or underrun error occurs if data area or empty area exceeds sixteen fifo stages. fifo transmissi on or reception reques t is cancelled when the above condition is not satisfied even if the fifo is not empty or full. number of fifos: the number of fifo stages used in transmission and reception is indicated by the following register. ?
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 623 of 950 rej09b0079-0200 ?
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 624 of 950 rej09b0079-0200 start no ye s no ye s end no. 1 2 3 4 5 6 7 8 9 set simdr, siscr, sitdar, sirdar, sicdar, and sifctr set scke bit in sictr to 1 start sck_sio clock transmission set fse bit in sictr to 1 set txe bit in sictr to 1 tdreq=1? set sitdr output sitdr contents from txd_sio synchronously with siofsync transfer ended? clear txe bit in sictr to 0 set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and the upper limit value of fifo request set operation start for baud rate generator set the start for frame synchronous signal transmit frame synchronous signal submit transmission request set to enable transmission set transmit data set to disable transmission output serial clock transmit end transmission time chart siof settings siof operation figure 17.9 example of transmission operation in master mode reception in master mode: figure 17.10 shows an example of settings and operation for master mode reception.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 625 of 950 rej09b0079-0200 start no ye s no ye s end no. 1 2 3 4 5 6 7 8 9 set simdr, siscr, sitdar, sirdar, sicdar, and sifctr set scke bit in sictr to 1 start sck_sio clock transmission set fse bit in sictr to 1 set rxe bit in sictr to 1 rdreq=1? receive ended? clear rxe bit in sictr to 0 set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and the upper limit value of fifo request set operation start for baud rate generator set the start for frame synchronous signal transmit frame synchronous signal set to enable reception transmit serial clock time chart siof settings siof operation submit reception request according to the receive fifo threshold value reception end reception read receive data set to disable reception read sirdr store receive data from rxd_sio in sirdr synchronously with siofsync figure 17.10 example of recepti on operation in master mode transmission in slave mode: figure 17.11 shows an example of settings and oper ation for slave mode transmission.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 626 of 950 rej09b0079-0200 start no ye s no ye s end no. 1 2 3 4 5 6 set simdr, siscr, sitdar, sirdar, sicdar, and sifctr set txe bit in sictr to 1 tdreq=1? set sitdr output sitdr contents from txd_sio synchronously with siofsync transfer ended? clear txe bit in sictr to 0 set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and the upper limit value of fifo request set transmit data set to disable transmission submit transmission request to disable transmission when frame synchronous signal is transmitted transmit end transmission time chart siof settings siof operation set to enable transmission figure 17.11 example of transmission operation in slave mode reception in slave mode: figure 17.12 shows an example of settings and operation for slave mode reception.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 627 of 950 rej09b0079-0200 start no ye s no ye s end no. 1 2 3 4 5 6 set simdr, siscr, sitdar, sirdar, sicdar, and sifctr set rxe bit in sictr register to 1 rdreq=1? transfer ended? clear rxe bit in sictr to 0 set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and the upper limit value of fifo request time chart siof settings siof operation submit reception request according to the limit value of receive fifo reception end reception read receive data set to disable reception read sirdr store receive data from rxd_sio in sirdr synchronously with siofsync set to enable reception enable reception when the frame synchronous signal is input figure 17.12 example of recep tion operation in slave mode transmission/reception reset: the siof can separately reset the transmission and reception units by setting the following bits to 1. ? ?
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 628 of 950 rej09b0079-0200 table 17.10 shows the details of initializati on upon transmission or reception reset. table 17.10 transmission and reception reset type objects initialized transmission reset sitdr transmit fifo write pointer, transmit fifo read pointer tcrdy bit, tfemp bit, tdreq bit in sistr txe bit in sictr reception reset sirdr receive fifo write pointer, receive fifo read pointer rcrdy bit, rfful bit, rdreq bit in sistr rxe bit in sictr module stop: in the module stop state, the siof stops transmit/receive operatio n with contents of all registers retained. if tran smit/receive operation is not perfor med immediately after the module stop state is cleared, issue a transmit/receive reset. 17.4.8 interrupts the siof has four types of interrupts listed below. this classification is reflected to the irr7 (siof0) and irr8 (siof1) of the interrupt controller (intc). ? ? ? ?
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 629 of 950 rej09b0079-0200 table 17.11 siof interrupt sources no. classification bit name function name description 1 transmission (txi) tdreq transmit data transfer request the number of transmit fifo data is equal to or less than the specified value by transmit operation. 2 reception (rxi) rdreq receive data transfer request the receive fifo stores data of specified value or more. 3 tcrdy transmit control data ready the transmit control data register is ready to be written. 4 rcrdy receive control data ready the receive control data register stores valid data. 5 tfemp transmit fifo empty the transmit fifo is empty. 6 control (cci) rfful receive fifo full the receive fifo is full. 7 tfudr transmit fifo underrun serial data transmission timing has arrived while the transmit fifo is empty. 8 tfovr transmit fifo overrun write to the transmit fifo is performed while the transmit fifo is full. 9 rfovr receive fifo overrun serial data is received while the receive fifo is full. 10 rfudr receive fifo underrun the receive fifo is read while the receive fifo is empty. 11 error (eri) fserr frame synchronization error a synchronous signal is input before the specified bit time has been passed (in slave mode). whether an interrupt is issued or not as the result of an interrupt source is determined by the siier settings. if an interrupt source is set to 1, and the corresponding bit in siier is set to 1, the siof issues each interrupt. transmit/receive interrupt flag: transmit and receive interrupt s are sent to the intc or dmac by this interrupt flag based on the values of bits tdreq and rdreq in sistr. table17.12 shows the setting condition of the transmit/receive interrupt flag.
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 630 of 950 rej09b0079-0200 table 17.12 setting condition of transmit/receive in terrupt flag setting condition reset condition transmit interrupt flag tdreq bit in sistr is set to 1 tdreq bit in sistr is cleared to 0 acknowledge from dmac receive interrupt flag rdreq bit in sistr is set to 1 rdreq bit in sistr is cleared to 0 acknowledge from dmac processing when errors occur: on occurrence of each of the erro rs indicated as a status in sistr, the siof performs the following operations. ? ? ? ? ?
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 631 of 950 rej09b0079-0200 sck_sio rxd_sio txd_sio siofsync lch.data slot no.0 trmd = 00or10, tdle = 1, rdle = 1, cd0e = 0, redg = 0, tdla3 to tdla0 = 0000, rdla3 to rdla0 = 0000, cd0a3 to cd0a0 = 0000, fl = 0000 (frame legth: 8 bits) tdre = 0, rdre = 0, cd1e = 0, tdra3 to tdra0 = 0000, rdra3 to rdra0 = 0000, cd1a3 to cd1a0 = 0000 setting: 1 frame 1-bit delay figure 17.13 transmission and reception timings (8-bit monaural data (1)) 8-bit monaural data (2): synchronous pulse method, falling edge sampling, slot no.0 used for transmit and receive data, frame length = 16 bits sck_sio rxd_sio txd_sio siofsync lch.data trmd = 00or10, tdle = 1, rdle = 1, cd0e = 0, redg = 0, tdla3 to tdla0 = 0000, rdla3 to rdla0 = 0000, cd0a3 to cd0a0 = 0000, fl = 0100 (frame length: 16 bits) tdre = 0, rdre = 0, cd1e = 0, tdra3 to tdra0 = 0000, rdra3 to rdra0 = 0000, cd1a3 to cd1a0 = 0000 slot no.0 slot no.1 setting: 1 frame 1-bit delay figure 17.14 transmission and reception timings (8-bit monaural data (2)) 16-bit monaural data (1): synchronous pulse method, falling edge sampling, slot no.0 used for transmit and receive data, frame length = 64 bits
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 632 of 950 rej09b0079-0200 sck_sio rxd_sio txd_sio siofsync lch.data trmd = 00 or 10, tdle = 1, rdle = 1, cd0e = 0, redg = 0, tdla3 to tdla0 = 0000, rdla3 to rdla0 = 0000, cd0a3 to cd0a0 = 0000, fl = 1101 (frame length: 64 bits) tdre = 0, rdre = 0, cd1e = 0, tdra3 to tdra0 = 0000, rdra3 to rdra0 = 0000, cd1a3 to cd1a0 = 0000 slot no.0 slot no.1 slot no.2 slot no.3 setting: 1 frame no bit delay figure 17.15 transmission and reception timings (16-bit monaural data (1)) 16-bit stereo data (1): l/r method, rising edge sampling, slot no.0 used for left channel data, slot no.1 used for right channel data, frame length = 32 bits sck_sio rxd_sio txd_sio siofsync lch.data trmd = 11, tdle = 1, rdle = 1, cd0e = 0, redg = 1, tdla3 to tdla0 = 0000, rdla3 to rdla0 = 0000, cd0a3 to cd0a0 = 0000, fl = 1100 (frame length: 32 bits) tdre = 1, rdre = 1, cd1e = 0, tdra3 to tdra0 = 0001, rdra3 to rdra0 = 0001, cd1a3 to cd1a0 = 0000 rch.data slot no.0 slot no.1 setting: 1 frame no bit delay figure 17.16 transmission and reception timings (16-bit stereo data (1)) 16-bit stereo data (2): l/r method, rising edge sampling, slot no.0 used for left channel transmit data, slot no.1 used for left channel receive data , slot no.2 used for righ t channel transmit data, slot no.3 used for right channel r eceive data, frame length = 64 bits
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 633 of 950 rej09b0079-0200 sck_sio rxd_sio txd_sio siofsync trmd = 01, tdle = 1, rdle = 1, cd0e = 0, redg = 1, tdla3 to tdla0 = 0000, rdla3 to rdla0 = 0001, cd0a3 to cd0a0 = 0000, fl = 1101 (frame length: 64 bits), tdre = 1, rdre = 1, cd1e = 0, tdra3 to tdra0 = 0010, rdra3 to rdra0 = 0011, cd1a3 to cd1a0 = 0000 lch.data rch.data lch.data rch.data slot no.0 slot no.1 slot no.2 slot no.3 setting: 1 frame no bit delay figure 17.17 transmission and reception timings (16-bit stereo data (2)) 16-bit stereo data (3): synchronous pulse method, falling edge sampling, slot no.0 used for left channel data, slot no.2 used for right channel data, slot no.1 used for control channel 0 data, slot no.3 used for control channel 1 data, frame length = 128 bits sck_sio rxd_sio txd_sio siofsync trmd = 00 or 10, tdle = 1, rdle = 1, cd0e = 1, redg = 0, tdla3 to tdla0 = 0000, rdla3 to rdla0 = 0000, cd0a3 to cd0a0 = 0001, fl = 1110 (frame length: 128 bits), tdre = 1, rdre = 1, cd1e = 1, tdra3 to tdra0 = 0010, rdra3 to rdra0 = 0010, cd1a3 to cd1a0 = 0011 lch.data rch.data control ch.1 slot no.0 slot no.1 slot no.2 slot no.3 slot no.4 slot no.5 slot no.6 slot no.7 setting: 1 frame 1 bit delay control ch.0 figure 17.18 transmission and reception timings (16-bit stereo data (3)) 16-bit monaural data (2): synchronous pulse method, falling edge sampling, request for secondary fs, slot no.0 used for left channel data, slot no.0 used for control channel 0 data, frame length = 128 bits
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 634 of 950 rej09b0079-0200 1 frame sck_sio (a) when control channel is not transferred (b) when control channel is transferred siofsync txd_sio rxd_sio 1bit delay lch.data slot no.0 slot no.1 slot no.2 slot no.3 slot no.4 slot no.5 slot no.6 slot no.7 lsb = 0 (secoundary fs request) 1 frame 1/2 frame setting: lsb = 1 (secoundary fs request) trmd = 01 redg = 0, tdle = 1, tdla3 to tdla0 = 0000, rdle = 1, rdla3 to rdla0 = 0000, cd0e = 1, cd0a3 to cd0a0 = 0000, fl = 1110 (frame length: 128 bits), tdre = 0, tdra3 to tdra0 = 0000, rdre = 0, rdra3 to rdra0 = 0000, cd1e = 0, cd1a3 to cd1a0 = 0000 sck_sio siofsync txd_sio rxd_sio 1/2 frame normal fs normal fs secondary fs lch.data control channel 0 slot no.0 slot no.1 slot no.2 slot no.3 slot no.0 slot no.1 slot no.2 slot no.3 1bit delay figure 17.19 transmission and reception timings (16-bit monaural data (2))
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 635 of 950 rej09b0079-0200 17.5 usage notes note the following when using the siof. 1. using the transmit function in slave mode if transmission is enabled when data has already been written to the transmit fifo, one or two of the first data bytes may be lost. therefore, data should not be written to the transmit fifo before enabling transmission. 2. using control data transmission/reception cons ecutively on control data interface (secondary fs position) the tcrdy value may become 1 before transmit control data is sent, and if the next control data is written to the control data register at this point, the control data waiting to be sent will be overwritten and erased. at this time, also, the control sequence is di srupted and the siof swit ches around the primary fs and secondary fs, with the result that transm ission/reception of data and control data can no longer be performed normally. the control data register should therefore be written to after transmit control data has been sent. example: check rcrdy, and write to the contro l data register when rcrdy is 1. after transmit control data has been written to, it is essential to read the receive control register (sircr) and clear rcrdy. 3. dma transfer do not use 16-byte dma transfer. (see section 13.4.4, dma transfer types.) 4. access from the cpu when performing access from the cpu, do not access the siof's transmit/receive fifo consecutively, but instead insert an access to somewhere else between siof transmit/receive fifo accesses. 5. transmit/receive fifo underflow if the transmit/receive fifo unde rflows during a tran smit/receive operation, control of the siof's transmit/receive fifo ma y fail and data may be lost. to prevent this, either set a watermark so that an underflow does not occur, or execute a transmit reset (txrst) or receive reset (rxrst) when an empty interrupt is generated. 6. transmit/receive reset execution when using the siof again after a transmit/r eceive operation ends, or after erroneous operation occurs, first execute a transmit re set (txrst) or receive reset (rxrst).
section 17 serial i/o with fifo (siof) rev. 2.00 dec. 07, 2005 page 636 of 950 rej09b0079-0200
section 18 ethernet controller (etherc) isfeth01b_000020020900 rev. 2.00 dec. 07, 2005 page 637 of 950 rej09b0079-0200 section 18 ethernet controller (etherc) this lsi has an on-chip ethernet controller (etherc) conforming to the ethernet or the ieee802.3 mac (media access control) layer standard. connecting a physical-l ayer lsi (phy-lsi) complying with this standard enables the ethernet controller (etherc) to perform transmission and reception of ethernet/ieee802.3 frames. the lsi has two mac layer interface ports (hereafter referred to as port 0 and port 1), both of which can be made to perform transmission and reception independently. this ethernet controller also has an on-chip tsu (transfer switching unit) which controls transferring, allowing mu tual transfer of data between mac layer controllers of ports 0 and 1. this tsu has a 32-entry cam (content addressable memory) and two external cam interface input pins for de termining whether to receive or transf er packets input to both ethernet controllers. the tsu also has a tota l 6-kbyte transfer fifo for retain ing packets to be transferred, allowing allocation of transfer fifo capacity to be set freely for the transfer conditions of port 0 to 1 and port 1 to 0. the ethernet controller is connected to the ethernet direct memory access controller (e-dmac) for ethernet controller inside the lsi, and carries out high-speed data transfer to and from the memory. figure 18.1 shows a configuration of the etherc. 18.1 features ? transmission and reception of ethernet/ieee802.3 frames ? supports 10/100 m bps receive/transfer ? supports full-duplex and half-duplex modes ? conforms to ieee 802.3u standard mii (media independent interface) ? magic packet detection and wake-on-lan (wol) signal output ? ethernet frame relay function by the tsu ? qtag addition and deletion functions conforming to ieee802.1q specifications (when frame relay is performed by the tsu) ? mac address filtering function by the multicast (group) address ? ethernet frame receive and transfer control functions by the cam (content addressable memory) interface signal s input externally
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 638 of 950 rej09b0079-0200 tsu mac-0 (port 0) receive controller command status interface transmit controller receive controller command status interface transmit controller mac-1 (port 1) etherc phy-0 cam control tsu fifo control tsu fifo (0 to 1) tsu fifo (1 to 0) address storage register (32 entries 48 bits) mii phy-1 mii e-dmac0 e-dmac1 figure 18.1 config uration of etherc
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 639 of 950 rej09b0079-0200 18.2 input/output pins table 18.1 lists the pin configuration of the etherc. table 18.1 pin configuration name port abbreviation i/o function transmit clock 0 tx-clk0 * 1 i tx-en, etxd3 to etxd0, tx-er timing reference signal receive clock 0 rx-clk0 * 1 i rx-dv, erxd3 to erxd0, rx-er timing reference signal transmit enable 0 tx-en0 * 1 o indicates that transmit data is ready on etxd3 to etxd0 transmit data 0 etxd03 to etxd00 * 1 o 4-bit transmit data transmit error 0 tx-er0 * 1 o notifies phy_lsi of error during transmission receive data valid 0 rx-dv0 * 1 i indicates that valid receive data is on erxd3 to erxd0 receive data 0 erxd03 to erxd00 * 1 i 4-bit receive data receive error 0 rx-er0 * 1 i identifies error st ate occurred during data reception carrier detection 0 crs0 * 1 i carrier detection signal collision detection 0 col0 * 1 i collision detection signal management data clock 0 mdc0 * 1 o reference clock signal for information transfer via mdio management data i/o 0 mdio0 * 1 i/o bidirectional signal for exchange of management information between this lsi and phy link status 0 lnksta0 i inputs link status from phy general-purpose external output 0 exout0 o signal indicating value of register-bit (ecmr0-elb) wake-on-lan 0 wol0 o signal indicating reception of magic packet transmit clock 1 tx-clk1 * 1 i tx-en, etxd3 to etxd0, tx-er timing reference signal receive clock 1 rx-clk1 * 1 i rx-dv, erxd3 to erxd0, rx-er timing reference signal
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 640 of 950 rej09b0079-0200 name port abbreviation i/o function transmit enable 1 tx-en1 * 1 o indicates that transmit data is ready on etxd3 to etxd0 transmit data 1 etxd13 to etxd10 * 1 o 4-bit transmit data transmit error 1 tx-er1 * 1 o notifies phy-lsi of error during transmission receive data valid 1 rx-dv1 * 1 i indicates that valid receive data is on erxd3 to erxd0 receive data 1 erxd13 to erxd10 * 1 i 4-bit receive data receive error 1 rx-er1 * 1 i identifies error st ate occurred during data reception carrier detection 1 crs1 * 1 i carrier detection signal collision detection 1 col1 * 1 i collision detection signal management data clock 1 mdc1 * 1 o reference clock signal for information transfer via mdio management data i/o 1 mdio1 * 1 i/o bidirectional signal for exchange of management information between this lsi and phy link status 1 lknsta1 i inputs link status from phy general-purpose external output 1 exout1 o signal indicating value of register-bit (ecmr1-elb) wake-on-lan 1 wol1 o signal indicating reception of magic packet cam input 0 ? camsen0 * 2 i cam interface signal input 0 cam input 1 ? camsen1 * 2 i cam interface signal input 1 bus release request ? arbusy * 3 o signal indicating bus release request when the threshold value set for the data volume in the receive fifo has been exceeded notes: 1. mii signal conforming to ieee802.3u 2. the cam input signal function is set by the camsel03 to camsel00 and camsel13 to camsel10 in the tsu_fwslc register. 3. refer to section 19, ethernet controll er direct memory access controller (e-dmac) and section 19.2.18, overflow alert fifo threshold register (fcftr).
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 641 of 950 rej09b0079-0200 18.3 register descriptions the etherc has the following registers. the last number of the abbreviation of the mac layer interface control register corresponds to the numb er of the two mac layer interfaces (mac-0 or mac-1). some number s have been omitted in the text. for details on addresses and access sizes of registers, see section 24, list of registers. reset register: ? software reset register (arstr) mac layer interface control registers: port 0 ? etherc mode register (ecmr0) ? etherc status register (ecsr0) ? etherc interrupt permission register (ecsipr0) ? phy interface regi ster (pir0) ? mac address high register (mahr0) ? mac address low register (malr0) ? receive frame length register (rflr0) ? phy status register (psr0) ? transmit retry over counter register (trocr0) ? delayed collision detect counter register (cdcr0) ? lost carrier counter register (lccr0) ? carrier not detect coun ter register (cndcr0) ? crc error frame receive counter register (cefcr0) ? frame receive error coun ter register (frecr0) ? too-short frame receive counter register (tsfrcr0) ? too-long frame receive counter register (tlfrcr0) ? residual-bit frame receive counter register (rfcr0) ? multicast address frame receive counter register (mafcr0) ? ipg register (ipgr0)
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 642 of 950 rej09b0079-0200 port 1 ? etherc mode register (ecmr1) ? etherc status register (ecsr1) ? etherc interrupt permission register (ecsipr1) ? phy interface regi ster (pir1) ? mac address high register (mahr1) ? mac address low register (malr1) ? receive frame length register (rflr1) ? phy status register (psr1) ? transmit retry over counter register (trocr1) ? delayed collision detect counter register (cdcr1) ? lost carrier counter register (lccr1) ? carrier not detect coun ter register (cndcr1) ? crc error frame receive counter register (cefcr1) ? frame receive error coun ter register (frecr1) ? too-short frame receive counter register (tsfrcr1) ? too-long frame receive counter register (tlfrcr1) ? residual-bit frame receive counter register (rfcr1) ? multicast address frame receive counter register (mafcr1) ? ipg register (ipgr1) tsu control registers: ? tsu counter reset register (tsu_ctrst) ? relay enable register (port 0 to 1) (tsu_fwen0) ? relay enable register (port 1 to 0) (tsu_fwen1) ? relay fifo size select register (tsu_fcm) ? relay fifo overflow alert set register (port 0) (tsu_bsysl0) ? relay fifo overflow alert set register (port 1) (tsu_bsysl1) ? transmit/relay priority control mode register (port 0) (tsu_prisl0) ? transmit/relay priority control mode register (port 1) (tsu_prisl1) ? receive/relay function set regist er (port 0 to 1) (tsu_fwsl0) ? receive/relay function set regist er (port 1 to 0) (tsu_fwsl1) ? relay function set register (common) (tsu_fwslc) ? qtag addition/deletion set register (port 0 to 1) (tsu_qtagm0) ? qtag addition/deletion set register (port 1 to 0) (tsu_qtagm1)
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 643 of 950 rej09b0079-0200 ? relay status register (tsu_fwsr) ? relay status interrupt mask register (tsu_fwinmk) ? added qtag value set register (port 0 to 1) (tsu_adqt0) ? added qtag value set register (port 1 to 0) (tsu_adqt1) ? cam entry table busy register (tsu_adsbsy) ? cam entry table enable register (tsu_ten) ? cam entry table post1 to post4 registers (tsu_post1 to tsu_post4) ? cam entry table 0 to 31 h registers (tsu_adrh0 to tsu_adrh31) ? cam entry table 0 to 31 l registers (tsu_adrl0 to tsu_adrl31) ? transmit frame counter register (port 0) (normal transmission only) (txnlcr0) ? transmit frame counter register (port 0) (normal and error transmission) (txalcr0) ? receive frame counter register (port 0) (normal reception only) (rxnlcr0) ? receive frame counter register (port 0) (normal and error reception) (rxalcr0) ? relay frame counter register (port 1 to 0) (normal relay only) (fwnlcr0) ? relay frame counter register (port 1 to 0) (normal and error relay) (fwalcr0) ? transmit frame counter register (port 1) (normal transmission only) (txnlcr1) ? transmit frame counter register (port 1) (normal and error transmission) (txalcr1) ? receive frame counter register (port 1) (normal reception only) (rxnlcr1) ? receive frame counter register (port 1) (normal and error reception) (rxalcr1) ? relay frame counter register (port 0 to 1) (normal relay only) (fwnlcr1) ? relay frame counter register (port 0 to 1) (normal and error relay) (fwalcr1)
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 644 of 950 rej09b0079-0200 18.3.1 software reset register (arstr) arstr resets all modules (etherc and e-dmac) related to the ethernet. by writing 1 to the arst bit in arstr, a software reset is issued to all modules related to the ethernet (for 64 cycles at external bus clock b ). the arst bit is always read as 0. while a software reset is issued, register access to all modules relate d to the ethernet is prohibited. bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 arst 0 r/w software reset when written with 1, a software reset is issued to all modules related to the ethernet (for 64 cycles at external bus clock b ). writing 0 does not affect this bit. this bit is always read as 0. while a software reset is issued, register access to all modules related to the ethernet is prohibited. the following registers are not initialized by a software reset. tsu_adrh0 to tsu_adrh31, tsu_adrl0 to tsu_adrl31, txnlcr0, txnlcr1, txalcr0, txalcr1, rxnlcr0, rxnlcr1, rxalcr0, rxalcr1, fwnlcr0, fwnlcr1, fwalcr0, fwalcr1
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 645 of 950 rej09b0079-0200 18.3.2 etherc mode register (ecmr) ecmr is a 32-bit readable/writable register an d specifies the operating mode of the ethernet controller. the settings in this register are norma lly made in the initialization process following a reset. the operating mode setting must not be changed while the transm itting and receiving functions are enabled. to switch the operating mode, return the etherc and e-dmac to their initial states by means of the swr bit in edmr before making settings again. bit bit name initial value r/w description 31 to 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 mct 0 r/w multicast address frame receive mode 0: frames other than the mu lticast address set by the cam entry table 0 to 31 (h/l) registers are received. however, if the on-chip cam entry table reference is disabled, all multicast address frames are received. 1: only the multicast address set by the cam entry table 0 to 31 (h/l) registers is received. 12 prcef 0 r/w crc error frame reception enable 0: a receive frame including a crc error is received as a frame with an error. 1: a receive frame including a crc error is received as a frame without an error. when this bit is cleared to 0, the crc error is reflected in ecsr of the e-dmac and the status of the receive descriptor. when this bit is set to 1, a frame is received as a normal frame. 11 10 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 646 of 950 rej09b0079-0200 bit bit name initial value r/w description 9 mpde 0 r/w magic packet detection enable enables or disables magic packet detection by hardware to allow activation from the ethernet. 0: magic packet detection is not enabled 1: magic packet detection is enabled 8 7 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0. 6 re 0 r/w reception enable if a switch is made from receive function enabled (re = 1) to disabled (re = 0) while a frame is being received, the receive function will be enabled until reception of the corresponding frame is completed. 0: receive function is disabled 1: receive function is enabled 5 te 0 r/w transmission enable if a switch is made from transmit function enabled (te = 1) to disabled (te = 0) while a frame is being transmitted, the transmit f unction will be enabled until transmission of the corresponding frame is completed. 0: transmit function is disabled 1: transmit function is enabled 4 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 3 ilb 0 r/w internal loop back mode specifies loopback mode in the etherc. 0: normal data transmission/reception is performed. 1: data loopback is performed inside the mac in the etherc.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 647 of 950 rej09b0079-0200 bit bit name initial value r/w description 2 elb 0 r/w external loop back mode this bit value is output directly to this lsi?s general- purpose external output pin (exout). this bit is used for loopback mode directives, etc., in the phy- lsi, using the exout pin. in order for phy-lsi loopback to be implemented using this function, the phy-lsi must have a pin corresponding to the exout pin. 0: low-level output from the exout pin 1: high-level output from the exout pin 1 dm 0 r/w duplex mode specifies the etherc transfer method. 0: half-duplex transfer is specified 1: full-duplex transfer is specified 0 prm 0 r/w promiscuous mode setting this bit enables all ethernet frames to be received. all ethernet frames means all receivable frames, irrespective of differences or enabled/disabled status (destination address, broadcast address, multicast bit, etc.). 0: etherc performs normal operation 1: etherc performs promiscuous mode operation
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 648 of 950 rej09b0079-0200 18.3.3 etherc status register (ecsr) ecsr is a 32-bit readable/writable register and indi cates the status in the etherc. this status can be notified to the cpu by interrupts. when 1 is written to the brcrx, psrto, lchng, mpd, and icd, the corresponding flags can be cleared. writing 0 does not affect the flag. for bits that generate interrupt, the interrupt can be enabled or disabled according to th e corresponding bit in ecsipr. the interrupts generated due to this status regist er are indicated in each eci bit in eesr of the e- dmac0 derived from port0 and the e-dmac1 derived from port1. bit bit name initial value r/w description 31 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 lchng 0 r/w link signal change indicates that the lnksta signal input from the phy- lsi has changed from high to low or low to high. however, signal changes may be detected at the timing at which the lnksta function was selected using pacr of pfc. to check the current link state, refer to the lmon bit in the phy status register (psr). 0: change in the lnksta signal has not been detected 1: change in the lnksta signal has been detected (high to low or low to high) 1 mpd 0 r/w magic packet detection indicates that a magic packet has been detected on the line. 0: magic packet has not been detected 1: magic packet has been detected
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 649 of 950 rej09b0079-0200 bit bit name initial value r/w description 0 icd 0 r/w illegal carrier detection indicates that the phy-lsi has detected an illegal carrier on the line. if a change in the signal input from the phy-lsi occurs before the software recognition period, the correct information may not be obtained. refer to the timing specification for the phy-lsi used. 0: phy-lsi has not detected an illegal carrier on the line 1: phy-lsi has detected an illegal carrier on the line 18.3.4 etherc interrupt perm ission register (ecsipr) ecsipr is a 32-bit readable/writable register that enables or disables the interrupt sources indicated by ecsr. each bit can disable or enable interrupts corr esponding to the bits in ecsr. bit bit name initial value r/w description 31 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 lchngip 0 r/w link signal changed interrupt enable 0: interrupt notification by the lchng bit is disabled 1: interrupt notification by the lchng bit is enabled 1 mpdip 0 r/w magic packet detection interrupt enable 0: interrupt notification by the mpd bit is disabled 1: interrupt notification by the mpd bit is enabled 0 icdip 0 r/w illegal carrier detection interrupt enable 0: interrupt notification by the icd bit is disabled 1: interrupt notification by the icd bit is enabled
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 650 of 950 rej09b0079-0200 18.3.5 phy interface register (pir) pir is a 32-bit readable/writable register that pr ovides a means of accessing the phy-lsi registers via the mii. bit bit name initial value r/w description 31 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 mdi undefined r mii management data-in indicates the level of the mdio pin. 2 mdo 0 r/w mii management data-out outputs the value set to this bit from the mdio pin, when the mmd bit is 1. 1 mmd 0 r/w mii management mode specifies the data read/writ e direction with respect to the mii. 0: read direction is indicated 1: write direction is indicated 0 mdc 0 r/w mii management data clock outputs the value set to this bit from the mdc pin and supplies the mii with the management data clock. for the method of accessing the mii registers, see section 18.4.6, accessing mii registers.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 651 of 950 rej09b0079-0200 18.3.6 mac address high register (mahr) mahr is a 32 -bit readable/writable register that specifies the upper 32 bits of the 48-bit mac address. the settings in this register are normally made in the initialization process after a reset. the mac address setting must not be changed whil e the transmitting and receiving functions are enabled. to switch the mac address setting, return the etherc and e-dmac to their initial states by means of the swr bit in edmr before making settings again. bit bit name initial value r/w description 31 to 0 ma47 to ma16 all 0 r/w mac address bits these bits are used to set the upper 32 bits of the mac address. if the mac address is 01-23-45-67-89-ab (hexadecimal), the value set in this register is h'01234567. 18.3.7 mac address low register (malr) malr is a 32-bit readable/writable register that specifies the lower 16 bits of the 48-bit mac address. the settings in this register are normally made in the initialization process after a reset. the mac address setting must not be changed whil e the transmitting and receiving functions are enabled. to switch the mac address setting, return the etherc and e-dmac to their initial states by means of the swr bit in edmr before making settings again. bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 0 ma15 to ma0 all 0 r/w mac address bits 15 to 0 these bits are used to set the lower 16 bits of the mac address. if the mac address is 01-23-45-67-89-ab (hexadecimal), the value set in this register is h'000089ab.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 652 of 950 rej09b0079-0200 18.3.8 receive frame le ngth register (rflr) rflr is a 32-bit readable/writable register and it specifies the maximum frame length (in bytes) that can be received by this lsi. the settings in this register must not be changed while the receiving function is enabled. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 rfl11 to rfl0 all 0 r/w receive frame length 11 to 0 the frame length described here refers to all fields from the destination address up to the crc data. frame contents from the des tination address up to the data are actually transferred to memory. crc data is not included in the transfer. when data that exceeds the specified value is received, the part of the data that exceeds the specified value is discarded. h'000 to h?5ee: 1,518 bytes h'5ef: 1,519 bytes h'5f0: 1,520 bytes : : : : h'7ff: 2,047 bytes h'800 to h?fff: 2,048 bytes
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 653 of 950 rej09b0079-0200 18.3.9 phy status register (psr) psr is a read-only register that can read interface signals from the phy-lsi. bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 lmon 0 r lnksta pin status the link status can be read by connecting the link signal output from the phy-lsi to the lnksta pin. for the polarity, refer to the ph y-lsi specifications to be connected. 18.3.10 transmit retry ov er counter register (trocr) trocr is a 32-bit counter that indi cates the number of frames that were unable to be transmitted in 16 transmission attempts including the retransf er. when 16 transmission attempts have failed, trocr is incremented by 1. when the value in this register reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 troc31 to troc0 all 0 r/w transmit retry over count these bits indicate the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 654 of 950 rej09b0079-0200 18.3.11 delayed collision detect counter register (cdcr) cdcr is a 32-bit counter that indicates the number of all delayed collisions that accured on the line after the start of data tran smission. when the value in this register reaches h'ffffffff, count-up is halted. the counter va lue is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 cosdc31 to cosdc0 all 0 r/w delayed collision detect count these bits indicate the number of all delayed collisions after the start of data transmission. 18.3.12 lost carrier co unter register (lccr) lccr is a 32-bit counter that indicates the numb er of times the carrier was lost during data transmission. when the value in this register reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by writing to this register with any value. bit bit name initial value r/w description 31 to 0 lcc31 to lcc0 all 0 r/w lost carrier count these bits indicate the number of times the carrier was lost during data transmission. 18.3.13 carrier not detect counter register (cndcr) cndcr is a 32-bit counter that in dicates the number of times the carrier could not be detected while the preamble was being sent. when the valu e in this register reac hes h'ffffffff, the count is halted. the counter value is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 cndc31 to cndc0 all 0 r/w carrier not detect count these bits indicate the number of times the carrier was not detected.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 655 of 950 rej09b0079-0200 18.3.14 crc error frame recei ve counter register (cefcr) cefcr is a 32-bit counter that indicates the number of times a frame with a crc error was received. when the value in this register reac hes h'ffffffff, the count is halted. the counter value is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 cefc31 to cefc0 all 0 r/w crc error frame count these bits indicate the count of crc error frames received. 18.3.15 frame receive erro r counter register (frecr) frecr is a 32-bit counter that indicates the nu mber of frames for which a receive error was indicated by the rx-er input pin from the ph y-lsi. frecr is incremented each time the rx- er pin becomes active. when the value in this re gister reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a wr ite to this register with any value. bit bit name initial value r/w description 31 to 0 frec31 to frec0 all 0 r/w frame receive error count these bits indicate the count of errors during frame reception. 18.3.16 too-short frame recei ve counter register (tsfrcr) tsfrcr is a 32-bit counter that indicates the number of frames of fewer than 64 bytes that have been received. when the value in this regist er reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a wr ite to this register with any value. bit bit name initial value r/w description 31 to 0 tsfc31 to tsfc0 all 0 r/w too-short frame receive count these bits indicate the count of frames received with a length of less than 64 bytes.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 656 of 950 rej09b0079-0200 18.3.17 too-long frame recei ve counter register (tlfrcr) tlfrcr is a 32-bit counter that in dicates the number of frames received with a length exceeding the value specified by the receive frame length register (rflr). when the value in this register reaches h'ffffffff, the count is halted. tlfrcr is not incremented when a frame containing residual bits is received. in this case, the rece ption of the frame is indi cated in the residual-bit frame counter register (rfcr). the counter value is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 tlfc31 to tlfc0 all 0 r/w too-long frame receive count these bits indicate the count of frames received with a length exceeding the value in rflr. 18.3.18 residual-bit frame r eceive counter register (rfcr) rfcr is a 32-bit counter that indicates the numb er of frames received containing residual bits (less than an 8-bit unit). when the value in this register reaches h'ffffff ff, the count is halted. the counter value is cleared to 0 by a wr ite to this register with any value. bit bit name initial value r/w description 31 to 0 rfc31 to rfc0 all 0 r/w residual-bit frame count these bits indicate the count of frames received containing residual bits.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 657 of 950 rej09b0079-0200 18.3.19 multicast address frame receive counter register (mafcr) mafcr is a 32-bit counter that in dicates the number of frames r eceived with a specified multicast address. when the value in this register reaches h'ffffffff, th e count is halted. the counter value is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 mafc31 to mafc0 all 0 r/w multicast address frame count these bits indicate the count of multicast frames received. 18.3.20 ipg register (ipgr) ipgr sets the ipg (inter packet gap). this register must not be changed while the transmitting and receiving functions of the et herc mode register (ecmr) are enabled. (for details, refer to section 18.4.8, operation by ipg setting.) bit bit name initial value r/w description 31 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 to 0 ipg4 to ipg0 h 13 r/w inter packet gap sets the ipg value every 4-bit time. h 00: 20-bit time h 01: 24-bit time : : h 13: 96-bit time (default) : : h 1f: 144-bit time
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 658 of 950 rej09b0079-0200 18.3.21 tsu counter reset register (tsu_ctrst) tsu_ctrst clears the transmit, receive, and transfer frame counters to 0. bit bit name initial value r/w description 31 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 ctrst 0 r/w tsu counter reset when 1 is written to this bit, the values of registers txncr0/1, txalcr0/1, rxnlcr0/1, rxalcr0/1, fwnlcr0/1, and fwalcr0/1 are cleared to 0. writing 0 does not affect this bit. these bits are always read as 0. 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 18.3.22 relay enable register (port 0 to 1) (tsu_fwen0) tsu_fwen0 enables or disables relay operations from the mac-0 to mac-1 (writing to the relay fifo). bit bit name initial value r/w description 31 fwen0 0 r/w port 0 to 1 relay operation enable 0: port 0 to 1 relay is disabled 1: port 0 to 1 relay is enabled when the value of the fcm2 to fcm0 in the tsu fifo size select register tsu_fcm is set to h 4, setting this bit to 1 is prohibited. 30 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 659 of 950 rej09b0079-0200 18.3.23 relay enable register (port 1 to 0) (tsu_fwen1) tsu_fwen1 enables or disables relay operations from the mac-1 to mac-0 (writing to the relay fifo). bit bit name initial value r/w description 31 fwen1 0 r/w port 1 to 0 relay operation enable 0: port 1 to 0 relay is disabled 1: port 1 to 0 relay is enabled when the value of the fcm2 to fcm0 in the tsu fifo size select register tsu_fcm is set to h 3, setting this bit to 1 is prohibited. 30 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 660 of 950 rej09b0079-0200 18.3.24 relay fifo size se lect register (tsu_fcm) tsu_fcm selects the size of the tsu fifo, used for relay operations between the mac-0 and mac-1. bit bit name initial value r/w description 31 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 to 0 fcm2 to fcm0 all 0 r/w tsu fifo size h 0: port 0 to 1: 3 kbytes port 1 to 0: 3 kbytes h 1: port 0 to 1: 4 kbytes port 1 to 0: 2 kbytes h 2: port 0 to 1 : 5 kbytes port 1 to 0: 1 kbyte h 3: port 0 to 1: 6 kbytes port 1 to 0: not used h 4: port 0 to 1: not used port 1 to 0: 6 kbytes h 5: port 0 to 1: 1 kbyte port 1 to 0: 5 kbytes h 6: port 0 to 1: 2 kbytes port 1 to 0: 4 kbytes h 7: setting prohibited writing to this register is pr ohibited, after relay operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1).
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 661 of 950 rej09b0079-0200 18.3.25 relay fifo overflow alert set register (port 0) (tsu_bsysl0) the tsu has an alert function, which informs the mac-0 and mac-1 that writing to the tsu fifo will be disabled when the data volume written in the tsu fifo during relay operations exceeds a certain threshold. tsu_bsysl0 sets the threshold of the tsu fifo when the tsu alerts the mac-0 that writing to the tsu fifo will be disabled during relay operations. bit bit name initial value r/w description 31 to 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 to 0 bsysl05 to bsysl00 all 1 r/w sets the threshold of the port 0 to 1 tsu fifo capacity in 256-byte units when the tsu alerts the mac-0 that writing in t he tsu fifo will be disabled during relay operations. h 00: 0 byte h 01: 256 bytes h 02: 512 bytes : : h 16: 5632 bytes h 17: 5888 bytes settings are disabled for h 18 to h 3f. (alert is not always carried out.) when h 00 is set, the tsu always alerts the mac-0 that writing to the tsu fifo will be disabled. when the value set is above the port 0 to 1 transfer fifo capacity set by the fcm2 to fcm0 in tsu_fcm, the tsu does not alert the mac-0 that writing to the tsu fifo will be disabled. writing to this register is prohibited, after relay operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1). when the enable bit of relay operations (the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1) is cleared to 0, the tsu stops alerting the mac-0 that writing to the tsu fifo will be disabled.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 662 of 950 rej09b0079-0200 18.3.26 relay fifo overflow alert set register (port 1) (tsu_bsysl1) the tsu has an alert function, which informs the mac-0 and mac-1 that writing to the tsu fifo will be disabled when the data volume written in the tsu fifo during relay operations exceeds a certain threshold. tsu_bsysl1 sets the threshold of the tsu fifo when the tsu alerts the mac-1 to writing to the tsu fifo will be disabled during relay operations. bit bit name initial value r/w description 31 to 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 to 0 bsysl15 to bsysl10 all 1 r/w sets the threshold of the port 1 to 0 tsu fifo capacity in 256-byte units when the tsu alerts the mac-1 that writing in t he tsu fifo will be disabled during relay operations. h 00: 0 byte h 01: 256 bytes h 02: 512 bytes : : h 16: 5632 bytes h 17: 5888 bytes settings are disabled for h 18 to h 3f. (alert is not always carried out.) when h 00 is set, the tsu always alerts the mac-1 that writing to the trans fer fifo will be disabled. when the value set is above the port 1 to 0 tsu fifo capacity set by the fcm2 to fcm0 in tsu_fcm, the tsu does not alert the mac-1 to writing that the tsu fifo will be disabled. writing to this register is prohibited, after relay operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1). when the enable bit of relay operations (the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1) is cleared to 0, the tsu stops alerting the mac-1 to writing to the tsu fifo will be disabled.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 663 of 950 rej09b0079-0200 18.3.27 transmit/relay priority control mode register (port 0) (tsu_prisl0) tsu_prisl0 sets the priority control mode when the transmission request from the e-dmac to mac-0 come into collision with port 1 to 0 relay op erations. writing to this register is prohibited, after relay operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1). bit bit name initial value r/w description 31 to 15 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 14 to 12 primd02 to primd00 all 0 r/w sets the priority c ontrol mode of mac-0 transmission and port 1 to 0 relay operations. h 0: round robin h 1: transmission priority h 2: relay priority h 4: round robin, however switched to relay priority when tsu fifo use amount exceeds the set value of prisl07 to prisl00 h 5: transmission priority, however switched to relay priority when tsu fifo use amount exceeds the set value of prisl07 to prisl00 others: setting prohibited 11 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 664 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 to 0 prisl07 to prisl00 all 0 r/w sets the threshold of the port 1 to 0 tsu fifo capacity in 64-byte units in the event switching to relay priority when primd02 to primd00 are set to h 4 or h 5. h 00: 0 byte h 01: 64 bytes h 02: 128 bytes : : h 5e: 6016 bytes h 5f: 6080 bytes settings are disabled for h 60 to h ff. when set to h 00, relay always takes priority. when the value set is above the port 1 to 0 tsu fifo capacity set by the fcm2 to fcm0 in tsu_fcm, if the primd02 to primd00 are h 4, round robin will always be set. if the primd02 to primd00 are h 5, transmission always takes priority. 18.3.28 transmit/relay priority control mode register (port 1) (tsu_prisl1) tsu_prisl1 sets the priority control mode when the transmission request from the e-dmac to mac-1 come into collision with port 0 to 1 relay op erations. writing to this register is prohibited, after relay operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1). bit bit name initial value r/w description 31 to 15 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 665 of 950 rej09b0079-0200 bit bit name initial value r/w description 14 to 12 primd12 to primd10 all 0 r/w sets the priority c ontrol mode of mac-1 transmission and port 0 to 1 relay operations. h 0: round robin h 1: transmission priority h 2: relay priority h 4: round robin, however switched to relay priority when tsu fifo use amount exceeds the set value of prisl17 to prisl10 h 5: transmission priority, however switched to relay priority when tsu fifo use amount exceeds the set value of prisl17 to prisl10 others: setting prohibited 11 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 prisl17 to prisl10 all 0 r/w sets the threshold val ue of the port 0 to 1 tsu fifo capacity in 64-byte units in the event switching to relay priority when primd12 to primd10 are set to h 4 or h 5. h 00: 0 byte h 01: 64 bytes h 02: 128 bytes : : h 5e: 6016 bytes h 5f: 6080 bytes settings are disabled for h 60 to h ff. when set to h 00, relay always takes priority. when the value set is above the port 0 to 1 tsu fifo capacity set by the fcm2 to fcm0 in tsu_fcm, if the primd12 to primd10 are h 4, round robin will always be set. if the primd12 to primd10 are h 5, transmission always takes priority.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 666 of 950 rej09b0079-0200 18.3.29 receive/relay function set register (port 0 to 1) (tsu_fwsl0) tsu_fwsl0 sets the processing me thod of each frame in port 0 reception and port 0 to 1 relay operations. in receiving a frame, th e processing method can be de termined by referring to the cam evaluation results when the multicast frame and the destination are other than this lsi. (for details, refer to section 18.4.4, cam function.) writin g to this register is prohibited, after relay operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1). bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 fw40 0 r/w sets the processing method when frames from port 0 are addressed to this lsi 0: frames are not relayed 1: frames are relayed to port 1 10 fw30 0 r/w sets the processing method when frames from port 0 are broadcast. 0: frames are not relayed 1: frames are relayed to port 1 9 fw20 0 r/w sets the processing method when frames from port 0 are multicast. 0: cam hit: frames are relayed to port 1 cam mishit: frames are not relayed 1: cam hit: frames are not relayed cam mishit: frames are relayed to port 1 8 fw10 0 r/w sets the processing method when frames from port 0 are addressed to other than this lsi. 0: cam hit: frames are relayed to port 1 cam mishit: frames are not relayed 1: cam hit: frames are not relayed cam mishit: frames are relayed to port 1
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 667 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 18.3.30 receive/relay function set register (port 1 to 0) (tsu_fwsl1) tsu_fwsl1 sets the processing me thod of each frame in port 1 reception and port 1 to 0 relay operations. in receiving a frame, th e processing method can be de termined by referring to the cam evaluation results when the multicast frame and the destination are other than this lsi. (for details, refer to section 18.4.4, cam function.) wri ting to this register is prohibited, after relay operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1). bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 fw41 0 r/w sets the processing method when frames from port 1 are addressed to this lsi 0: frames are not relayed 1: frames are relayed to port 0 10 fw31 0 r/w sets the processing method when frames from port 1 are broadcast. 0: frames are not relayed 1: frames are relayed to port 0 9 fw21 0 r/w sets the processing method when frames from port 1 are multicast. 0: cam hit: frames are relayed to port 0 cam mishit: frames are not relayed 1: cam hit: frames are not relayed cam mishit: frames are relayed to port 0
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 668 of 950 rej09b0079-0200 bit bit name initial value r/w description 8 fw11 0 r/w sets the processing method when frames from port 1 are addressed to other than this lsi. 0: cam hit: frames are relayed to port 0 cam mishit: frames are not relayed 1: cam hit: frames are not relayed cam mishit: frames are relayed to port 0 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 669 of 950 rej09b0079-0200 18.3.31 relay function set register (common) (tsu_fwslc) when the cam is used, the referred area in the cam entry table (partially or wholly) can be specified by the tsu_post1 to tsu_post4 registers. when the cam is installed outside this lsi, the evaluation results of the external cam can be referred by input on the camsen0 and camsen1 pins. (for details, refer to section 18.4.4, cam function.) tsu_fwslc enables settings by the tsu_post1 to tsu_post4 registers and conditions for referring signals on the camsen0 and camsen1 pins. writing to this register is prohibited, after relay operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1). bit bit name initial value r/w description 31 to 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 postenu 0 r/w enables the settings of the post field of cam entry tables 0 to 15 (settings by the tsu_post1 and tsu_post2 registers). 0: disables the settings of the post field. (the cam entry table is referred only in port 0 reception.) 1: enables the settings of the post field. (the cam entry table reference conditions follow the post field settings.) 12 postenl 0 r/w enables the settings of the post field of cam entry tables 16 to 31 (settings by the tsu_post3 and tsu_post4 registers). 0: disables the settings of the post field. (the cam entry table is referred only in port 1 reception.) 1: enables the settings of the post field. (the cam entry table reference conditions follow the post field settings.) 11 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 670 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 6 5 4 camsel03 camsel02 camsel01 camsel00 1 0 0 0 r/w r/w r/w r/w these bits set the conditions for referring signals on the camsen0 pin. by setting multiple bits to 1, multiple conditions can be selected. camsel03: refers signals on the camsen0 pin in port 0 reception camsel02: refers signals on the camsen0 pin in port 0 to 1 relay camsel01: refers signals on the camsen0 pin in port 1 reception camsel00: refers signals on the camsen0 pin in port 1 to 0 relay 3 2 1 0 camsel13 camsel12 camsel11 camsel10 0 0 1 0 r/w r/w r/w r/w these bits set the conditions for referring signals on the camsen1 pin. by setting multiple bits to 1, multiple conditions can be selected. camsel13: refers signals on the camsen1 pin in port 0 reception camsel12: refers signals on the camsen1 pin in port 0 to 1 relay camsel11: refers signals on the camsen1 pin in port 1 reception camsel10: refers signals on the camsen1 pin in port 1 to 0 relay
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 671 of 950 rej09b0079-0200 18.3.32 qtag addition/deletion set register (port 0 to 1) (tsu_qtagm0) tsu_qtagm0 sets the functions adding qtag fr om the normal ethernet frames (no qtag) to ieee802.1q frames (with qtag) and deleting qtags from ieee802.1q frames (with qtag) to normal ethernet frames (no qtag) during port 0 to 1 relay operations. writing to this register is prohibited, after relay operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1). bit bit name initial value r/w description 31 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1,0 qtagm01, qtagm00 all 0 r/w these bits set qtag adding and deleting functions during port 0 to 1 relay operations. h 0: no qtag adding and deleting functions h 1: no qtag adding and deleting functions (same as h 0) h 2: deletes qtag from frames with qtag h 3: adds qtag to frames with no qtag writing to this register is prohibited, after transfer operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1).
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 672 of 950 rej09b0079-0200 18.3.33 qtag addition/deletion set register (port 1 to 0) (tsu_qtagm1) tsu_qtagm1 sets the functions adding qtag fr om the normal ethernet frames (no qtag) to ieee802.1q frames (with qtag) and deleting qtags from ieee802.1q frames (with qtag) to normal ethernet frames (no qtag) during port 1 to 0 relay operations. writing to this register is prohibited, after relay operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1). bit bit name initial value r/w description 31 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1, 0 qtagm11, qtagm10 all 0 r/w these bits set qtag adding and deleting functions during port 1 to 0 relay operations. h 0: no qtag adding and deleting functions h 1: no qtag adding and deleting functions (same as h 0) h 2: deletes qtag from frames with qtag h 3: adds qtag to frames with no qtag writing to this register is prohibited, after transfer operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1).
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 673 of 950 rej09b0079-0200 18.3.34 relay status register (tsu_fwsr) tsu_fwsr is a 32-bit readable/writa ble register that indicates the status during relay operations. by setting the tsu status interrupt mask register (tsu_fwinmk), this status can be notified to the cpu as an interrupt source. the status bit set to 1 will be cleared to 0 by writing 1 to corresponding bit. (the status bit retains the value until it is cleared to 0.) interrupts generated due to this status register is eint2. for details on the priority order of interrupts, refer to section 8.3.5, interrupt excep tion handling and priority in section 8, interrupt controller (intc). bit bit name initial value r/w description 31 to 28 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 27 tint40 0 r/w mac-0 carrier not detect set to 1 when a carrier not detect has occured in the mac-0 26 tint30 0 r/w mac-0 carrier lost set to 1 when a carrier is lost during data transmission in the mac-0 25 tint20 0 r/w mac-0 collision detect set to 1 when a collision of frames is detected in the mac-0 24 tint10 0 r/w mac-0 transmission time out set to 1 when frames were unable to be transmitted in 16 transmission attempts including the retransfer in the mac-0 23 ovf0 0 r/w port 0 to 1 tsu fifo overflow detect set to 1 when a port 0 to 1 tsu fifo overflow has occured 22 rbsy0 0 r/w mac-0 overflow alert signal output set to 1 when the threshold of tsu_bsysl0 is valid and exceeded 21 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 674 of 950 rej09b0079-0200 bit bit name initial value r/w description 20 rint50 0 r/w mac-0 residual bit frame receive set to 1 when frames containing residual bits (less than an 8-bit unit) are received in the mac-0 19 rint40 0 r/w mac-0 exceeding byte frame receive set to 1 when frames exceeding the value set by rflr0 are received in the mac-0 18 rint30 0 r/w mac-0 less 64-byte frame receive set to 1 when frames with a length of less than 64 bytes are received in the mac-0 17 rint20 0 r/w mac-0 frame receive error set to 1 when a receive error is detected on the rx-er pin input from the phy in the mac-0 16 rint10 0 r/w mac-0 crc error frame receive set to 1 when a receive frame results in a crc error in the mac-0 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 tint41 0 r/w mac-1 carrier not detect set to 1 when a carrier not detect has occured in the mac-1 10 tint31 0 r/w mac-1 carrier lost set to 1 when a carrier is lost during data transmission in the mac-1 9 tint21 0 r/w mac-1 collision detect set to 1 when a collision of frames is detected in the mac-1 8 tint11 0 r/w mac-1 transmission time out set to 1 when frames were unable to be transmitted in 16 transmission attempts including the retransfer in the mac-1 7 ovf1 0 r/w port 1 to 0 tsu fifo overflow detect set to 1 when a port 1 to 0 tsu fifo overflow has occured
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 675 of 950 rej09b0079-0200 bit bit name initial value r/w description 6 rbsy1 0 r/w mac-1 overflow alert signal output set to 1 when the threshold of tsu_bsysl1 is valid and exceeded 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 rint51 0 r/w mac-1 residual bit frame receive set to 1 when frames containing residual bits (less than an 8-bit unit) are received in the mac-1 3 rint41 0 r/w mac-1 exceeding byte frame receive set to 1 when frames exceeding the value set by rflr1 are received in the mac-1 2 rint31 0 r/w mac-1 less 64-byte frame receive set to 1 when frames with a length of less than 64 bytes are received in the mac-1 1 rint21 0 r/w mac-1 frame receive error set to 1 when a receive error is detected on the rx-er pin input from the phy in the mac-1 0 rint11 0 r/w mac-1 crc error frame receive set to 1 when a receive frame results in a crc error in the mac-1 18.3.35 relay status interrupt mask register (tsu_fwinmk) tsu_fwinmk is a 32-bit readable/writable register that sets the interrupt mask for status bits in tsu_fwsr. bit bit name initial value r/w description 31 to 28 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 27 tintm40 0 r/w mac-0 carrier not detect interrupt mask 0: interrupts disabled 1: interrupts enabled
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 676 of 950 rej09b0079-0200 bit bit name initial value r/w description 26 tintm30 0 r/w mac-0 carrier lost interrupt mask 0: interrupts disabled 1: interrupts enabled 25 tintm20 0 r/w mac-0 collision detect interrupt mask 0: interrupts disabled 1: interrupts enabled 24 tintm10 0 r/w mac-0 transmission time out interrupt mask 0: interrupts disabled 1: interrupts enabled 23 ovfm0 0 r/w port 0 to 1 tsu fifo overflow detect interrupt mask 0: interrupts disabled 1: interrupts enabled 22 rbsym0 0 r/w mac-0 overflow aler t signal output interrupt mask 0: interrupts disabled 1: interrupts enabled 21 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 20 rintm50 0 r/w mac-0 residual bit frame receive interrupt mask 0: interrupts disabled 1: interrupts enabled 19 rintm40 0 r/w mac-0 exceeding by te frame receive interrupt mask 0: interrupts disabled 1: interrupts enabled 18 rintm30 0 r/w mac-0 less 64-byt e frame receive interrupt mask 0: interrupts disabled 1: interrupts enabled 17 rintm20 0 r/w mac-0 frame receive error interrupt mask 0: interrupts disabled 1: interrupts enabled
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 677 of 950 rej09b0079-0200 bit bit name initial value r/w description 16 rintm10 0 r/w mac-0 crc error frame receive interrupt mask 0: interrupts disabled 1: interrupts enabled 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 tintm41 0 r/w mac-1 carrier not detect interrupt mask 0: interrupts disabled 1: interrupts enabled 10 tintm31 0 r/w mac-1 carrier lost interrupt mask 0: interrupts disabled 1: interrupts enabled 9 tintm21 0 r/w mac-1 collision detect interrupt mask 0: interrupts disabled 1: interrupts enabled 8 tintm11 0 r/w mac-1 transmission time out interrupt mask 0: interrupts disabled 1: interrupts enabled 7 ovfm1 0 r/w port 1 to 0 tsu fifo overflow detect interrupt mask 0: interrupts disabled 1: interrupts enabled 6 rbsym1 0 r/w mac-1 overflow aler t signal output interrupt mask 0: interrupts disabled 1: interrupts enabled 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 rintm51 0 r/w mac-1 residual bit frame receive interrupt mask 0: interrupts disabled 1: interrupts enabled
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 678 of 950 rej09b0079-0200 bit bit name initial value r/w description 3 rintm41 0 r/w mac-1 exceeding byte frame receive interrupt mask 0: interrupts disabled 1: interrupts enabled 2 rintm31 0 r/w mac-1 less 64-byt e frame receive interrupt mask 0: interrupts disabled 1: interrupts enabled 1 rintm21 0 r/w mac-1 frame receive error interrupt mask 0: interrupts disabled 1: interrupts enabled 0 rintm11 0 r/w mac-1 crc error frame receive interrupt mask 0: interrupts disabled 1: interrupts enabled
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 679 of 950 rej09b0079-0200 18.3.36 added qtag value set register (port 0 to 1) (tsu_adqt0) tsu_adqt0 sets qtag data to be added in the conversion of normal ethernet frames (without qtag) to ieee802.1q frames (with qtag) in port 0 to 1 relay operations (when setting the qtagm01 to qtagm00 bits in tsu_qtagm0 to h 3 in the use of the qtag addition function). writing to this register is prohibited, after relay operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1). bit bit name initial value r/w description 31 to 16 qtag031 to qtag016 h 8100 r/w be sure to set the value of the upper 16 bits (qtag031 to qtag016) as h 8100 (indicates that it is the qtag extension frame format). the value read is h 8100. 15 to 13 qtag015 to qtag013 h 0 r/w priority setting (prt) these bits set the processing priority of frames with qtag. for details on the settings, refer to the specifications on qtag control specified in ieee802.1q. 12 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 11 to 0 qtag011 to qtag000 h 000 r/w v-lan id setting (vid) these bits set the flames with qtag to be used in the systems supporting v-lan. for details on settings, refer to the specifications on qtag control specified in ieee802.1q.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 680 of 950 rej09b0079-0200 18.3.37 added qtag value set register (port 1 to 0) (tsu_adqt1) tsu_adqt1 sets qtag data to be added in the conversion of normal ethernet frames (without qtag) to ieee802.1q frames (with qtag) in port 1 to 0 relay operations (when setting the qtagm11 to qtagm10 bits in tsu_qtagm1 to h 3 in the use of the qtag addition function). writing to this register is prohibited, after relay operations have been enabled once (after the fwen0 in tsu_fwen0 or the fwen1 in tsu_fwen1 is set to 1). bit bit name initial value r/w description 31 to 16 qtag131 to qtag116 h 8100 r/w be sure to set the value of the upper 16 bits (qtag131 to qtag116) as h 8100 (indicates that it is the qtag extension frame format). the value read is h 8100. 15 to 13 qtag115 to qtag113 h 0 r/w priority setting (prt) these bits set the processing priority of frames with qtag. for details on the settings, refer to the specifications on qtag control specified in ieee802.1q. 12 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 11 to 0 qtag111 to qtag100 h 000 r/w v-lan id setting (vid) these bits set the flames with qtag to be used in the systems supporting v-lan. for details on settings, refer to the specifications on qtag control specified in ieee802.1q.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 681 of 950 rej09b0079-0200 18.3.38 cam entry table busy register (tsu_adsbsy) when cam entry table registers (tsu_adrh0 to tsu_adrh31, tsu_adrl0 to tsu_adrl31) are set by register writing, the adsbsy bit in this register is set to 1 (when the process of reflecting the contents of the cam en try table register in the cam controller is completed inside the tsu, the adsbsy bit is automatically restored to 0). accessing to tsu_adrh0 to tsu_adrh31 and tsu_adrl0 to tsu_adrl31 is prohibited, while the adsbsy bit in this register is set to 1. this register is a read-only status register, and writing to this register is prohibited. bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 adsbsy 0 r cam entry table setting busy when tsu_adrh0 to tsu_adrh31 and tsu_adrl0 to tsu_adrl31 are set by r egister writing, the adsbsy bit is set to 1. when the process of reflecting the contents of the cam entry table register in the cam controller is completed in side the tsu, the adsbsy bit is automatically restored to 0. accessing to tsu_adrh0 to tsu_adrh31 and tsu_adrl0 to tsu_adrl31 is prohibited, while this bit is set to 1. writing to this register is also prohibited.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 682 of 950 rej09b0079-0200 18.3.39 cam entry table enable register (tsu_ten) tsu_ten enables or disables to refer cam entry table registers (tsu_adrh0 to tsu_adrh31 and tsu_adrl0 to tsu_adrl31). bit bit name initial value r/w description 31 ten0 0 r/w cam entry table 0 (tsu_adrh0 and tsu_adrl0) setting 0: disabled 1: enabled 30 ten1 0 r/w cam entry table 1 (tsu_adrh1 and tsu_adrl1) setting 0: disabled 1: enabled 29 ten2 0 r/w cam entry table 2 (tsu_adrh2 and tsu_adrl2) setting 0: disabled 1: enabled 28 ten3 0 r/w cam entry table 3 (tsu_adrh3 and tsu_adrl3) setting 0: disabled 1: enabled 27 ten4 0 r/w cam entry table 4 (tsu_adrh4 and tsu_adrl4) setting 0: disabled 1: enabled 26 ten5 0 r/w cam entry table 5 (tsu_adrh5 and tsu_adrl5) setting 0: disabled 1: enabled 25 ten6 0 r/w cam entry table 6 (tsu_adrh6 and tsu_adrl6) setting 0: disabled 1: enabled
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 683 of 950 rej09b0079-0200 bit bit name initial value r/w description 24 ten7 0 r/w cam entry table 7 (tsu_adrh7 and tsu_adrl7) setting 0: disabled 1: enabled 23 ten8 0 r/w cam entry table 8 (tsu_adrh8 and tsu_adrl8) setting 0: disabled 1: enabled 22 ten9 0 r/w cam entry table 9 (tsu_adrh9 and tsu_adrl9) setting 0: disabled 1: enabled 21 ten10 0 r/w cam entry table 10 (tsu_adrh10 and tsu_adrl10) setting 0: disabled 1: enabled 20 ten11 0 r/w cam entry table 11 (tsu_adrh11 and tsu_adrl11) setting 0: disabled 1: enabled 19 ten12 0 r/w cam entry table 12 (tsu_adrh12 and tsu_adrl12) setting 0: disabled 1: enabled 18 ten13 0 r/w cam entry table 13 (tsu_adrh13 and tsu_adrl13) setting 0: disabled 1: enabled 17 ten14 0 r/w cam entry table 14 (tsu_adrh14and tsu_adrl14) setting 0: disabled 1: enabled
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 684 of 950 rej09b0079-0200 bit bit name initial value r/w description 16 ten15 0 r/w cam entry table 15 (tsu_adrh10 and tsu_adrl15) setting 0: disabled 1: enabled 15 ten16 0 r/w cam entry table 16 (tsu_adrh16 and tsu_adrl16) setting 0: disabled 1: enabled 14 ten17 0 r/w cam entry table 17 (tsu_adrh17 and tsu_adrl17) setting 0: disabled 1: enabled 13 ten18 0 r/w cam entry table 18 (tsu_adrh18 and tsu_adrl18) setting 0: disabled 1: enabled 12 ten19 0 r/w cam entry table 19 (tsu_adrh19 and tsu_adrl19) setting 0: disabled 1: enabled 11 ten20 0 r/w cam entry table 20 (tsu_adrh20 and tsu_adrl20) setting 0: disabled 1: enabled 10 ten21 0 r/w cam entry table 21 (tsu_adrh21 and tsu_adrl21) setting 0: disabled 1: enabled 9 ten22 0 r/w cam entry table 22 (tsu_adrh22 and tsu_adrl22) setting 0: disabled 1: enabled
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 685 of 950 rej09b0079-0200 bit bit name initial value r/w description 8 ten23 0 r/w cam entry table 23 (tsu_adrh23 and tsu_adrl23) setting 0: disabled 1: enabled 7 ten24 0 r/w cam entry table 24 (tsu_adrh24 and tsu_adrl24) setting 0: disabled 1: enabled 6 ten25 0 r/w cam entry table 25 (tsu_adrh20 and tsu_adrl25) setting 0: disabled 1: enabled 5 ten26 0 r/w cam entry table 26 (tsu_adrh20 and tsu_adrl26) setting 0: disabled 1: enabled 4 ten27 0 r/w cam entry table 27 (tsu_adrh27 and tsu_adrl27) setting 0: disabled 1: enabled 3 ten28 0 r/w cam entry table 28 (tsu_adrh28 and tsu_adrl28) setting 0: disabled 1: enabled 2 ten29 0 r/w cam entry table 29 (tsu_adrh29 and tsu_adrl29) setting 0: disabled 1: enabled 1 ten30 0 r/w cam entry table 30 (tsu_adrh30 and tsu_adrl30) setting 0: disabled 1: enabled
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 686 of 950 rej09b0079-0200 bit bit name initial value r/w description 0 ten31 0 r/w cam entry table 31 (tsu_adrh31 and tsu_adrl31) setting 0: disabled 1: enabled 18.3.40 cam entry table post1 register (tsu_post1) when using the cam, the conditions for referring to each cam entry table can be specified by using the tsu_post1 to tsu_post4 registers. tsu_post1 specifies the conditions for referring to tsu_adrh0 to tsu_adrh7 and tsu_adrl0 to tsu_adrl7. the settings of this register are valid when the pose nu bit in tsu_fwslc is set to 1. bit bit name initial value r/w description 31 to 28 post03 to post00 all 0 r/w these bits set the conditions for referring to the cam entry table 0. by setting multiple bits to 1, multiple conditions can be selected. post03: the cam entry tabl e 0 is referred in port 0 reception. post02: the cam entry tabl e 0 is referred in port 0 to 1 relay. post01: the cam entry tabl e 0 is referred in port 1 reception. post00: the cam entry tabl e 0 is referred in port 1 to 0 relay. 27 to 24 post13 to post10 all 0 r/w these bits set the conditions for referring to the cam entry table 1. by setting multiple bits to 1, multiple conditions can be selected. post13: the cam entry tabl e 1 is referred in port 0 reception. post12: the cam entry tabl e 1 is referred in port 0 to 1 relay. post11: the cam entry tabl e 1 is referred in port 1 reception. post10: the cam entry tabl e 1 is referred in port 1 to 0 relay.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 687 of 950 rej09b0079-0200 bit bit name initial value r/w description 23 to 20 post23 to post20 all 0 r/w these bits set the conditions for referring to the cam entry table 2. by setting multiple bits to 1, multiple conditions can be selected. post23: the cam entry tabl e 2 is referred in port 0 reception. post22: the cam entry tabl e 2 is referred in port 0 to 1 relay. post21: the cam entry tabl e 2 is referred in port 1 reception. post20: the cam entry tabl e 2 is referred in port 1 to 0 relay. 19 to 16 post33 to post30 all 0 r/w these bits set the conditions for referring to the cam entry table 3. by setting multiple bits to 1, multiple conditions can be selected. post33: the cam entry tabl e 3 is referred in port 0 reception. post32: the cam entry tabl e 3 is referred in port 0 to 1 relay. post31: the cam entry tabl e 3 is referred in port 1 reception. post30: the cam entry tabl e 3 is referred in port 1 to 0 relay. 15 to 12 post43 to post40 all 0 r/w these bits set the conditions for referring to the cam entry table 4. by setting multiple bits to 1, multiple conditions can be selected. post43: the cam entry tabl e 4 is referred in port 0 reception. post42: the cam entry tabl e 4 is referred in port 0 to 1 relay. post41: the cam entry tabl e 4 is referred in port 1 reception. post40: the cam entry tabl e 4 is referred in port 1 to 0 relay.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 688 of 950 rej09b0079-0200 bit bit name initial value r/w description 11 to 8 post53 to post50 all 0 r/w these bits set the conditions for referring to the cam entry table 5. by setting multiple bits to 1, multiple conditions can be selected. post53: the cam entry tabl e 5 is referred in port 0 reception. post52: the cam entry tabl e 5 is referred in port 0 to 1 relay. post51: the cam entry tabl e 5 is referred in port 1 reception. post50: the cam entry tabl e 5 is referred in port 1 to 0 relay. 7 to 4 post63 to post60 all 0 r/w these bits set the conditions for referring to the cam entry table 6. by setting multiple bits to 1, multiple conditions can be selected. post63: the cam entry tabl e 6 is referred in port 0 reception. post62: the cam entry tabl e 6 is referred in port 0 to 1 relay. post61: the cam entry tabl e 6 is referred in port 1 reception. post60: the cam entry tabl e 6 is referred in port 1 to 0 relay. 3 to 0 post73 to post70 all 0 r/w these bits set the conditions for referring to the cam entry table 7. by setting multiple bits to 1, multiple conditions can be selected. post73: the cam entry tabl e 7 is referred in port 0 reception. post72: the cam entry tabl e 7 is referred in port 0 to 1 relay. post71: the cam entry tabl e 7 is referred in port 1 reception. post70: the cam entry tabl e 7 is referred in port 1 to 0 relay.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 689 of 950 rej09b0079-0200 18.3.41 cam entry table post2 register (tsu_post2) when using the cam, the conditions for referring to each cam entry table can be specified by using the tsu_post1 to tsu_post4 registers. tsu_post2 specifies the conditions for referring to tsu_adrh8 to tsu_adrh15 and tsu_adrl8 to tsu_adrl15. the settings of this register are valid when the pose nu bit in tsu_fwslc is set to 1. bit bit name initial value r/w description 31 to 28 post83 to post80 all 0 r/w these bits set the conditions for referring to the cam entry table 8. by setting multiple bits to 1, multiple conditions can be selected. post83: the cam entry tabl e 8 is referred in port 0 reception. post82: the cam entry tabl e 8 is referred in port 0 to 1 relay. post81: the cam entry tabl e 8 is referred in port 1 reception. post80: the cam entry tabl e 8 is referred in port 1 to 0 relay. 27 to 24 post93 to post90 all 0 r/w these bits set the conditions for referring to the cam entry table 9. by setting multiple bits to 1, multiple conditions can be selected. post93: the cam entry tabl e 9 is referred in port 0 reception. post92: the cam entry tabl e 9 is referred in port 0 to 1 relay. post91: the cam entry tabl e 9 is referred in port 1 reception. post90: the cam entry tabl e 9 is referred in port 1 to 0 relay.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 690 of 950 rej09b0079-0200 bit bit name initial value r/w description 23 to 20 post103 to post100 all 0 r/w these bits set the conditions for referring to the cam entry table 10. by setting mult iple bits to 1, multiple conditions can be selected. post103: the cam entry table 10 is referred in port 0 reception. post102: the cam entry table 10 is referred in port 0 to 1 relay. post101: the cam entry table 10 is referred in port 1 reception. post100: the cam entry table 10 is referred in port 1 to 0 relay. 19 to 16 post113 to post110 all 0 r/w these bits set the conditions for referring to the cam entry table 11. by setting mult iple bits to 1, multiple conditions can be selected. post113: the cam entry table 11 is referred in port 0 reception. post112: the cam entry table 11 is referred in port 0 to 1 relay. post111: the cam entry table 11 is referred in port 1 reception. post110: the cam entry table 11 is referred in port 1 to 0 relay. 15 to 12 post123 to post120 all 0 r/w these bits set the conditions for referring to the cam entry table 12. by setting mult iple bits to 1, multiple conditions can be selected. post123: the cam entry table 12 is referred in port 0 reception. post122: the cam entry table 12 is referred in port 0 to 1 relay. post121: the cam entry table 12 is referred in port 1 reception. post120: the cam entry table 12 is referred in port 1 to 0 relay.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 691 of 950 rej09b0079-0200 bit bit name initial value r/w description 11 to 8 post133 to post130 all 0 r/w these bits set the conditions for referring to the cam entry table 13. by setting mult iple bits to 1, multiple conditions can be selected. post133: the cam entry table 13 is referred in port 0 reception. post132: the cam entry table 13 is referred in port 0 to 1 relay. post131: the cam entry table 13 is referred in port 1 reception. post130: the cam entry table 13 is referred in port 1 to 0 relay. 7 to 4 post143 to post140 all 0 r/w these bits set the conditions for referring to the cam entry table 14. by setting mult iple bits to 1, multiple conditions can be selected. post143: the cam entry table 14 is referred in port 0 reception. post142: the cam entry table 14 is referred in port 0 to 1 relay. post141: the cam entry table 14 is referred in port 1 reception. post140: the cam entry table 14 is referred in port 1 to 0 relay. 3 to 0 post153 to post150 all 0 r/w these bits set the conditions for referring to the cam entry table 15. by setting mult iple bits to 1, multiple conditions can be selected. post153: the cam entry table 15 is referred in port 0 reception. post152: the cam entry table 15 is referred in port 0 to 1 relay. post151: the cam entry table 15 is referred in port 1 reception. post150: the cam entry table 15 is referred in port 1 to 0 relay.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 692 of 950 rej09b0079-0200 18.3.42 cam entry table post3 register (tsu_post3) when using the cam, the conditions for referring to each cam entry table can be specified by using the tsu_post1 to tsu_post4 registers. tsu_post3 specifies the conditions for referring to tsu_adrh16 to tsu_adrh23 and tsu_adrl16 to tsu_adrl23. the settings of this register are valid when the posenu bit in tsu_fwslc is set to 1. bit bit name initial value r/w description 31 to 28 post163 to post160 all 0 r/w these bits set the conditions for referring to the cam entry table 16. by setting mult iple bits to 1, multiple conditions can be selected. post163: the cam entry table 16 is referred in port 0 reception. post162: the cam entry table 16 is referred in port 0 to 1 relay. post161: the cam entry table 16 is referred in port 1 reception. post160: the cam entry table 16 is referred in port 1 to 0 relay. 27 to 24 post173 to post170 all 0 r/w these bits set the conditions for referring to the cam entry table 17. by setting mult iple bits to 1, multiple conditions can be selected. post173: the cam entry table 17 is referred in port 0 reception. post172: the cam entry table 17 is referred in port 0 to 1 relay. post171: the cam entry table 17 is referred in port 1 reception. post170: the cam entry table 17 is referred in port 1 to 0 relay.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 693 of 950 rej09b0079-0200 bit bit name initial value r/w description 23 to 20 post183 to post180 all 0 r/w these bits set the conditions for referring to the cam entry table 18. by setting mult iple bits to 1, multiple conditions can be selected. post183: the cam entry table 18 is referred in port 0 reception. post182: the cam entry table 18 is referred in port 0 to 1 relay. post181: the cam entry table 18 is referred in port 1 reception. post180: the cam entry table 18 is referred in port 1 to 0 relay. 19 to 16 post193 to post190 all 0 r/w these bits set the conditions for referring to the cam entry table 19. by setting mult iple bits to 1, multiple conditions can be selected. post193: the cam entry table 19 is referred in port 0 reception. post192: the cam entry table 19 is referred in port 0 to 1 relay. post191: the cam entry table 19 is referred in port 1 reception. post190: the cam entry table 19 is referred in port 1 to 0 relay. 15 to 12 post203 to post200 all 0 r/w these bits set the conditions for referring to the cam entry table 20. by setting mult iple bits to 1, multiple conditions can be selected. post203: the cam entry table 20 is referred in port 0 reception. post202: the cam entry table 20 is referred in port 0 to 1 relay. post201: the cam entry table 20 is referred in port 1 reception. post200: the cam entry table 20 is referred in port 1 to 0 relay.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 694 of 950 rej09b0079-0200 bit bit name initial value r/w description 11 to 8 post213 to post210 all 0 r/w these bits set the conditions for referring to the cam entry table 21. by setting mult iple bits to 1, multiple conditions can be selected. post213: the cam entry table 21 is referred in port 0 reception. post212: the cam entry table 21 is referred in port 0 to 1 relay. post211: the cam entry table 21 is referred in port 1 reception. post210: the cam entry table 21 is referred in port 1 to 0 relay. 7 to 4 post223 to post220 all 0 r/w these bits set the conditions for referring to the cam entry table 22. by setting mult iple bits to 1, multiple conditions can be selected. post223: the cam entry table 22 is referred in port 0 reception. post222: the cam entry table 22 is referred in port 0 to 1 relay. post221: the cam entry table 22 is referred in port 1 reception. post220: the cam entry table 22 is referred in port 1 to 0 relay. 3 to 0 post233 to post230 all 0 r/w these bits set the conditions for referring to the cam entry table 23. by setting mult iple bits to 1, multiple conditions can be selected. post233: the cam entry table 23 is referred in port 0 reception. post232: the cam entry table 23 is referred in port 0 to 1 relay. post231: the cam entry table 23 is referred in port 1 reception. post230: the cam entry table 23 is referred in port 1 to 0 relay.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 695 of 950 rej09b0079-0200 18.3.43 cam entry table post4 register (tsu_post4) when using the cam, the conditions for referring to each cam entry table can be specified by using the tsu_post1 to tsu_post4 registers. tsu_post4 specifies the conditions for referring to tsu_adrh24 to tsu_adrh31 and tsu_adrl24 to tsu_adrl31. the settings of this register are valid when the posenu bit in tsu_fwslc is set to 1. bit bit name initial value r/w description 31 to 28 post243 to post240 all 0 r/w these bits set the conditions for referring to the cam entry table 24. by setting mult iple bits to 1, multiple conditions can be selected. post243: the cam entry table 24 is referred in port 0 reception. post242: the cam entry table 24 is referred in port 0 to 1 relay. post241: the cam entry table 24 is referred in port 1 reception. post240: the cam entry table 24 is referred in port 1 to 0 relay. 27 to 24 post253 to post250 all 0 r/w these bits set the conditions for referring to the cam entry table 25. by setting mult iple bits to 1, multiple conditions can be selected. post253: the cam entry table 25 is referred in port 0 reception. post252: the cam entry table 25 is referred in port 0 to 1 relay. post251: the cam entry table 25 is referred in port 1 reception. post250: the cam entry table 25 is referred in port 1 to 0 relay.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 696 of 950 rej09b0079-0200 bit bit name initial value r/w description 23 to 20 post263 to post260 all 0 r/w these bits set the conditions for referring to the cam entry table 26. by setting mult iple bits to 1, multiple conditions can be selected. post263: the cam entry table 26 is referred in port 0 reception. post262: the cam entry table 26 is referred in port 0 to 1 relay. post261: the cam entry table 26 is referred in port 1 reception. post260: the cam entry table 26 is referred in port 1 to 0 relay. 19 to 16 post273 to post270 all 0 r/w these bits set the conditions for referring to the cam entry table 27. by setting mult iple bits to 1, multiple conditions can be selected. post273: the cam entry table 27 is referred in port 0 reception. post272: the cam entry table 27 is referred in port 0 to 1 relay. post271: the cam entry table 27 is referred in port 1 reception. post270: the cam entry table 27 is referred in port 1 to 0 relay. 15 to 12 post283 to post280 all 0 r/w these bits set the conditions for referring to the cam entry table 28. by setting mult iple bits to 1, multiple conditions can be selected. post283: the cam entry table 28 is referred in port 0 reception. post282: the cam entry table 28 is referred in port 0 to 1 relay. post281: the cam entry table 28 is referred in port 1 reception. post280: the cam entry table 28 is referred in port 1 to 0 relay.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 697 of 950 rej09b0079-0200 bit bit name initial value r/w description 11 to 8 post293 to post290 all 0 r/w these bits set the conditions for referring to the cam entry table 29. by setting mult iple bits to 1, multiple conditions can be selected. post293: the cam entry table 29 is referred in port 0 reception. post292: the cam entry table 29 is referred in port 0 to 1 relay. post291: the cam entry table 29 is referred in port 1 reception. post290: the cam entry table 29 is referred in port 1 to 0 relay. 7 to 4 post303 to post300 all 0 r/w these bits set the conditions for referring to the cam entry table 30. by setting mult iple bits to 1, multiple conditions can be selected. post303: the cam entry table 30 is referred in port 0 reception. post302: the cam entry table 30 is referred in port 0 to 1 relay. post301: the cam entry table 30 is referred in port 1 reception. post300: the cam entry table 30 is referred in port 1 to 0 relay. 3 to 0 post313 to post310 all 0 r/w these bits set the conditions for referring to the cam entry table 31. by setting mult iple bits to 1, multiple conditions can be selected. post313: the cam entry table 31 is referred in port 0 reception. post312: the cam entry table 31 is referred in port 0 to 1 relay. post311: the cam entry table 31 is referred in port 1 reception. post310: the cam entry table 31 is referred in port 1 to 0 relay.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 698 of 950 rej09b0079-0200 18.3.44 cam entry table 0 to 31 h registers (tsu_adrh0 to tsu_adrh31) tsu_adrh0 to tsu_adrh31 are entry tables referred by the cam in reception and relay. this register sets the upper 32 bits of the 48-bit ma c address. maximum 32 entries of mac addresses can be registered. to refer to input signals on the camsen0 and camsen 1 pins, do not set the same mac address set by this register to the entry tables of the external cam. bit bit name initial value r/w description 31 to 0 adrhn31 to adrhn0 (n: 0 to 31) all 0 r/w mac address bit these bits set the upper 32 bits of the mac address. when the mac address is 01-23-45-67-89-ab (displayed in hexadecimal), h 01234567 is set to this register. notes: set the cam entry table as follows: 1. check that the adsbsy bit in tsu_adsbsy is cleared to 0. 2. set the upper 32 bits of the ma c address by tsu_adrh0 to tsu_adrh31. 3. set the lower 16 bits of the mac address by tsu_adrl0 to tsu_adrl31.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 699 of 950 rej09b0079-0200 18.3.45 cam entry table 0 to 31 l registers (tsu_adrl0 to tsu_adrl31) tsu_adrl0 to tsu_adrl31 are entry tables referr ed by the cam in reception and relay. this register sets the lower 16 bits of the 48-bit ma c address. maximum 32 entries of mac addresses can be registered. to refer to input signals on the camsen0 and camsen 1 pins, do not set the same mac address set by this register to the entry tables of the external cam. bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 0 adrln15 to adrln0 (n: 0 to 31) all 0 r/w mac address bit these bits set the lower 16 bits of the mac address. when the mac address is 01-23-45-67-89-ab (displayed in hexadecimal), h 000089ab is set to this register. notes: set the cam entry table as follows: 1. check that the adsbsy bit in tsu_adsbsy is cleared to 0. 2. set the upper 32 bits of the ma c address by tsu_adrh0 to tsu_adrh31. 3. set the lower 16 bits of the mac address by tsu_adrl0 to tsu_adrl31. 18.3.46 transmit frame counter register (port 0) (normal transmission only) (txnlcr0) txnlcr0 is a 32-bit counter indi cating the number of frames su ccessfully transmitted in mac- 0. when the value in this register reaches h'f fffffff, the count is halted . the counter value is cleared to 0 by a read to this regist er. this register cannot be written. bit bit name initial value r/w description 31 to 0 ntc031 to ntc000 all 0 r port 0 transmit frame counter bit these bits indicate the number of frames successfully transmitted.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 700 of 950 rej09b0079-0200 18.3.47 transmit frame counter register (port 0) (normal and error transmission) (txalcr0) txalcr0 is a 32-bit counter i ndicating the number of frames successfully tr ansmitted and frames transmitted with error in mac-0. when th e value in this register reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a read to this register. this register cannot be written. bit bit name initial value r/w description 31 to 0 tc031 to tc000 all 0 r port 0 transmit frame counter bit these bits indicate the number of frames successfully transmitted and frames transmitted with error. 18.3.48 receive frame counter register (por t 0) (normal recept ion only) (rxnlcr0) rxnlcr0 is a 32-bit counter indi cating the number of frames su ccessfully received in mac-0. when the value in this register reaches h'ffffff ff, the count is halted. the counter value is cleared to 0 by a read to this regist er. this register cannot be written. bit bit name initial value r/w description 31 to 0 nrc031 to nrc000 all 0 r port 0 receive frame counter bit these bits indicate the number of frames successfully received.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 701 of 950 rej09b0079-0200 18.3.49 receive frame counter register (port 0) (normal and error reception) (rxalcr0) rxalcr0 is a 32-bit counter in dicating the number of frames successfully received and frames received with error in mac-0. wh en the value in this register reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a read to this register. this register cannot be written. bit bit name initial value r/w description 31 to 0 rc031 to rc000 all 0 r port 0 receive frame counter bit these bits indicate the number of frames successfully received and frames received with error. 18.3.50 relay frame counter register (port 1 to 0) (normal relay only) (fwnlcr0) fwnlcr0 is a 32-bit counter indica ting the number of fra mes successfully relayed in port 1 to 0 relay operations. when the value in this regist er reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a read to this register. this register cannot be written. bit bit name initial value r/w description 31 to 0 nfc031 to nfc000 all 0 r port 1 to 0 relay frame counter bit these bits indicate the number of frames successfully relayed.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 702 of 950 rej09b0079-0200 18.3.51 relay frame counter register (port 1 to 0) (normal and error relay) (fwalcr0) fwalcr0 is a 32-bit counter in dicating the number of frames successfully relayed and frames relayed with error in port 1 to 0 relay operatio ns. when the value in this register reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a read to this register. this register cannot be written. bit bit name initial value r/w description 31 to 0 fc031 to fc000 all 0 r port 1 to 0 relay frame counter bit these bits indicate the number of frames successfully relayed and frames relayed with error. 18.3.52 transmit frame counter register (port 1) (normal transmission only) (txnlcr1) txnlcr1 is a 32-bit counter indi cating the number of frames su ccessfully transmitted in mac- 1. when the value in this register reaches h'f fffffff, the count is halted . the counter value is cleared to 0 by a read to this regist er. this register cannot be written. bit bit name initial value r/w description 31 to 0 ntc131 to ntc100 all 0 r port 1 transmit frame counter bit these bits indicate the number of frames successfully transmitted.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 703 of 950 rej09b0079-0200 18.3.53 transmit frame counter register (port 1) (normal and error transmission) (txalcr1) txalcr1 is a 32-bit counter i ndicating the number of frames successfully transmitted and frames transmitted with error in mac-1. when th e value in this register reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a read to this register. this register cannot be written. bit bit name initial value r/w description 31 to 0 tc131 to tc100 all 0 r port 1 transmit frame counter bit these bits indicate the number of frames successfully transmitted and frames transmitted with error. 18.3.54 receive frame counter register (por t 1) (normal recept ion only) (rxnlcr1) rxnlcr1 is a 32-bit counter indi cating the number of frames su ccessfully received in mac-1. when the value in this register reaches h'ffffff ff, the count is halted. the counter value is cleared to 0 by a read to this regist er. this register cannot be written. bit bit name initial value r/w description 31 to 0 nrc131 to nrc100 all 0 r port 1 receive frame counter bit these bits indicate the number of frames successfully received.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 704 of 950 rej09b0079-0200 18.3.55 receive frame counter register (port 1) (normal and error reception) (rxalcr1) rxalcr1 is a 32-bit counter in dicating the number of frames successfully received and frames received with error in mac-1. when the value in this register reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a read to this register. this register cannot be written. bit bit name initial value r/w description 31 to 0 rc131 to rc100 all 0 r port 1 receive frame counter bit these bits indicate the number of frames successfully received and frames received with error. 18.3.56 relay frame counter register (port 0 to 1) (normal relay only) (fwnlcr1) fwnlcr1 is a 32-bit counter indicat ing the number of fra mes successfully relayed in port 0 to 1 relay operations. when the value in this regist er reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a read to this register. this register cannot be written. bit bit name initial value r/w description 31 to 0 nfc131 to nfc100 all 0 r port 0 to 1 relay frame counter bit these bits indicate the number of frames successfully relayed.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 705 of 950 rej09b0079-0200 18.3.57 relay frame counter register (port 0 to 1) (normal and error relay) (fwalcr1) fwalcr1 is a 32-bit counter in dicating the number of frames successfully relayed and frames relayed with error in port 0 to 1 relay operatio ns. when the value in this register reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a read to this register. this register cannot be written. bit bit name initial value r/w description 31 to 0 fc131 to fc100 all 0 r port 0 to 1 relay frame counter bit these bits indicate the number of frames successfully relayed and frames relayed with error.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 706 of 950 rej09b0079-0200 18.4 operation the following outlines the operations of the ethernet controller (etherc). automatic ethernet frame tran sfer function by hardware: each mac controller can transmit and receive independently using two ports of mac controllers. furthermore, relay between the two mac controllers can be performed by hardware using the on-chip tsu of the etherc. tsu selects one of the following processes depending on the mac address of the destination of the ethernet frame input to the mac controller according to on the settings of the cam and registers tsu_fwsl0/1, and tsu_fwslc; 1) reception, 2) relay, 3) reception and relay, and 4) discard. this sett ing can be performed independently for each port at the receive and relay sides by means of registers tsu_ten and tsu_post1 to tsu_post4. it also has a 6- kbyte tsu fifo for temporarily retaining the frames relayed. this tsu fifo can vary capacity allotment with port 0 to 1 transfer and port 1 to 0 transfer using the tsu fi fo size select register (tsu_fcm). tsu fifo overflow prevention function: by supporting relay operations, the mac controller needs to transmit relay frames other than tran smit frames requested by the e-dmac normally. arbitration is carried out between these two frames. the procedure of arbitration is specified by registers tsu_prisl0 and tsu_prisl1. it has a function which relays frames of the tsu fifo with priority when the using rate of the tsu fifo exceeds the value set by registers tsu_prisl0 and tsu_prisl1, thus preven ting frame losses by tsu fifo overflow. qos (ieee802.1q) frame transmit/receive, relay function: qos frames can be transmitted and received. at the using relay function, if th e ethernet device connect ed to one of the mac controllers cannot transmit/receive qos frames, th is lsi can convert to the normal ieee802.3 frames and relay it. figure 18.2 shows the data path and outline of various settings.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 707 of 950 rej09b0079-0200 tsu etherc phy-0 phy-1 edmac-0 cam control relay enable tsu_fwen0 tsu fifo (1 to 0) tsu fifo (0 to 1) (reference setting: tsu_ten and tsu_fwslc) cam entry table (32 entries 48 bits) transmission enable te (ecmr1) = 1 transmission enable te (ecmr0) = 1 reception enable re (ecmr1) = 1 reception enable re (ecmr0) = 1 external cam i/f determination of priority tsu_prisl1 cam reference cam reference cam reference determination of priority tsu_prisl0 cam reference edmac-1 camsen pin mac-0 mac-1 relay enable tsu_fwen1 figure 18.2 etherc data path and various settings 18.4.1 transmission the etherc transmitter assembles the transmit data on the frame and outputs to mii when there is a transmit request from the e-dmac. the data tran smitted via the mii is transmitted to the lines by phy-lsi. figure 18.3 shows the status change of the ether-c transmitter. this operation is the same between ports 0 and 1. the priority of the process when transmit frame from e-dmac and relay frame transmission collide can be set by the transmit/relay priority control mode register (tsu_prisl0/1).
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 708 of 950 rej09b0079-0200 fdpx fdpx hdpx hdpx collision collision collision * 2 collision * 2 error error error normal transmission notes: 1. transmission retry processing includes both jam transmission that depends on collision detection and the adjustment of transmission intervals based on the back-off algorithm. 2. transmission is retried only when data of 512 bits or less (including the preamble and sfd)is transmitted. when a collision is detected during the transmission of data greater than 512 bits, only jam is transmitted and transmission based on the back-off algorithm is not retried. legend fdpx: full-duplex hdpx: half-duplex error notification transmission halted start of transmission (preamble transmission) carrier detection carrier detection sfd transmission crc transmission data transmission carrier detection failure of 15 retransfer attempts or collision after 512-bit time retransfer processing * 1 error detection retransfer initiation carrier non-detection carrier non-detection carrier detection idle te set te reset reset figure 18.3 etherc tran smitter state transitions 1. when the transmit enable (te) bit is set, the transmitter enters th e transmit idle state. 2. when a transmit request is issued by the transmit e-dmac, the etherc sends the preamble after a transmission delay equivalent to the frame interval time. if full-duplex transfer is
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 709 of 950 rej09b0079-0200 selected, which does not require carrier detection, the preamble is sent as soon as a transmit request is issued by the e-dmac. 3. the transmitter sends the sfd, data, and crc sequentially. at the end of transmission, the transmit e-dmac generates a transmission comp lete interrupt (tc). if a collision or the carrier-not-detected state occurs during data transmission, thes e are reported as interrupt sources. 4. after waiting for the frame interval time, the tran smitter enters the idle state, and if there is more transmit data, continues transmitting. 18.4.2 reception the etherc receiver separates the frame from th e mii into preamble, sfd, data and crc, and the fields from da (destination addr ess) to the crc data are transf erred to the receive e-dmac. figure 18.4 shows the state trans itions of the etherc receiver. these operations are the same for ports 0 and 1. in frame processing during reception, cam evaluation can be referenced. (when using the cam function, refer to section 18.4.4, cam function.)
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 710 of 950 rej09b0079-0200 illegal carrier detection start of frame reception wait for sfd reception data reception crc reception destination address reception preamble detection reception halted reset error notification * re set legend sfd: start frame delimiter note: the error frame also transmits data to the buffer. end of reception receivce error detection receivce error detection error detection promiscuous and other station destination address re reset normal reception idle rx-dv negation sfd reception own destination address or broadcast or multicast or promiscuous figure 18.4 etherc r eceiver state transmissions 1. when the receive enable (re) bit is set, the receiver enters the receive idle state. 2. when an sfd (start frame delimiter) is detect ed after a receive packet preamble, the receiver starts receive processing . discards a frame with an invalid pattern. 3. in normal mode, if the destination address matches the receiver?s own address, or if broadcast or multicast transmission or promiscuou s mode is specified, the receive r starts data reception. 4. following data reception fr om the mii, the receiver carries out a crc check. the result is indicated as a status bit in the descriptor af ter the frame data has been written to memory. reports an error status in the case of an abnormality. 5. after one frame has been receiv ed, if the receive enable bit is set (re = 1) in the etherc mode register, the receiver prepares to receive the next frame.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 711 of 950 rej09b0079-0200 18.4.3 relay etherc has a function to relay frames received fr om the mii of either mac-0 or mac-1 to the other mac. when relay is enabled, frames input from the mii are sent to both the tsu fifo and receive e-dmac, and determined independently whether to receive or not by the receive e- dmac and whether to relay or not by the tsu. (refer to figure 18.2.) to execute relay, specify both mac controllers as promiscuous mode, and th e same mac address in both mac controllers (hereafter this mac address is refe rred to as mac address of this lsi). the setting of the transfer frame processing (relayed /discarded) is carried by the tsu_fwsl0 and tsu_fwsl1. frames passing the tsu fifo during relaying are sent to the phy_lsi from mac-1 in mac-0 to mac- 1 relay, from mac-0 in mac1 to mac0 relay via the mii. at this time, collision with the relay frames from the e-dmac may occur. the priority of the process when collision occurs can be set by tsu_prisl0/1. for multicast frame s and frames their destinations are other than this lsi, the cam evaluation in frame relay processing can be referenced (for details on the cam function, refer to section 18.4.4, cam function). table 18.2 shows the settings of the relay frame processing (without cam). table 18.2 transfer frame processing (without cam) name tsu-fwsl frame processing fw40/1 = 0 discarded frame for this lsi fw40/1 = 1 relayed fw30/1 = 0 discarded broadcast frame fw30/1 = 1 relayed fw20/1 = 0 discarded multicast frame fw20/1 = 1 relayed fw10/1 = 0 discarded frames to destinations other than this lsi fw10/1 = 1 relayed 18.4.4 cam function frames input to the mac are grouped into the following four types; unicast for this lsi, broadcast, multicast, and unicast to other destin ations. of this, the mac addresses of unicast for this lsi and broadcast are fixed, and determination is carried out only by register settings. consequently, only multicast and unicast to other destinations determine whether to receive or not and whether to relay or not by using the cam (u nicast frames whose destination mac addresses match this lsi are called unicast frames to this ls i, and those that do not are called unicast frames to other destinations).
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 712 of 950 rej09b0079-0200 furthermore, with the etherc, the evaluation of receive and relay of unicast to other destinations and multicast frames by using cam are performed by referencing the registered mac addresses of the cam entry table in the etherc and the cam logic connected externally via the camsen0 and camsen1 pins. by using this function, receive fifo overflow can be prevented caused by accumulation of frame data not required for r eception, and cpu processing for determining receive can be reduced. the post table is composed of 4 bits, and each bit corresponds to po rt 0 reception, port 1 reception, port 0 to 1 relay, and po rt 1 to 0 relay. when the corres ponding bit is set to 1, the cam evaluation results are used for determining re ceive and relay. in other words, when the corresponding bit of the post table is cleared to 0, receive and relay evaluation will be the same as when cam is not used shown in table 18.2. the difference between the on-chip cam entry table and externally connected cam logic lies in how the post table is set. in the internal cam entry table, there are 32 post tables (same as th e number of entries) an d the post table can be set for each entry. the internal cam entry table ha s 32 entries and 32 post tables, and the post table can be specified in each entry. the external connection cam logic conf iguration is based on pins because post tables (total of 2) ar e allocated to the camsen0 and camsen1 pins. when on-chip cam entry table is used: the on-chip cam has entry tables which can register the mac address of 32 entries, the details of which can be set by tsu_adrh0 to tsu_adrh31 and tsu_adrl0 to tsu_adrl31. the setting to enable/disable referencing of the on-chip cam entry table is carried out by th e cam entry table enable setting register which sets whether to perform cam evaluation or not, and the cam entry table post setting register for setting whether to use the cam determination re sults for determining receive or relay. when on-chip cam entry table referencin g during receive is enabled, the destination address in the frame and mac address registered in the cam en try table are compared, and it is determined whether to transfer the frames input to the mac to e-dmac (h ave e-dmac receive the frames) or discard the frames. when relaying and cam entry table referencing during relay are both enabled, whether to tran sfer or discard multicast frames and frames for destinations other than this lsi can be determined by comparing the destination address in the frame and mac address registered in the cam entry table. table 18.3 sh ows the processing method of frames (receive or discard) in mac0 to e-dmac0 and mac1 to e-dmac1 reception, while table 18.4 shows the processing for frames in mac0 to mac1 and mac1 to mac0 relay (relay or discard).
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 713 of 950 rej09b0079-0200 table 18.3 reception frame process normal mode promiscuous mode cam entry table referencing results frame mct = 0 mct = 1 mct = 0 mct = 1 frame to this lsi discarded discarded broadcast frame discarded discarded multicast frame discarded received discarded received cam hit (when addresses match) frames to destinations other than this lsi received discarded frames to this lsi received received broadcast frame received received multicast frame received discarded received discarded cam mishit (when addresses do not match) frames to destinations other than this lsi discarded received [legend] mct (bit 13 in ecmr): multicast rece ive mode (0: receive when cam mishit/ 1: receive when cam hit) table 18.4 relay frame process (with cam) frame relay function setting register bit cam hit cam mishit fw40/1 = 0 relayed discarded multicast frame fw40/1 = 1 discarded relayed fw40/1 = 0 relayed discarded frames to destinations other than this lsi fw40/1 = 1 discarded relayed note: cam can be referenced only for multicast fr ames and frames to destinations other than this lsi. the processing of frames to this lsi and broadcast frames conforms to the values of the relay function setting register regardless of cam reference. when external cam logic is used: in addition to the on-chip ca m entry table, use of the camsen0 and camsen1 pins allows referencing of evaluation results of the external cam logic connected externally to this lsi for frame processing evaluation. this function externally connects the cam logic for comparin g the destination address in r eceive frames, and receives the results of comparing destination addresses corresponding to the signals (rxd3 to rxd0) input from the mii to determine whether to receive or discard the correspond ing frame. figure 18.5
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 714 of 950 rej09b0079-0200 shows the connection example of the external cam logic while figure 18.6 shows the timing conditions of the external cam signal. etherc external cam logic this lsi external memory descriptor mii (rx-dv, rxd3 to rxd0) camsen0 or camsen1 pin phy-lsi figure 18.5 example of external cam connection the setting on whether to enable or disable the referencing of external cam logic evaluation results by the camsen0 and camsen1 pins is carried out by the transfer function setting register (common) (tsu_fwslc). when referencing of the camsen0 and camsen1 pins is enabled during receive, it is determined whether to send or discard the fr ames input from to mac- 0/1 to e-dmac0/1 (have e-dmac receive the frames) according to the value of the camsen0 or camsen1 pin. when relaying and camsen0/1 pin referencing are enabled at the same time, the transfer or discard of multicast frames and frames to destinations other than this lsi can be determined by the value of the camsen0 and camsen1 pins. table 18.5 shows the processing method (receive or discard) for frames in mac0 to e-dmac0 or mac1 to e-dmac1 reception, while table 18.6 shows the pr ocessing method (receive or discard) for frames in mac0 to mac1 or mac1 to mac relay. the external cam logic is memorized with mac addresses different from th e cam entry table in this lsi. when the mac address received from the phy matches the destin ation address memorized in the external cam logic, the camsen0 or camsen1 pi n is asserted*. ethe rc receives or discards the frames when camsen0/1 was asserted according to the settings in table 18.5. figure 18.6 shows the valid ra nge of camsen0/1 asse rtion for the corresponding receive frames.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 715 of 950 rej09b0079-0200 with etherc, before storage of receive frames in the fifo of e-dmac/tsu is started, there is a need to determine receive frame processing. the time limit for de termining this processing is within 52 clocks from rx_dv assertion. note: * do not memorize mac addresses overlapping with the internal cam entry table of this lsi during external cam logic. if the camsen0 or camsen1 pin is asserted at the same time as cam hit occurs for the in ternal cam entry table, evaluation may not performed correctly. table 18.5 receive frame process (w hen external cam logic is used) normal mode promiscuous mode camsen0 or camsen1 pin frame mct = 0 mct = 1 mct = 0 mct = 1 frame to this lsi discarded discarded broadcast frame discarded discarded multicast frame discarded received discarded received assertion (when addresses match) frames to destinations other than this lsi received discarded frames to this lsi received received broadcast frame received received multicast frame received discarded received discarded negation (when addresses do not match) frames to destinations other than this lsi discarded received [legend] mct (bit 13 in ecmr): multicast receiv e mode (0: received when cam mishit/ 1: received when cam hit)
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 716 of 950 rej09b0079-0200 table 18.6 relay frame process (w hen external cam logic is used) frame relay function setting register bit camsen0 or camsen1 pin assertion camsen0 or camsen1 pin negation fw40/1 = 0 relayed discarded multicast frame fw40/1 = 1 discarded relayed fw40/1 = 0 relayed discarded frames to destinations other than this lsi fw40/1 = 1 discarded relayed note: cam can be referenced only for multicast fr ames and frames to destinations other than this lsi. the processing of frames to this lsi and broadcast frames conforms to the values of the relay function setting register regardless of cam reference. rx-clk 1 2 3 7 8 9 10 11 12 13 50 51 52 53 rx-dv rxd3 to rxd0 camsen * sfd preamble destination address camsen signal valid range assertion above 1 clock note: * outside the valid range of the camsen signal, always set the camsen signal to low. figure 18.6 external cam signal timing
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 717 of 950 rej09b0079-0200 18.4.5 mii frame timing each mii frame timing is shown in figure 18.7. tx-clk tx-en txd3 to txd0 tx-er crs col sfd preamble data crc figure 18.7 (1) mii frame transmit timing (normal transmission) tx-clk tx-en txd3 to txd0 tx-er crs col preamble jam figure 18.7 (2) mii frame transmit timing (collision)
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 718 of 950 rej09b0079-0200 tx-clk tx-en txd3 to txd0 tx-er crs col sfd preamble data figure 18.7 (3) mii frame tran smit timing (transmit error) rx-clk rx-dv rxd3 to rxd0 rx-er preamble data crc sfd figure 18.7 (4) mii frame r eceive timing (normal reception) rx-clk rx-dv rxd3 to rxd0 rx-er preamble data xxxx sfd figure 18.7 (5) mii frame recei ve timing (reception error (1)) rx-clk rx-dv rxd3 to rxd0 rx-er xxxx 1110 xxxx figure 18.7 (6) mii fame recei ve timing (reception error (2))
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 719 of 950 rej09b0079-0200 18.4.6 accessing mii registers mii registers in the phy-lsi are accessed via this lsi?s phy interface regi ster (pir). connection is made as a serial interface in accordance with the mii frame format sp ecified in ieee802.3u. mii management frame format: the format of an mii management frame is shown in figure 18.8. to access an mii register , a management frame is impl emented by the program in accordance with the proced ures shown in mii register access procedure. access type mii management frame item number of bits read write pre 32 1..1 1..1 st 2 01 01 op 2 10 01 phyad 5 00001 00001 regad 5 rrrrr rrrrr ta 2 z0 10 data 16 d..d d..d idle x pre: st: op: phyad: regad: ta: data: idle: [legend] 32 consecutive 1s write of 01 indicating start of frame write of code indicating access type write of 0001 if the phy-lsi address is 1 (sequential write starting with the msb). this bit changes depending on the phy-lsi address. write of 0001 if the register address is 1 (sequential write starting with the msb). this bit changes depending on the phy-lsi register address. time for switching data transmission source on mii interface (a) write: 10 written (b) read: bus release (notation: z0) performed 16-bit data. sequential write or read from msb (a) write: 16-bit data write (b) read: 16-bit data read wait time until next mii management format input (a) write: independent bus release (notation: x) performed (b) read: bus already released in ta; control unnecessary figure 18.8 mii management frame format
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 720 of 950 rej09b0079-0200 mii register access procedure: the program accesses mii regi sters via the phy interface register (pir). access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data read, bus release, and independent bus release. figure 18.9 show s the mii register access timing. the timing will differ depending on the phy-lsi type. mdc (1) (1) (2) (3) mdo (2) (3) write to phy interface register 1-bit data write timing relationship mmd = 1 mdo = write data mdc = 0 mmd = 1 mdo = write data mdc = 1 write to phy interface register mmd = 1 mdo = write data mdc = 0 write to phy interface register figure 18.9 (1) 1-bit data write flowchart
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 721 of 950 rej09b0079-0200 mdc (1) (1) (2) (3) write to phy interface register mmd = 0 mdc = 0 bus release timing relationship mdo (2) write to phy interface register mmd = 0 mdc = 1 (3) write to phy interface register mmd = 0 mdc = 0 figure 18.9 (2) bus release flowchart (ta in read in figure 18.8) mdc (1) (1) (2) (3) write to phy interface register mmd = 0 mdc = 1 1-bit data read timing relationship (3) write to phy interface register mmd = 0 mdc = 0 (2) read from phy interface register mmd = 0 mmc = 1 mdi is read data mdi figure 18.9 (3) 1-bit data read flowchart
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 722 of 950 rej09b0079-0200 mdc (1) (1) write to phy interface register mmd = 0 mdc = 0 independent bus release timing relationship mdo figure 18.9 (4) independent bus release flowchart (idle in write in figure 18.8) 18.4.7 magic packet detection the etherc has a magic packet detection function. this function provides a wake-on-lan (wol) facility that activates various peripheral devices connected to a lan from the host device or other source. this makes it possible to constr uct a system in which a peripheral device receives a magic packet sent from the host device or othe r source, and activates itself. when the magic packet is detected, data is stored in the fifo of the e-dmac by the broadcast packet that has received data previously and the etherc is notifie d of the receiving status . to return to normal operation from the interrupt processing, initialize the etherc and e-dmac by using arst bit in the software reset register (arstr). with a magic packet, reception is performed regardless of the destin ation address. as a result, this function is valid, and the wol pin enabled, only in the case of a match with the destination address specified by the format in the magic packet. further information on magic packets can be found in the technical documentation published by amd corporation. the procedure for using the wol func tion with this lsi is as follows. 1. disable interrupt source output by means of the various interrupt enable/mask registers. 2. set the magic packet detection enable bit (mpde) in the etherc mode register (ecmr). 3. set the magic packet detection interrupt enable bit (mpdip) in the etherc interrupt enable register (ecsipr) to the enable setting. 4. if necessary, set the cpu operating mode to sleep mode or set peripheral modules to module standby mode. 5. when a magic packet is detected, an interrupt is sent to the cpu. the wol pin notifies peripheral lsis that the magic packet has been detected.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 723 of 950 rej09b0079-0200 18.4.8 operation by ipg setting the etherc has a function to chan ge the non-transmission period ipg (inter packet gap) between transmit frames. by changing the set values of th e ipg setting register (i pgr), the transmission efficiency can be raised and lowered from the st andard value. ipg settings are prescribed in ieee802.3 standards. when changing settings, ad equately check that th e respective devices can operate smoothly on the same network. ipg * [1] [2] [3] [4] [1] [2] [3] [4] [5] ...... ...... packet note: * ipg may be longer than the set value, depending on the state of the line and the system bus. case a (short ipg) case b (long ipg) figure 18.10 changing ipg and transmission efficiency 18.4.9 direction for ieee802.1q qtag the etherc supports ieee802.1q frame processing. it can add or delete qtags to or from frames processed in relay. this function can also transm it and receive qos frames. during relaying, if the ethernet device connected to one mac controller cannot transmit or receive qos frames, it can be converted to the normal ieee802.3 frames and relayed in this lsi. whether to add or delete qtags is determined by the added qtag value set register (tsu_adqt0/1). figure 18.11 shows an outline of the qtag add function while figure 18.12 shows the comparison between the normal ethernet frames and ieee802.1q frames (with qtag). for details on setting qtag, refer to the specifications on qtag contro l specified in ieee802.1q.
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 724 of 950 rej09b0079-0200 tsu qtag deleting qtag adding frame conversion mechanism 802.1q supporting network 802.1q unsupporting network 802.1q conforming frame (with qtag) normal frame (without qtag) mac-0 etherc this lsi mac-1 figure 18.11 diagram of qtag additional functions da sa l/t data fcs 1 oct 6 oct 6 oct 2 oct 46 to 1500 oct 4 oct l/t 2 oct 42 to 1500 oct qtag 4oct data da sa fcs 6 oct 6 oct 4 oct 7 normal ethernet frame (without qtag) 802.1q conforming frame (with qtag) oct h extension code (fixed) ' 81 h'00 prt vid cfi 8bit 8bit 3bit 1bit 12 bit pr: legend: sfd: da: sa: l/t: fcs: preamble qtag setting (tsu_adqt0/1) prt: cfi: vid: priority level setting fixed at 0 v-lan id setting start frame delimiter destination address source address length or type frame check sequence sfd 1oct 7 oct pr sfd pr figure 18.12 comparison of normal ethernet frame and ieee802.1q frame (with qtag)
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 725 of 950 rej09b0079-0200 18.5 connection to lsi figure 18.13 shows the example of connection to a dp83847 (national semiconductor corporation). tx-er etxd3 etxd2 etxd1 etxd0 tx-en tx-clk mdc mdio erxd3 erxd2 erxd1 erxd0 rx-clk crs col rx-dv rx-er tx_er txd[3] txd[2] txd[1] txd[0] tx_en tx_clk mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv rx_er this lsi dp83847 mii (media independent interface) figure 18.13 example of connection to dp83847
section 18 ethernet controller (etherc) rev. 2.00 dec. 07, 2005 page 726 of 950 rej09b0079-0200
section 19 ethernet controller direct memory access controller (e-dmac) edmas20b_000020020900 rev. 2.00 dec. 07, 2005 page 727 of 950 rej09b0079-0200 section 19 ethernet controller direct memory access controller (e-dmac) this lsi has an on-chip two-channel direct memory access controller (e-dmac0/1) directly connected to the ethernet controller (etherc). by using the dmac contained in the e-dmac, the e-dmac transfers transmit/receive data between th e transmit/receive fifo in the e-dmac and a user-specified data storage des tination (buffer) by dma transfer . at dma transfer, information referenced by the e-dmac is referred to as a tr ansmit/receive descriptor, and the user places this descriptor in memory. this function reduces the load on the cpu and en ables efficient data transfer control to be achieved. the e-dmac0 and e-dmac1 control the data transmission/reception from the mac-0 and mac-1 of etherc respectively. (hereafter the channel controll ed by the e-dmac0 is channel 0. the channel controlled by the e-dmac1 is channel 1.) figure 19.1 shows the configuration of the e-dmac, and the descriptors and transmit/receive buffers in memory. 19.1 features the e-dmac has the following features: ? contains two-chan nel independent transmit/receive dmac ? the load on the cpu is reduced by means of a descriptor management system ? transmit/receive frame status inform ation is indicated in descriptors ? achieves efficient system bus utilization thro ugh the use of dma bloc k transfer (16-byte units) ? supports single-frame/single-de scriptor operation and single-f rame/multi-frame (multi-buffer) operation note: the e-dmac cannot access peripheral modules.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 728 of 950 rej09b0079-0200 e-dmac1 transmit fifo receive fifo transmit fifo receive fifo descriptor information transmit dmac transmit descriptor 1 transmit buffer 1 receive buffer 1 transmit buffer 0 receive buffer 0 receive descriptor 1 external bus interface internal bus internal bus interface internal bus interface this lsi transmit descriptor 0 receive descriptor 0 external memory etherc descriptor information receive dmac descriptor information receive dmac descriptor information transmit dmac e-dmac0 figure 19.1 configuration of e- dmac, and descriptors and buffers 19.2 register descriptions the e-dmac has the following re gisters. the number at the en d of the register abbreviation represents the number of corresponding e-dmac (e-dmac0 or e-dmac1). in this section, some numbers are not mentioned. for addresses an d access sizes of these registers, see section 24, list of registers. channel 0: ? e-dmac mode register (edmr0) ? e-dmac transmit request register (edtrr0) ? e-dmac receive request register (edrrr0) ? transmit descriptor list address register (tdlar0) ? receive descriptor list ad dress register (rdlar0) ? etherc/e-dmac status register (eesr0) ? etherc/e-dmac status interrupt permission register (eesipr0) ? transmit/receive status copy enable register (trscer0)
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 729 of 950 rej09b0079-0200 ? receive missed-frame coun ter register (rmfcr0) ? transmit fifo threshold register (tftr0) ? fifo depth register (fdr0) ? receiving method control register (rmcr0) ? e-dmac operation control register (edocr0) ? receive buffer write addr ess register (rbwar0) ? receive descriptor fetch ad dress register (rdfar0) ? transmit buffer read address register (tbrar0) ? transmit descriptor fetch address register (tdfar0) ? overflow alert fifo threshold register (fcftr0) ? transmit interrupt register (trimd0) channel 1: ? e-dmac mode register (edmr1) ? e-dmac transmit request register (edtrr1) ? e-dmac receive request register (edrrr1) ? transmit descriptor list address register (tdlar1) ? receive descriptor list ad dress register (rdlar1) ? etherc/e-dmac status register (eesr1) ? etherc/e-dmac status interrupt permission register (eesipr1) ? transmit/receive status copy enable register (trscer1) ? receive missed-frame coun ter register (rmfcr1) ? transmit fifo threshold register (tftr1) ? fifo depth register (fdr1) ? receiving method control register (rmcr1) ? e-dmac operation control register (edocr1) ? receive buffer write addr ess register (rbwar1) ? receive descriptor fetch ad dress register (rdfar1) ? transmit buffer read address register (tbrar1) ? transmit descriptor fetch address register (tdfar1) ? overflow alert fifo threshold register (fcftr1) ? transmit interrupt register (trimd1)
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 730 of 950 rej09b0079-0200 19.2.1 e-dmac mode register (edmr) edmr is a 32-bit readable/writable register that specifies e-dmac resetti ng and transmit/receive descriptor length. this register is to be set be fore the tr bit in edtrr or the rr bit in edrrr is set to 1. if a software reset is executed with th is register during data transmission, abnormal data may be transmitted on the line. execute a software reset with this register before specifying transmit/receive descriptor length and modifying th e settings of tdlar, rdlar, and so forth, the setting of ecmr (etherc mode register), and the settings of registers related to e-dmac and etherc operation. the time required for completi on of etherc and e-dmac initialization from a software reset with this register is 64 cycles of the in ternal bus clock b . therefore, registers of the etherc and e-dmac should be accessed afte r 64 cycles of the internal bus clock b has elapsed. bit bit name initial value r/w description 31 to 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 4 dl1 dl0 0 0 r/w r/w descriptor length these bits specify the descr iptor length. (see section 19.3.1, descriptors and descriptor list.) 00: 16 bytes 01: 32 bytes 10: 64 bytes 11: reserved (setting prohibited) 3 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 731 of 950 rej09b0079-0200 bit bit name initial value r/w description 0 swr 0 r/w software reset by writing 1 to this bit, the registers of the e-dmac other than tdlar, rdlar, and rmfcr and the registers of etherc other than tsu-related registers can be initialized. (the registers whose names start with tsu_ are not initialized.) the swr bit in edmr0 initializes the edmac0 and mac-0 registers in the etherc. the swr bit in edmr1 initializes edmac1 and mac-1 registers in t he etherc. when transfer operation is enabled by specifying the relay enable register (port 0 to 1) (tsu_fwen0) and the relay enable register (port 1 to 0) (tsu_fwen1) in the etherc, software reset should not be performed by using this bit. while a software reset is issued (64 cycles of the internal bus clock b ), accesses to the all ethernet-related regi sters are prohibited. software reset period (example): when b = 100 mhz: 0.64 s when b = 66 mhz: 0.97 s when b = 50 mhz: 1.28 s when b = 33 mhz: 1.94 s this bit is always read as 0. 1: etherc and e-dmac are reset (when writing) 19.2.2 e-dmac transmit request register (edtrr) edtrr is a 32-bit readable/writable register that issues transmit directives to the e-dmac. after writing 1 to the tr bit in this register, the e-dm ac reads the transmit descriptor at the address specified by tdlar. if the tact bit of this descri ptor is set to 1 (valid), transmit dma transfer by the e-dmac starts. when dma transfer based on the first transmit descriptor is completed, the e-dmac reads the next transmit descriptor. if the tact bit of that descriptor is set to 1 (valid), the e-dmac continues transmit dma operation. if the tact bit of a transmit descriptor is cleared to 0 (invalid), the e-dmac clears th e tr bit and stops transmit dmac operation. for details of writing to the tr bit, see section 19.4.1, using of edtrr and edrrr.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 732 of 950 rej09b0079-0200 bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 tr 0 r/w transmit request 0: transmission-halted state. writing 0 does not stop transmission. termination of transmission is controlled by the tact bit of the transmit descriptor. 1: transmit dma operation being performed by the e- dmac. after writing 1 to this bit, the e-dmac starts reading a transmit descriptor. 19.2.3 e-dmac receive request register (edrrr) edrrr is a 32-bit readable/writable register that issues receive di rectives to the e-dmac. after writing 1 to the rr bit in this register, the e-dm ac reads the receive desc riptor at the address specified by rdlar. if the ract bit of this descri ptor is set to 1 (valid), and the receive fifo holds a receive frame, the e-dmac starts receive dma transfer. when dma transfer based on the first receive descriptor is completed, the e- dmac reads the next receive descriptor. if the ract bit of that descriptor is set to 1 (valid ), the e-dmac continues receive dma operation. however, if the receive fifo holds no receive data, the e-dmac places receive dma operation in the standby state. if the ract bit of the recei ve descriptor is cleared to 0 (invalid), the e- dmac clears the rr bit and st ops receive dmac operation. for details of writing to the rr bit, see section 19.4.1, using of edtrr and edrrr.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 733 of 950 rej09b0079-0200 bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 rr 0 r/w receive request 0: the receive function is disabled * 1: a receive descriptor is read, and the e-dmac is ready to receive note: * if the receive function is disabled during fr ame reception, write-back is not performed successfully to the receive descriptor. follo wing pointers to read a receive descriptor become abnormal and the e-dmac can not operate successfully. in this case, to make the e-dmac reception enabled again, execute a software reset by the swr bit in edmr0 (edmr1). to make the e-dmac re ception disabled without executing a software reset, specify the re bit in ec mr0 (ecmr1). next, after the e_dmac has completed the reception and write-back to the receive descriptor has been confirmed, disable the receive function of this register. 19.2.4 transmit descriptor li st address register (tdlar) tdlar is a 32-bit readable/writable register that specifies the start address of the transmit descriptor list. descriptors have a boundary configuration in accordance with the descriptor length indicated by the dl bit in edmr. this register must not be written to during transmission. modifications to this register should only be made while transmission is disabled by the tr bit ( = 0) in the e-dmac transmit request register (edtrr). bit bit name initial value r/w description 31 to 0 tdla31 to tdla0 all 0 r/w transmit descriptor start address the lower bits are set as follows according to the specified descriptor length. 16-byte boundary: tdla3 and tdla0 = 0000 32-byte boundary: tdla4 and tdla0 = 00000 64-byte boundary: tdla5 and tdla0 = 000000
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 734 of 950 rej09b0079-0200 19.2.5 receive descriptor li st address register (rdlar) rdlar is a 32-bit readab le/writable register that specifies the start address of the receive descriptor list. descriptors have a boundary configuration in accordance with the descriptor length indicated by the dl bit in edmr. this register must not be written to during reception. modifications to this register should only be made while reception is disabled by the rr bit ( = 0) in the e-dmac receive request register (edrrr). bit bit name initial value r/w description 31 to 0 rdla31 to rdla0 all 0 r/w receive descriptor start address the lower bits are set as follows according to the specified descriptor length. 16-byte boundary: rdla3 and rdla0 = 0000 32-byte boundary: rdla4 and rdla0 = 00000 64-byte boundary: rdla5 and rdla0 = 000000 19.2.6 etherc/e-dmac st atus register (eesr) eesr is a 32-bit readable/writable register that shows communications status information on the e-dmac in combination with the etherc. the informat ion in this register is reported in the form of interrupt sources. individual bits are cleared by writing 1 (however, bit 22 (eci) is a read-only bit and not to be cleared by writing 1) and are not affected by writing 0. ea ch interrupt source can also be masked by means of the corresponding bit in the etherc/e-dmac status interrupt permission register (eesipr). the interrupts generated by this register are eint0 for channel 0 and eint1 for channel 1. for interrupt priorities, see section 8, interrupt controller (intc) and section 8.3.5, interrupt exception handling and priority. the eint2 is an interrupt generated by the tsu_fnsr in the etherc. bit bit name initial value r/w description 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 735 of 950 rej09b0079-0200 bit bit name initial value r/w description 30 twb 0 r/w write-back complete indicates that write-back from the e-dmac to the corresponding descriptor has completed. this operation is enabled when the tis bit in trimd is set to 1. 0: write-back has not completed, or no transmission directive 1: write-back has completed 29 to 27 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 26 tabt 0 r/w transmit abort detection indicates that the etherc aborts transmitting a frame because of failures during transmitting the frame. 0: frame transmission has not been aborted or no transmit directive 1: frame transmit has been aborted 25 rabt 0 r/w receive abort detection indicates that the etherc aborts receiving a frame because of failures during receiving the frame. 0: frame reception has not been aborted or no receive directive 1: frame receive has been aborted 24 rfcof 0 r/w receive frame counter overflow indicates that the receiv e fifo frame counter has overflowed. 0: receive frame counter has not overflowed 1: receive frame counter overflows
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 736 of 950 rej09b0079-0200 bit bit name initial value r/w description 23 ade 0 r/w address error indicates that the memory address that the e-dmac tried to transfer is found illegal. 0: illegal memory address not detected (normal operation) 1: illegal memory address detected note: when an address error is detected, the e-dmac halts transmitting/receiving. to resume the operation, execute a software reset with the swr bit in edmr. 22 eci 0 r etherc status register interrupt source this bit is a read-only bit. when the source of an ecsr interrupt in the etherc is cleared, this bit is also cleared. 0: etherc status interrupt source has not been detected 1: etherc status interrupt source has been detected 21 tc 0 r/w frame transmit complete indicates that all the data specified by the transmit descriptor has been transmitt ed from the etherc. this bit is set to 1, assu ming the completion of transmission, when transmission of one frame is completed in single-frame/single-descriptor operation or when the last data of a frame has been transmitted and the transmit descriptor valid bit (tact) of the next descriptor is not set in for the processing of multi-buffer frame based on single-frame/multi- descriptor operation. after frame transmission, the e- dmac writes the transmission status back to the relevant descriptor. 0: transfer not complete, or no transfer directive 1: transfer complete
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 737 of 950 rej09b0079-0200 bit bit name initial value r/w description 20 tde 0 r/w transmit descriptor empty indicates that the transmit descriptor valid bit (tact) of a transmit descriptor read by the e-dmac is not set if the previous descriptor does not represent the end of a frame for the processing of multi-buffer frame based on the single-frame/multi-descriptor. as a result, an incomplete frame may be transmitted. 0: transmit descriptor active bit tact = 1 detected 1: transmit descriptor active bit tact = 0 detected when transmission descriptor empty (tde = 1) occurs, execute a software reset and initiate transmission. in this case, the address that is stored in the transmit descriptor list address register (tdlar) is transmitted first. 19 tfuf 0 r/w transmit fifo underflow indicates that underflow has occurred in the transmit fifo during frame transmission. incomplete data is sent onto the line. 0: underflow has not occurred 1: underflow has occurred 18 fr 0 r/w frame reception indicates that a frame has been received and the receive descriptor has been updated. this bit is set to 1 each time a frame is received. 0: frame not received 1: frame received
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 738 of 950 rej09b0079-0200 bit bit name initial value r/w description 17 rde 0 r/w receive descriptor empty indicates that the ract bit of a receive descriptor read by the e-dmac for receive dma is cleared to 0 (invalid). when receive descriptor empty (rde = 1) occurs, reception can be resumed by setting the ract bit (cleared to 0) of the receive descriptor to 1 and writing 1 to the rr bit in edrrr. 0: receive descriptor active bit ract = 1 detected 1: receive descriptor active bit ract = 0 detected 16 rfof 0 r/w receive fifo overflow indicates that the receive fifo has overflowed during frame reception. 0: overflow has not occurred 1: overflow has occurred 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 cnd 0 r/w carrier not detect indicates the carrier detecti on status during preamble transmission. 0: a carrier is detected when transmission starts 1: a carrier is not detected 10 dlc 0 r/w detect loss of carrier indicates that loss of t he carrier has been detected during frame transmission. 0: loss of carrier not detected 1: loss of carrier detected 9 cd 0 r/w delayed collision detect indicates that a delayed collision has been detected during frame transmission. 0: delayed collision not detected 1: delayed collision detected
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 739 of 950 rej09b0079-0200 bit bit name initial value r/w description 8 tro 0 r/w transmit retry over indicates that a retry-over condition has occurred during frame transmission. total 16 transmission retries including 15 retries based on the back-off algorithm are failed after the etherc transmission starts. 0: transmit retry-over condition not detected 1: transmit retry-over condition detected 7 rmaf 0 r/w receive multicast address frame 0: multicast address frame has not been received 1: multicast address frame has been received 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 rrf 0 r/w receive residual-bit frame 0: residual-bit frame has not been received 1: residual-bit frame has been received 3 rtlf 0 r/w rece ive too-long frame indicates that the frame more than the number of receive frame length upper limit set by rflr has been received. 0: too-long frame has not been received 1: too-long frame has been received 2 rtsf 0 r/w receive too-short frame indicates that a frame of fewer than 64 bytes has been received. 0: too-short frame has not been received 1: too-short frame has been received 1 pre 0 r/w phy-lsi receive error 0: phy-lsi receive error not detected 1: phy-lsi receive error detected 0 cerf 0 r/w crc error on received frame 0: crc error not detected 1: crc error detected
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 740 of 950 rej09b0079-0200 19.2.7 etherc/e-dmac st atus interrupt permissi on register (eesipr) eesipr is a 32-bit readable/writable register that enables interrupts corresponding to individual bits in the etherc/e-dmac status register (eesr) . an interrupt is enabled by writing 1 to the corresponding bit. bit bit name initial value r/w description 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30 twbip 0 r/w write-back complete interrupt enable 0: write-back complete interrupt is disabled 1: write-back complete interrupt is enabled 29 to 27 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 26 tabtip 0 r/w transmit abort detection interrupt enable 0: transmit abort detection interrupt is disabled 1: transmit abort detection interrupt is enabled 25 rabtip 0 r/w receive abort detection interrupt enable 0: receive abort detection interrupt is disabled 1: receive abort detection interrupt is enabled 24 rfcofip 0 r/w receive frame c ounter overflow interrupt enable 0: receive frame counter overflow interrupt is disabled 1: receive frame counter overflow interrupt is enabled 23 adeip 0 r/w address error interrupt enable 0: address error interrupt is disabled 1: address error interrupt is enabled 22 eciip 0 r/w etherc status register interrupt enable 0: etherc status interrupt is disabled 1: etherc status interrupt is enabled 21 tcip 0 r/w frame transmit complete interrupt enable 0: frame transmit complete interrupt is disabled 1: frame transmit complete interrupt is enabled
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 741 of 950 rej09b0079-0200 bit bit name initial value r/w description 20 tdeip 0 r/w transmit descriptor empty interrupt enable 0: transmit descriptor empty interrupt is disabled 1: transmit descriptor empty interrupt is enabled 19 tfufip 0 r/w transmit fifo underflow interrupt enable 0: underflow interrupt is disabled 1: underflow interrupt is enabled 18 frip 0 r/w frame received interrupt enable 0: frame received interrupt is disabled 1: frame received interrupt is enabled 17 rdeip 0 r/w receive descriptor empty interrupt enable 0: receive descriptor empty interrupt is disabled 1: receive descriptor empty interrupt is enabled 16 rfofip 0 r/w receive fifo overflow interrupt enable 0: receive fifo overflow interrupt is disabled 1: receive fifo overflow interrupt is enabled 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 cndip 0 r/w carrier not detect interrupt enable 0: carrier not detect interrupt is disabled 1: carrier not detect interrupt is enabled 10 dlcip 0 r/w detect loss of carrier interrupt enable 0: detect loss of carrier interrupt is disabled 1: detect loss of carrier interrupt is enabled 9 cdip 0 r/w delayed collision detect interrupt enable 0: delayed collision detect interrupt is disabled 1: delayed collision detect interrupt is enabled 8 troip 0 r/w transmit retry over interrupt enable 0: transmit retry over interrupt is disabled 1: transmit retry over interrupt is enabled
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 742 of 950 rej09b0079-0200 bit bit name initial value r/w description 7 rmafip 0 r/w receive multicast address frame interrupt enable 0: receive multicast address frame interrupt is disabled 1: receive multicast address frame interrupt is enabled 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 rrfip 0 r/w receive residual-bit frame interrupt enable 0: receive residual-bit frame interrupt is disabled 1: receive residual-bit frame interrupt is enabled 3 rtlfip 0 r/w receive too- long frame interrupt enable 0: receive too-long frame interrupt is disabled 1: receive too-long frame interrupt is enabled 2 rtsfip 0 r/w receive too-s hort frame interrupt enable 0: receive too-short frame interrupt is disabled 1: receive too-short frame interrupt is enabled 1 preip 0 r/w phy-lsi receive error interrupt enable 0: phy-lsi receive error interrupt is disabled 1: phy-lsi receive error interrupt is enabled 0 cerfip 0 r/w crc error on received frame 0: crc error on received frame interrupt is disabled 1: crc error on received frame interrupt is enabled
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 743 of 950 rej09b0079-0200 19.2.8 transmit/receive status copy enable register (trscer) trscer indicates whether multicast address frame receive status informati on reported by bit 7 in eesr is reflected in the rfe bit in the corresponding descriptor (for details of descriptor descriptions, see section 19.3.1, descriptors and descriptor list). the rmafce bit in this register corresponds to bit 7 in eesr. when the rmafce bit is cleared to 0, the receive status (bit 7 in eesr) is reflect ed in the rfe bit in the receive descriptor. when this bit is set to 1, the status is not reflected in the descriptor even if the corresponding source occurs. the rmafce bit is cleared to 0 after a power-on reset and manual reset. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 rmafce 0 r/w rmaf bit copy directive 0: reflects the rmaf bit st atus in the rfe bit of the receive descriptor 1: occurrence of the corresponding source is not reflected in the rfe bit of the receive descriptor 6 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 744 of 950 rej09b0079-0200 19.2.9 receive missed-fram e counter register (rmfcr) rmfcr is a 16-bit counter that indicates the number of frames missed (discarded, and not transferred to the receive buffer) during reception. when the recei ve fifo overflow s, the receive frames in the fifo are discarded. the number of frames discarded at this time is counted. when the value in this register reaches h ffff, counting-up is halted. when this register is read, the counter value is cleared to 0. write opera tions to this register have no effect. bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 0 mfc15 to mfc0 all 0 r missed-frame counter indicate the number of fr ames that are discarded and not transferred to the receive buffer during reception.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 745 of 950 rej09b0079-0200 19.2.10 transmit fifo threshold register (tftr) tftr is a 32-bit readable/writable register that sp ecifies the transmit fifo threshold at which the first transmission is started. the actual threshol d is 4 times the set value. the etherc starts transmission when the amount of data in the transmit fifo exceeds the number of bytes specified by this register, when the transmit fifo is full, or when 1-frame write is executed. when setting this register, do so in the transmission-halt state.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 746 of 950 rej09b0079-0200 bit bit name initial value r/w description 31 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 to 0 tft10 to tft0 all 0 r/w transmit fifo threshold when setting a transmit fifo, the fifo must be set to a smaller value than the specified value of the fifo capacity by fdr. h 00: store and forward modes h 01 to h 0c: setting prohibited h 0d: 52 bytes h 0e: 56 bytes : : h 1f: 124 bytes h 20: 128 bytes : : h 3f: 252 bytes h 40: 256 bytes : : h 7f: 508 bytes h 80: 512 bytes : : h ff: 1020 bytes h 100: 1024 bytes : : h 1ff: 2044 bytes h 200: 2048 bytes note: when starting transmission before one frame of data write has completed, take care the generation of the underflow.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 747 of 950 rej09b0079-0200 19.2.11 fifo depth register (fdr) fdr is a 32-bit readable/writable register that sp ecifies the size of the tr ansmit and receive fifos. bit bit name initial value r/w description 31 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 to 8 tfd2 to tfd0 all 1 r/w transmit fifo size specifies 256 bytes to 2 kbytes in 256-byte units as the size of the transmit fi fo. the setting must not be changed after transmission/reception has started. 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 to 0 rfd2 to rfd0 all 1 r/w receive fifo size specifies 256 bytes to 2 kbytes in 256-byte units as the size of the receive fi fo. the setting must not be changed after transmission/reception has started.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 748 of 950 rej09b0079-0200 19.2.12 receiving method control register (rmcr) rmcr is a 32-bit readable/writable register that specifies the control meth od for the re bit in ecmr when a frame is received. this register must be set during the receiving-halt state. bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 rnc 0 r/w receive enable control sets whether to continue frame reception. 0: upon completion of reception of one frame, the e- dmac writes receive status to the descriptor and clears the rr bit in edrrr to 0 1: upon completion of reception of one frame, the e- dmac writes (writes back) receive status to the descriptor. in addition, the e-dmac reads the next descriptor and prepares for the reception of the next frame
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 749 of 950 rej09b0079-0200 19.2.13 e-dmac operation control register (edocr) edocr is a 32-bit readable/writable register that specifies the control methods used in e-dmac operation. bit bit name initial value r/w description 31 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 fec 0 r/w fifo error control specifies e-dmac operation when transmit fifo underflow or receive fifo overflow occurs. 0: e-dmac operation continues when underflow or overflow occurs 1: e-dmac operation halts when underflow or overflow occurs 2 aec 0 r/w address error control indicates detection of an illegal memory address in an attempted e-dmac transfer. 0: illegal memory address not detected (normal operation) 1: indicates that e-dmac operation is halted because an illegal memory address is detected. when 0 is written to this bit, the e-dmac resumes operation 1 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 750 of 950 rej09b0079-0200 19.2.14 receive buffer writ e address register (rbwar) rbwar stores the address of data to be written in the receiving buffer when the e-dmac writes data to the receiving buffer. which addresses in the receiving buffer are processed by the e- dmac can be recognized by monitoring addresses displayed in this register. the address that the e-dmac is actually processing may be differ ent from the value read from this register. bit bit name initial value r/w description 31 to 0 rbwa31 to rbwa0 all 0 r receiving-buffer write address these bits can only be read. writing is prohibited. 19.2.15 receive descriptor fe tch address register (rdfar) rdfar stores the descriptor star t address that is required when the e-dmac fetches descriptor information from the receiving descriptor. which receiving descriptor information is used for processing by the e-dmac can be recognized by monitoring addresses displayed in this register. the address from which the e-dmac is actually fetching a descriptor may be different from the value read from this register. bit bit name initial value r/w description 31 to 0 rdfa31 to rdfa0 all 0 r receiving-descriptor fetch address these bits can only be read. writing is prohibited. 19.2.16 transmit buffer read address register (tbrar) tbrar stores the addres s of the transmission buffer when the e-dmac reads data from the transmission buffer. which addresses in the tran smission buffer are processed by the e-dmac can be recognized by monitoring addresses displayed in this register. the address from which the e-dmac is actually reading in the buffer may be different from the value read from this register. bit bit name initial value r/w description 31 to 0 tbra31 to tbra0 all 0 r transmission-buffer read address these bits can only be read. writing is prohibited.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 751 of 950 rej09b0079-0200 19.2.17 transmit descriptor fetch address register (tdfar) tdfar stores the descriptor start address that is required when the e-dmac fetches descriptor information from the transmission descriptor. which transmission descriptor information is used for processing by the e-dmac can be recognized by monitoring addresses displayed in this register. the address from which the e-dmac is actually fetching a descriptor may be different from the value read from this register. bit bit name initial value r/w description 31 to 0 tdfa31 to tdfa0 all 0 r transmission-descriptor fetch address these bits can only be read. writing is prohibited. 19.2.18 overflow alert fifo threshold register (fcftr) fcftr is a 32-bit readable/writable register that se ts the flow control of the etherc. the threshold can be specified by the size of the receive fifo data (rfd2 to rfd0) and the number of receive frames (rff2 to rff0). if the same receive fifo size as set by the fifo size register (fdr) is set when flow control is turned on according to the rfd setting condition, flow control is turned on with (fifo data size ? 64) bytes. for instance, when rfd in fdr = 7 and rfd in fcftr = 7, flow control is turned on when (2048 ? 64) bytes of data is stored in the receive fifo. the value set in the rfd bits in this register should be equal to or less than those in fdr. flow control is turned on when any of the set ting conditions of the rff2 to rff0 bits or the rfd2 to rfd0 bits is satisfied. flow control is tu rned off when none of the conditions is satisfied (release).
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 752 of 950 rej09b0079-0200 bit bit name initial value r/w description 31 to 19 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 18 17 16 rff2 rff1 rff0 1 1 1 r/w r/w r/w receive fifo overflow alert signal output threshold 000: when one receive frame has been stored in the receive fifo 001: when two receive frames have been stored in the receive fifo : : 110: when seven receive frames have been stored in the receive fifo 111: when eight receive frames have been stored in the receive fifo 15 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 1 0 rfd2 rfd1 rfd0 1 1 1 r/w r/w r/w receive fifo overflow alert signal output threshold 000: when (256 ? 32) bytes of data is stored in the receive fifo 001: when (512 ? 32) bytes of data is stored in the receive fifo : : 110: when (1792 ? 32) bytes of data is stored in the receive fifo 111: when (2048 ? 64) bytes of data is stored in the receive fifo
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 753 of 950 rej09b0079-0200 19.2.19 transmit interrupt register (trimd) trimd is a 32-bit readable/writable register that specifies whether or not to notify write-back completion for each frame using th e twb bit in eesr and an inte rrupt on transmit operations. bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 tis 0 r/w transmit interrupt setting 0: write-backed completion for each frame using the twb bit in eesr is notified 1: write-back completion for each frame is not notified 19.3 operation using its direct memory access (dma) function, the e-dmac performs dma transfer of transmit/receive data between a ethernet frame tran smission/reception data storage destination of user- specified (accessible memory space: transmit buffer/receive buffer) an d the transmit/receive fifo in the e-dmac. (the user cannot read and write data in the transm it/receive fifo directly via the cpu). to enable the e-dmac to perfor m dma transfer, inform ation (data) including a transmit/receive data storage address and so forth, referred to as a descriptor, is required. before ethernet frame transmission/reception, the e-dmac reads descriptor information, then reads transmit data from the transmit buffer or writes receive data to the receive buffer according to the read descriptor information. by arranging multiple descriptors as a de scriptor row (list) (to be placed in a readable/writable memory space) , multiple ethernet frames can be transmitted or received continuously.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 754 of 950 rej09b0079-0200 19.3.1 descriptors a nd descriptor list two types of descriptors are available: transmit descriptors and receive de scriptors. the e-dmac automatically starts reading a tran smit/receive descriptor when the tr bit in edtrr is set to 1 or the rr bit in edrrr is set to 1. in a transmit/receive descriptor, th e user stores information about dma transfer of transmit/receive data. after comp letion of ethernet fram e transmissi on/reception, the e-dmac disables the descriptor valid/invalid bit and reflects the result of transmission/reception in the status bits. descriptors are placed in a readable/writable memo ry space. the address of the start descriptor (descriptor to be read first by the e-dmac) is set in tdlar/rdlar. when multiple descriptors are prepared as a descriptor row (descriptor list), the descriptors are placed in continuous (memory) addresses according to the descriptor length set in the dl0 and dl1 bits in edmr. the e-dmac consists of two systems: system 0 and system 1. the dmac for transmission and the dmac for reception operate i ndependently of each other, and the dmac for system 0 and the dmac for system 1 operate independently of eac h other. for normal e-dmac operation, place descriptors for transmission and reception and descriptors for system 0 and system 1 in those address spaces that do not overlap. (1) transmit descriptor figure 19.2 shows the configuration of a transmit descriptor and the relationship with a transmit buffer. the data of a transmit descriptor consists of td0, td1, td2, and padding data in groups of 32 bits from top to end. the length of padding data is determined according to the descriptor length specified by the dl0 and dl1 bits in edmr. in the figure, tba (bits 31 to 0 in td2) indicates the start address of a transmit bu ffer, and tdl (bits 31 to 16 in td1) indicates the valid data length of the transmit buffer. td0 indicates whether the transmit descriptor is valid or invalid as well as information about the descriptor configuration and status. td1 indicates the length of data in a transmit buffer to be transferred according to the speci fication of the descriptor. td2 in dicates the start address of a transmit buffer that holds data to be transferred. depending on the descriptor specification, one transmit descriptor can specify all transmit data of one frame (single-frame/single-buffe r) or multiple descriptors can specify the transmit data of one frame (single-frame/multi-buffer). as an example of single-frame/multi-buffer operation, the data portion that is used in a fixed manner in each et hernet frame transmission can be referenced by multiple descriptors. for example, multiple desc riptors can share the destination address and
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 755 of 950 rej09b0079-0200 transmit source address in an et hernet frame, and the remainin g data can be stored in each separate buffer. transmit descriptor transmit buffer valid transmit data t a c t t d l e t f p 1 t f p 0 tfs26 to tfs0 td0 tdl td1 tba padding (4/20/52 bytes) * td2 31 30 29 28 27 26 0 t f e 31 16 31 0 note: * according to the descriptor length set by the dl0 and dl1 bits in edmr, the padding size is determined as follows: for 16 bytes: padding = 4 bytes for 32 bytes: padding = 20 bytes for 64 bytes: padding = 52 bytes figure 19.2 relationship between tr ansmit descriptor and transmit buffer
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 756 of 950 rej09b0079-0200 (a) transmit descriptor 0 (td0) before the tr bit in edtrr is set to 1, the user sets the descriptor valid/invalid bit and sets other descriptor configuration. after completion of et hernet frame transmission , the e-dmac disables the descriptor valid/invalid bit and writes status info rmation. this operation is referred to as write- back. when using td0, the user should write desired values to bits 31 to 28 according to the descriptor configuration. write 0 to bits 27 to 0. bit bit name initial value r/w description 31 tact 0 r/w transmit descriptor valid/invalid indicates whether the corresponding descriptor is valid or invalid. to make this bit valid, store transmit data in a transmit buffer (user-specified transmit data storage destination) beforeha nd, then write 1 to this bit. the e-dmac clears this bit to 0 upon completion of data transfer. 0: indicates that the trans mit descriptor is invalid indicates the initial setting state, the state after 0 is written, or (in case the user writes 1 to this bit) that this bit is cleared to 0 because of completion of the processing of the e-dmac data transfer. if this state is recognized when the e-dmac reads a descriptor, the e-dmac clears the tr bit in edtrr to 0, and halts transfer operation related to transmission by the e-dmac. 1: indicates that the tr ansmit descriptor is valid after the user writes 1 to this bit, this bit indicates that data is not transferred yet or data is being transferred. when there is a descriptor row (descriptor list) consisting of multiple continuous descriptors, the e-dmac can continue operation when this bit of the next descriptor is valid.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 757 of 950 rej09b0079-0200 bit bit name initial value r/w description 30 tdle 0 r/w transmit descriptor list end indicates whether the corresponding descriptor is the last descriptor of the descriptor row (descriptor list). 0: not last descriptor upon completion of transfer of the corresponding descriptor, the e-dmac reads the next one in the list of continuous descriptors. 1: last descriptor upon completion of transfer of the corresponding descriptor, the e-dmac reads the descriptor placed at the address indicated by tdlar.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 758 of 950 rej09b0079-0200 bit bit name initial value r/w description 29 28 tfp1 tfp0 0 0 r/w r/w transmit frame position 1, 0 indicates whether information of the corresponding descriptor represents information about the start, middle, or end of the transmit frame. 00: the information of the descriptor represents information about the middle of the frame. 01: the information of the descriptor represents information about the end of the frame. 10: the information of the descriptor represents information about the start of the frame. 11: the information of t he descriptor represents all information about the frame (single-frame/single- descriptor (single-buffer)). reference: when one frame is divided for use, the method of specifying this bit for a descriptor row according to the number of divisions is described below. [for single-frame/single-descriptor operation] first descriptor: tfp[1:0] = 11 [for single-frame/two-descriptor operation] first descriptor: tfp[1:0] = 10 second descripto r: tfp[1:0] = 01 [for single-frame/three-descriptor operation] first descriptor: tfp[1:0] = 10 second descripto r: tfp[1:0] = 00 third descriptor: tfp[1:0] = 01 when the number of divisions is large, a descriptor row is configured by adding intermediate descriptors with tfp[1:0] = 00.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 759 of 950 rej09b0079-0200 bit bit name initial value r/w description 27 tfe 0 r/w transmit frame error occurrence indicates that an error occurred in the transmit frame. the errors occurred in tfs8 (bit 8), or tfs3 to tfs0 (bits 3 to 0). 26 to 0 tfs26 to tfs0 all 0 r/w transmit frame status indicate the status of the corresponding frame. a bit below, when set to 1, indicates the occurrence of the corresponding event. if the events of tfs8, or tfs3 to tfs0 occur, frames are incompletely transmitted. tfs26 to tfs9: reserved (the write value should always be 0.) tfs8: transmit abort detected note: this bit is set when any bit of tfs3 to tfs0 is set. tfs7 to tfs4: reserved (the write value should always be 0.) tfs3: failure to detect the carrier at the start of transmission (corresponding to the cnd bit in eesr) tfs2: loss of the carrier during transmission (corresponding to the dlc bit in eesr) tfs1: late (delayed) collision (corresponding to the cd bit in eesr) tfs0: transmit retry over (corresponding to the tro bit in eesr)
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 760 of 950 rej09b0079-0200 (b) transmit descriptor 1 (td1) td1 indicates the data length of the transmit buffer used by the corresponding descriptor. the user should set td1 before the start of a read by the e-dmac. bit bit name initial value r/w description 31 to 16 tdl all 0 r/w transmit buffer data length (in bytes) indicate the data length of the corresponding transmit buffer in bytes. 15 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. (c) transmit descriptor 2 (td2) td2 indicates the start address of the corresponding 32-bit width transmit buffer. an address value on a longword boundary should be specified. the user should set td2 before the start of a read by the e-dmac. (2) receive descriptor figure 19.3 shows the relatio nship between a receive desc riptor and receive buffer. the data of a receive descriptor co nsists of rd0, rd1, rd2, and pa dding data in groups of 32 bits from top to end. the length of padding data is determined according to the descriptor length specified by the dl0 and dl1 bits in edmr. in the figure, rba (bits 31 to 0 in rd2) indicates the start address of a recei ve buffer. rbl (bits 31 to 16 in rd1) indicates the usable data length of the receive buffer. rdl (b its 15 to 0 in rd1) indicates th e data length of a received frame. rd0 indicates whether the receive descriptor is valid or invalid as well as information about descriptor configuration and status. rd1 indicates the length (storage destination size) of data in the receive buffer to be received according to th e specification of the desc riptor. rd2 indicates the start address of the receive bu ffer for storing receive data. depending on the descriptor specification, one r eceive descriptor can specify the storing of all receive data of one frame in a receive buffer (s ingle-frame/single-buffer) or multiple descriptors can specify the storing of the r eceive data of one frame in recei ve buffers (single-frame/multi- buffer). as an example of single-frame/multi-buff er operation, suppose that a row of multiple descriptors (descriptor list) is prepared, rbl of each descriptor is 500 bytes, and a 1514-byte
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 761 of 950 rej09b0079-0200 ethernet frame is received. in such a case, the received ethernet frame is transferred sequentially to buffers, 500 bytes for each buffer, starting with the first descript or. only the last 14 bytes are transferred to the fourth buffer. when a frame longer than rbl of a descriptor is received, the e-dmac transfers the remaining data to the receive buffer by using the subsequent descriptors. as an example of efficient single-frame/multi-bu ffer operation, informat ion items on different processing layers in an ethernet frame can be separated from each other by using different buffers. for example, the destination address, transmit sour ce address, and type fiel d data in an ethernet frame can be stored in buffer 1 (with rbl set to 14 bytes) and the remaining data can be stored in buffer 2 (with rbl set to 1500 bytes). all receive frames, of course, can be stored in a single buffer if multiple descriptors are prepared and rbl of each descriptor is set to more than 1514 bytes (maximum ethernet frame length). receive descriptor receive buffer valid receive data r a c t r d l e r f p 1 r f e rfs26 to rfs0 rd0 rbl rdl rd1 rba padding (4/20/52 bytes) * rd2 r f p 0 31 30 29 28 27 26 0 31 16 31 0 15 0 note: * according to the descriptor length set by the dl0 and dl1 bits in edmr, the padding size is determined as follows: for 16 bytes: padding = 4 bytes for 32 bytes: padding = 20 bytes for 64 bytes: padding = 52 bytes figure 19.3 relationship between receive descriptor and receive buffer
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 762 of 950 rej09b0079-0200 (a) receive descriptor 0 (rd0) the user sets the descriptor valid/invalid bit and sets whether the descriptor represents the end of the descriptor list in rd0 before the rr bit in edrrr is set to 1 and the start of a read by the e- dmac. after completion of receive dma transfer of an ethernet frame by the e-dmac, the e- dmac disables the descriptor valid/invalid bit and writes status information. this operation is referred to as write-back. when using rd0, the user should write desired values to bits 31 and 30 according to the descriptor configuration. write 0 to bits 29 to 0. bit bit name initial value r/w description 31 ract 0 r/w receive descriptor valid/invalid indicates whether the corresponding descriptor is valid or invalid. to make this bit valid, prepare a receive buffer (user-specified receive data storage destination) beforehand, then write 1 to this bit. the e-dmac clears this bit to 0 upon completion of data transfer. 0: indicates that the rece ive descriptor is invalid indicates the initial setting state, the state after 0 is written, or (in case the user writes 1 to this bit) that this bit is cleared to 0 because of completion of the processing of the e-dmac data transfer. if this state is recognized when the e-dmac reads a descriptor, the e-dmac clears the rr bit in edrrr to 0, and halts transfer operation related to reception by the e-dmac. 1: indicates that the re ceive descriptor is valid indicates that data is not transferred yet after the user writes 1 to this bit, or that data is being transferred. when there is a descriptor row (descriptor list) consisting of multiple continuous descriptors, the e-dmac can continue operation when this bit of the next descriptor is valid.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 763 of 950 rej09b0079-0200 bit bit name initial value r/w description 30 rdle 0 r/w receive descriptor list end indicates whether the corresponding descriptor is the last descriptor of the descriptor row (descriptor list). 0: not last descriptor upon completion of transfer of the corresponding descriptor, the e-dmac reads the next one in the list of continuous descriptors. 1: last descriptor upon completion of transfer of the corresponding descriptor, the e-dmac reads the descriptor placed at the address indicated by rdlar.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 764 of 950 rej09b0079-0200 bit bit name initial value r/w description 29 28 rfp1 rfp0 0 0 r/w r/w receive frame position 1, 0 the e-dmac indicates by write-back operation whether information of the corresponding descriptor represents information about the start, middle, or end of the receive frame. 00: the information of the descriptor represents information about the middle of the frame. 01: the information of the descriptor represents information about the end of the frame. 10: the information of the descriptor represents information about the start of the frame. 11: the information of t he descriptor represents all information about the frame (single-frame/single- descriptor (single-buffer)). reference: the relationship between a frame after reception of one frame and a descriptor is described below. [for single-frame/single-descriptor operation] first descriptor: rfp[1:0] = 11 [for single-frame/two-descriptor operation] first descriptor: rfp[1:0] = 10 second descriptor: rfp[1:0] = 01 [for single-frame/three-descriptor operation] first descriptor: rfp[1:0] = 10 second descriptor: rfp[1:0] = 00 third descriptor: rfp[1:0] = 01 when the number of divisions is large, a descriptor row is configured by adding intermediate descriptors with rfp[1:0] = 00.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 765 of 950 rej09b0079-0200 bit bit name initial value r/w description 27 rfe 0 r/w receive frame error occurrence indicates that an error occurred in the receive frame. the errors occurred in rfs8 (bit 8), or rfs3 to rfs0 (bits 3 to 0). trscer can specify whether the multicast address frame receive information is reflected in this bit or not. 26 to 0 rfs26 to rfs0 all 0 r/w receive frame status indicate the status of the corresponding frame. a bit below, when set to 1, indicates the occurrence of the corresponding event. if the events of rfs8, or rfs4 to rfs0 occur, frames are incompletely received. rfs26 to rfs10: reserved (the write value should always be 0) rfs9: receive fifo overflow (corresponding to the rfof bit in eesr) rfs8: receive abort detected note: this bit is set when any bit of rfs3 to rfs0 is set. rfs7: multicast address frame received (corresponding to the rmaf bit in eesr) rfs6 and rfs5: reserved (the write value should always be 0) rfs4: residual-bit frame receive error (corresponding to the rrf bit in eesr) rfs3: too-long frame receive error (corresponding to the rtlf bit in eesr) rfs2: too-short frame receive error (corresponding to the rtsf bit in eesr) rfs1: phy-lsi receive error (corresponding to the pre bit in eesr) rfs0: crc error on receive frame (corresponding to the cerf bit in eesr)
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 766 of 950 rej09b0079-0200 (b) receive descriptor 1 (rd1) in rd1, the user specifies the data length of a receive buffer usable by the corresponding descriptor. after reception of a frame, rd1 indi cates the length of a frame received by the e-dmac. the user should set rd1 before the start of a read by the e-dmac. bit bit name initial value r/w description 31 to 16 rbl all 0 r/w receive buffer data length (in bytes, to be specified on 16-byte boundary) set the length of data that can be received by the corresponding receive buffer in bytes. set a receive buffer length on a 16-byte boundary (with bits 19 to 16 cleared to 0). in single-frame/single-buffer (descriptor) operation, the maximum receive frame length excluding crc data is 1514 bytes. when specifying a receive buffer length, set 1520 bytes (h'05f0), which is determined considering the maximum receive frame length and a 16-byte boundary. 15 to 0 rdl all 0 r receive data length indicate the data length of a receive frame stored in the receive buffer. receive data transferred to the receive buffer does not include crc data (4 bytes) placed at the end of a frame. as a receive frame length, the number of bytes (valid data bytes) not including crc data are reported. in single-frame/multi-buffer (descriptor) operation, only the receive data length of the last descriptor is valid. the receive data length of an intermediate descriptor has no meaning. (c) receive descriptor 2 (rd2) rd2 indicates the start address of the corresponding 32-bit widt h receive buffer. set the start address of a receive buffer on a longword boundary. when an sd ram is connected, set the start address of a receive buffer on a 16-byte boundary. the user should set rd2 before the start of a read by the e-dmac.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 767 of 950 rej09b0079-0200 19.3.2 transmission when 1 is written to the transmit request bit (t r) in the e-dmac transmit request register (edtrr) while the te bit in ecmr is set to 1, the e-dmac reads the descriptor following the previously used descriptor from the transmit descriptor list (or the descriptor indicated by the transmit descriptor start address register (tdlar) at the initial start time). if the tact bit of the read descriptor is set to 1 (valid), the e-dmac sequentially read s transmit frame data from the transmit buffer start address specified by td2 for transfer to the etherc. the etherc creates a transmit frame and starts transmission to the mii. after dma transfer of data equivalent to the buffer length specified in the descriptor, the following processing is carried out according to the tfp value. 1. tfp = 00 or 10 (frame continuation): descriptor write-back (writing 0 to the tact bit) is performed after dma transfer. 2. tfp = 01 or 11 (frame end): descriptor write-back (writing 0 to the tact bit and writing status) is performed after completion of frame transmission. as long as the tact bit of a read descriptor is set to 1 (valid), the reading of e-dmac descriptors and the transmission of frames continue. when a descriptor with the tact bit cleared to 0 (invalid) is read, the e-dmac clears the tr bit in edtrr to 0 and completes transmit processing.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 768 of 950 rej09b0079-0200 this lsi + memory transmission flowchart e-dmac etherc ethernet transmit fifo etherc/e-dmac initialization transmit descriptor and transmit buffer setting start of transmission transmit descriptor read transmit descriptor write-back transmit descriptor write-back transmission completed transmit descriptor read transmit data transfer frame transmission transmit data transfer [legend] etherc/e-dmac initialization: executes a software reset with the swr bit in edmr set to 1. transmit descriptor and transmit buffer setting: sets transmit descriptors and transmit buffers, and sets etherc and e-dmac registers, then writes 1 to the te bit i n ecmr and the tr bit in edtrr. start of transmission: occurs when 1 is written to the te bit in ecmr and the tr bit in edtrr. transmit descriptor read: the e-dmac reads a transmit descriptor. transmit data transfer: writes transmit data to the transmit fifo by using dma transfer by the e-dmac. transmit descriptor write-back: the e-dmac writes 0 to the tact bit and writes the transmit status to the transmit descriptor. figure 19.4 sample transmission flowchart (single-frame/two-descriptor)
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 769 of 950 rej09b0079-0200 19.3.3 reception when 1 is written to the receive request bit ( rr) in the e-dmac receive request register (edrrr) while the re bit in ecmr is set to 1, the e-dmac reads the descriptor following the previously used descriptor from the receive descri ptor list (or the descri ptor indicated by the receive descriptor start address re gister (rdlar) at the initial star t time) then enters the receive standby state. when the etherc receives a fram e for this lsi (with an address enabled for reception by this lsi), the etherc stores the receive data in the receive fifo. the receive data is transferred to the receive buffer specified by rd2 according to th e receive descriptor with the ract bit set to 1 (valid). if th e data length of a received frame is longer than the buffer length specified by rd1, the e-dmac performs a write-back operation to the descriptor (with rfp set to 10 or 00) when the buffer becomes full, then reads the next descriptor. the e-dmac then continues to transfer data to th e receive buffer specified by the ne w rd2. when frame reception is completed, or if frame reception is suspended b ecause of a certain kind of error, the e-dmac performs write-back to the relevant descriptor (with rfp set to 11 or 01), and then ends the receive processing. the e-dmac then reads the ne xt descriptor and enters the receive standby state again. to receive frames continuously, the receive enable control bit (rnc) must be set to 1 in the receive method control register (rmcr). the initial value is 0.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 770 of 950 rej09b0079-0200 this lsi + memory reception flowchart e-dmac etherc receive fifo ethernet etherc/e-dmac initialization receive descriptor and receive buffer setting reception completed [legend] etherc/e-dmac initialization: executes a software reset with the swr bit in edmr set to 1. receive descriptor and receive buffer setting: sets receive descriptors and receive buffers, and sets etherc and e-dmac registers, then writes 1 to the re bit in ecmr and the rr bit in edrrr. start of reception: occurs when 1 is written to the re bit in ecmr and the rr bit in edrrr. receive descriptor read: the e-dmac reads a receive descriptor. receive data transfer: writes receive data from the receive fifo to the receive buffer by using dma transfer by the e-dmac. receive descriptor write-back: the e-dmac writes 0 to the ract bit and writes the receive status to the receive descriptor. receive data transfer receive data transfer frame reception start of reception receive descriptor read receive descriptor write-back receive descriptor write-back receive descriptor read (preparation for receiving the next frame) receive descriptor read figure 19.5 sample reception flow chart (single-fram e/two-descriptor)
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 771 of 950 rej09b0079-0200 19.3.4 transmit/receive processing of multi-buffer frame (single-frame/ multi-descriptor) (1) multi-buffer frame transmit processing if an error occurs during multi-buffer frame transmission, the processing shown in figure 19.6 is carried out by the e-dmac. in the figure where the transmit descriptor is shown as inactive (tact bit = 0), buffer data has already been transmitted normally, and where the tr ansmit descriptor is shown as active (tact bit = 1), buffer data has not been transmitted. if a fra me transmit error occurs in the first descriptor part where the transmit descriptor is active (tact bit = 1), transmission is halted, and the tact bit cleared to 0, immediately. the next descriptor is then read, and the position within the transmit frame is determined on the basis of bits tfp1 and tfp0 (continuing [b 00] or end [b 01]). in the case of a continuing descriptor, the tact bit is cleared to 0, only, and the next descriptor is read immediately. if the descriptor is the final descriptor, not only is the tact bit cleared to 0, but write-back is also performed to the tfe and tfs b its at the same time. data in the buffer is not transmitted between the occurrence of an error and write-back to the final descriptor. if error interrupts are enabled in the etherc/e-dmac status interrupt permission register (eesipr), an interrupt is generated immediately after the final descriptor write-back. 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 e-dmac inactivates tact (change 1 to 0) descriptor read inactivates tact descriptor read inactivates tact descriptor read inactivates tact descriptor read inactivates tact and writes tfe, tfs descriptors untransmitted data is not transmitted after error occurrence. descriptor is only processed. one frame buffer length set by descriptor transmitted data untransmitted data transmit error occurrence t a c t t d l e t f p 1 t f p 0 frame type start start end continue continue continue continue continue continue figure 19.6 e-dmac oper ation after transmit error
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 772 of 950 rej09b0079-0200 (2) receive processing in case of multi-buffer frame if an error occurs during reception in the case of a multi-buffer frame where a receive frame is divided for storage in multiple buffers, the e- dmac performs the processing shown in figure 19.7. in the figure, the invalid receive descriptors (with the ract bit cleared to 0) represent the normal reception of data to be stored in buffers, and th e valid receive descriptors (with the ract bit set to 1) represent unreceived buffers. if a frame receive error occu rs with a descript or shown in the figure, the status is written back to the corresponding descriptor. if error interrupts are enabled in the etherc/e -dmac status interrupt permission register (eesipr), an interrupt is generated immediatel y after the write-back. if there is a new frame receive request, reception is continued from th e buffer after that in which the error occurred. e-dmac inactivates ract and writes rfe, rfs descriptor read descritptors buffer length set by descriptor received data unreceived data receive error occurrence start of frame new frame reception continues from this buffer 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r a c t r d l e r f p 1 r f p 0 frame type start continue continue . . . . . . . . figure 19.7 e-dmac oper ation after receive error
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 773 of 950 rej09b0079-0200 19.3.5 receive fifo ov erflow alert signal ( arbusy ) the e-dmac outputs the receive fifo overflow alert signal ( arbusy ) to the etherc to support flow control function conforming to ieee802.3x of the etherc. the arbusy signal synchronized with the bus clock (b clock) signal is also output to an external pin of this lsi. when the capacity of data received in receive fifo or the number of receive frames reach the threshold (rff2 to rff0, or rfd2 to rfd0) specified in fcftr in e-dmac, arbusy is valid. the threshold is the value less than the overflow value: 2048 ? 64, 1792 ? 32, 1536 ? 32, and 256 ? 32 bytes. figure 19.9 shows the conf iguration of the receive fi fo overflow alert signal ( arbusy ) output. as shown in figure 19.9, because the arbusy signal passes through the system clock synchronization circuit, it is behind the receive fifo overflow alert si gnal received in etherc. this lsi e-dmac1 arbusy etherc system clock synchronization circuit receive fifo overflow alert signal e-dmac0 receive fifo overflow alert signal figure 19.8 configuration of arbusy
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 774 of 950 rej09b0079-0200 (1) operation of receive fi fo overflow alert signal receive fifo overflow aler t signal is asserted when the number of the receive data accumulated in the receive fifo is equal to or more than the threshold set in the overflow alert fifo threshold register (fcftr) (1). after that, when the numbe r of the accumulated receive data drops below (threshold ? 32) bytes, the signal is negated (2). here, threshold values are as follows: 2048 ? 64, 1792 ? 32, . therefore, the signal-negated values are as follows: 2048 ? 96, 1792 ? 64, . receive fifo receive data alert signal empty full (1) (2) t threshold (threshold ? 32) bytes transfer to memory by e-dmac figure 19.9 summary of receive fifo overflow alert signal (a) receive fifo overflow alert signal changing the receive fifo in the e-dmac can perform writing (reception) da ta from the ethernet line and reading data from the system simultaneously. ther efore during system operation, receive data of fifo is always increased or decr eased. if the change is performed near the threshold, the receive fifo overflow alert signal may be seen as sh own in figure 19.11. minimum of receive data changes depending on the number of fifo read cycles and rate of ethernet line (10 to 100 mbs).
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 775 of 950 rej09b0079-0200 arbusy signal minimum value (low): 150 nsec (exernal bus operated at 66.66mhz and 16-byte burst transfer (5 cycle 2)) minimum value (high): 2560 nsec (100 base-t (100m ether) operation) (time for receiving 32-byte data) empty t threshold ( threshold ? 32) bytes figure 19.10 arbusy signal change and minimum pulse width depending on increase and decrease of fifo
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 776 of 950 rej09b0079-0200 19.4 usage notes 19.4.1 using of edtrr and edrrr [problems] while the ethernet functions are being used, the tr bit in edtrr or the rr bit in edrrr is cleared to 0 to stop the e-damc functions if the descriptor valid bit is invalid. when the request bit (tr or rr) is cleared by the e-dmac and th e request bit (tr or rr) is set by the user's firmware simultaneously, transmission or reception may not be started even if the request bit (tr or rr) is set to 1. [occurring condition] when the user's firmware tries to set the reques t bit (tr or rr), while the request bit (tr or rr) is 1. [avoiding methods] to prevent the simultaneous occu rrence of the request bit (tr or rr) being cleared by the e- dmac and the request bit (tr or rr) being set by the user's firmware, the user's firmware should set the request bit (tr or rr) after confirming that it is cleared by the e-dmac. the methods to clear the rr bit with e-dmac are as follows. (1) confirmation of the tr bit as a direct method, it is possible to confirm by reading the tr bit in edtrr as 0. as an indirect method, it is possible to confirm by reading the tde bit in eesr as 1. (2) confirmation of the rr bit as a direct method, it is possible to confirm by reading the rr bit in edrrr as 0. as an indirect method, it is possible to confirm by reading the rde bit in eesr as 0.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 777 of 950 rej09b0079-0200 19.4.2 endian support in e-dmac when the external memory is accessed through th e e-dmac, big endian is supported but little endian is not supported. therefor e, if the external memory is accessed through the e-dmac in little endian mode, data format should be converted from big endian mode to little endian mode through software.
section 19 ethernet controller direct memory access controller (e-dmac) rev. 2.00 dec. 07, 2005 page 778 of 950 rej09b0079-0200
section 20 ip security accelerator (ipsec) rev. 2.00 dec. 07, 2005 page 779 of 950 rej09b0079-0200 section 20 ip security accelerator (ipsec) this section will be made available on conclusion of a nondisclosure agreement. for details, contact your renesas sales agency.
section 20 ip security accelerator (ipsec) rev. 2.00 dec. 07, 2005 page 780 of 950 rej09b0079-0200
section 21 pin function controller (pfc) rev. 2.00 dec. 07, 2005 page 781 of 950 rej09b0079-0200 section 21 pin function controller (pfc) 21.1 overview the pin function controller (pfc) is composed of registers for selecting the function of multiplexed pins and the input/output direction. the pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the chip. tables 21.1 and 21.2 list the multiplexed pins. table 21.1 list of multiplexed pins (1) port port function (related module) other function (related module) a pta7 input/output (port) s iofsync0 input/output (siof0) a pta6 input/output (port) txd_sio0 output (siof0) a pta5 input/output (port) rxd_sio0 input (siof0) a pta4 input/output (port) siomclk0 input (siof0) a pta3 input/output (port) sc k_sio0 input/output (siof0) a pta2 input/output (port) scif0ck input/output (scif0) a pta1 input/output (port) txd0 output (scif0) a pta0 input/output (port) rxd0 input (scif0) b ptb7 input/output (port) rts0 output (scif0) b ptb6 input/output (port) cts0 input (scif0) b ptb5 input/output (port) scif1ck input/output (scif1) b ptb4 input/output (port) txd1 output (scif1) b ptb3 input/output (port) rxd1 input (scif1) b ptb2 input/output (port) rts1 output (scif1) b ptb1 input/output (port) cts1 input (scif1) b ptb0 input/output (port) reserved (setting prohibited) * c ptc7 input/output (port) iois16 input (bsc) c ptc6 input/output (port) ce2b output (bsc) c ptc5 input/output (port) ce2a output (bsc) c ptc4 input/output (port) s iofsync1 input/output (siof1)
section 21 pin function controller (pfc) rev. 2.00 dec. 07, 2005 page 782 of 950 rej09b0079-0200 port port function (related module) other function (related module) c ptc3 input/output (port) txd_sio1 output (siof1) c ptc2 input/output (port) rxd_sio1 input (siof1) c ptc1 input/output (port) siomclk1 input (siof1) c ptc0 input/output (port) sc k_sio1 input/output (siof1) note: * when the register is set to reserv ed, the operation is not guaranteed. table 21.2 list of multiplexed pins (2) ethernet controller function other function (related module) exout1 output tend1 output (dmac) camsen1 input irq5 input (intc) exout0 output tend0 output (dmac) camsen0 input irq4 input (intc) 21.2 register configuration the registers of the pin function controller are shown below. ? ? ? ?
section 21 pin function controller (pfc) rev. 2.00 dec. 07, 2005 page 783 of 950 rej09b0079-0200 21.3 register descriptions 21.3.1 port a control register (pacr) pacr is a 16-bit readable/writable register that selects the pin functions. pacr is initialized to h bit bit name initial value r/w description 15 pa7md1 1 r/w 14 pa7md0 0 r/w 13 pa6md1 1 r/w 12 pa6md0 0 r/w 11 pa5md1 1 r/w 10 pa5md0 0 r/w 9 pa4md1 1 r/w 8 pa4md0 0 r/w 7 pa3md1 1 r/w 6 pa3md0 0 r/w 5 pa2md1 1 r/w 4 pa2md0 0 r/w 3 pa1md1 1 r/w 2 pa1md0 0 r/w 1 pa0md1 1 r/w 0 pa0md0 0 r/w modes pa7 to pa0 control the combination of panmd1 and panmd0 (n = 0 to 7) selects the pin function s and control input pull-up mos. 00: other function (see table 21.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off)
section 21 pin function controller (pfc) rev. 2.00 dec. 07, 2005 page 784 of 950 rej09b0079-0200 21.3.2 port b control register (pbcr) pbcr is a 16-bit readable/writable register that selects the pin functions. pbcr is initialized to h bit bit name initial value r/w description 15 pb7md1 1 r/w 14 pb7md0 0 r/w 13 pb6md1 1 r/w 12 pb6md0 0 r/w 11 pb5md1 1 r/w 10 pb5md0 0 r/w 9 pb4md1 1 r/w 8 pb4md0 0 r/w 7 pb3md1 1 r/w 6 pb3md0 0 r/w 5 pb2md1 1 r/w 4 pb2md0 0 r/w 3 pb1md1 1 r/w 2 pb1md0 0 r/w 1 pb0md1 1 r/w 0 pb0md0 0 r/w modes pb7 to pb0 control the combination of pbnmd1 and pbnmd0 (n = 0 to 7) selects the pin functions and controls input pull-up mos. 00: other function (n = 1 to 7) or reserved (n = 0) (see table 21.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off)
section 21 pin function controller (pfc) rev. 2.00 dec. 07, 2005 page 785 of 950 rej09b0079-0200 21.3.3 port c control register (pccr) pccr is a 16-bit readable/writable register that selects the pin functions. pccr is initialized to h bit bit name initial value r/w description 15 pc7md1 1 r/w 14 pc7md0 0 r/w 13 pc6md1 1 r/w 12 pc6md0 0 r/w 11 pc5md1 1 r/w 10 pc5md0 0 r/w 9 pc4md1 1 r/w 8 pc4md0 0 r/w 7 pc3md1 1 r/w 6 pc3md0 0 r/w 5 pc2md1 1 r/w 4 pc2md0 0 r/w 3 pc1md1 1 r/w 2 pc1md0 0 r/w 1 pc0md1 1 r/w 0 pc0md0 0 r/w modes pc7 to pc0 control the combination of pcnmd1 and pcnmd0 (n = 0 to 7) selects the pin functions and controls input pull-up mos. 00: other function (see table 21.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off)
section 21 pin function controller (pfc) rev. 2.00 dec. 07, 2005 page 786 of 950 rej09b0079-0200 21.3.4 ethernet controller pin control register (petcr) petcr is a 16-bit readable/writable register that selects the pin functions. petcr is initialized to h bit bit name initial value r/w description 15 pet3md 1 r/w controls output of exout 1 (ethernet controller function) and tend1 (other function). 0: tend1 (other function) is selected. 1: exout1 (ethernet controller function) is selected. 14 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 13 pet2md 1 r/w controls input of camsen1 (ethernet controller function) and irq5 (other function). 0: irq5 (other function) is selected. 1: camsen1 (ethernet controller function) is selected. 12 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 11 pet1md 1 r/w controls output of exout0 (ethernet controller function) and tend0 (other function). 0: tend0 (other function) is selected. 1: exout0 (ethernet controller function) is selected. 10 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 9 pet0md 1 r/w controls input of camsen0 (ethernet controller function) and irq4 (other function). 0: irq4 (other function) is selected. 1: camsen0 (ethernet controller function) is selected.
section 21 pin function controller (pfc) rev. 2.00 dec. 07, 2005 page 787 of 950 rej09b0079-0200 bit bit name initial value r/w description 8 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 7 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 6 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 5 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 4 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 3 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 0 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 21 pin function controller (pfc) rev. 2.00 dec. 07, 2005 page 788 of 950 rej09b0079-0200
section 22 i/o ports rev. 2.00 dec. 07, 2005 page 789 of 950 rej09b0079-0200 section 22 i/o ports 22.1 overview this lsi has three 8-bit ports (ports a to c). all port pins are multiplexed with other pin functions (the pin function controller (pfc) handles the selection of pin functions and pull-up mos control). each port has a data register which stores data for the pins. 22.2 register descriptions 22.2.1 port a data register (padr) padr is an 8-bit readable/writable register that stores data for pins pta7 to pta0. bits pa7dt to pa0dt correspond to pins pta7 to pta0. padr is initialized to h bit bit name initial value r/w description 7 pa7dt 0 r/w 6 pa6dt 0 r/w 5 pa5dt 0 r/w 4 pa4dt 0 r/w 3 pa3dt 0 r/w 2 pa2dt 0 r/w 1 pa1dt 0 r/w 0 pa0dt 0 r/w when the pin function is general output port, if the port is read, the value of the corresponding padr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. table 22.1 shows the function of padr.
section 22 i/o ports rev. 2.00 dec. 07, 2005 page 790 of 950 rej09b0079-0200 table 22.1 port a data register (padr) read/write operations panmd1 panmd0 pin state read write 0 0 other function padr value value is written to padr, but does not affect pin state. 1 output padr value write value is output from pin. 1 0 input (pull-up mos on) pin state value is written to padr, but does not affect pin state. 1 input (pull-up mos off) pin state value is written to padr, but does not affect pin state. [legend] n = 0 to 7 22.2.2 port b data register (pbdr) pbdr is an 8-bit readable/writable register that stores the data for pins ptb7 to ptb0. bits pb7dt to pb0dt correspond to the pins ptb7 to ptb0. pbdr is initialized to h bit bit name initial value r/w description 7 pb7dt 0 r/w 6 pb6dt 0 r/w 5 pb5dt 0 r/w 4 pb4dt 0 r/w 3 pb3dt 0 r/w 2 pb2dt 0 r/w 1 pb1dt 0 r/w 0 pb0dt 0 r/w when the pin function is general output port, if the port is read, the value of the corresponding pbdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. tables 22.2 and 22.3 show the function of pbdr.
section 22 i/o ports rev. 2.00 dec. 07, 2005 page 791 of 950 rej09b0079-0200 table 22.2 port b data register (pbdr) read/write operations (1) pbnmd1 pbnmd0 pin state read write 0 0 other function pbdr value value is written to pbdr, but does not affect pin state. 1 output pbdr value write value is output from pin. 1 0 input (pull-up mos on) pin state value is written to pbdr, but does not affect pin state. 1 input (pull-up mos off) pin state value is written to pbdr, but does not affect pin state. [legend] n = 1 to 7 table 22.3 port b data register (pbdr) read/write operations (2) pbnmd1 pbnmd0 pin state read write 0 0 reserved * pbdr value value is written to pbdr, but does not affect pin state. 1 output pbdr value write value is output from pin. 1 0 input (pull-up mos on) pin status value is written to pbdr, but does not affect pin state. 1 input (pull-up mos off) pin status value is written to pbdr, but does not affect pin state. [legend] n = 0 note: * when this pin is specified as a reserv ed pin, its operation is not guaranteed.
section 22 i/o ports rev. 2.00 dec. 07, 2005 page 792 of 950 rej09b0079-0200 22.2.3 port c data register (pcdr) pcdr is an 8-bit readable/writable register that stores the data for pins ptc7 to ptc0. bits pc7dt to pc0dt correspond to the pins ptc7 to ptc0. pcdr is initialized to h bit bit name initial value r/w description 7 pc7dt 0 r/w 6 pc6dt 0 r/w 5 pc5dt 0 r/w 4 pc4dt 0 r/w 3 pc3dt 0 r/w 2 pc2dt 0 r/w 1 pc1dt 0 r/w 0 pc0dt 0 r/w when the pin function is general output port, if the port is read, the value of the corresponding pcdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. table 22.4 shows the function of pcdr. table 22.4 port c data register (pcdr) read/write operations pcnmd1 pcnmd0 pin state read write 0 0 other function pcdr value value is written to pcdr, but does not affect pin state. 1 output pcdr value write value is output from pin. 1 0 input (pull-up mos on) pin state value is written to pcdr, but does not affect pin state. 1 input (pull-up mos off) pin state value is written to pcdr, but does not affect pin state. [legend] n = 0 to 7
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 793 of 950 rej09b0079-0200 section 23 user debu gging interface (h-udi) this lsi incorporates a user debugging interface (h-udi) and advanced us er debugger (aud) for a boundary scan function and emulator support. this section describes the h-udi. the aud is a function exclusively fo r use by an emulator. refer to the user?s manual for the rele vant emulator for details of the aud. 23.1 features the h-udi (user debugging interface) is a serial i/o interface which conf orms to jtag (joint test action group, ieee standard 1149.1 and ieee standard test access port and boundary- scan architecture) specifications. the h-udi in this lsi supports a boundary scan mode, and is also used for emulator connection. when using an emulator, h-udi functions should not be used. refer to the emulator manual for the method of conn ecting the emulator. figure 23.1 shows a block diagram of the h-udi. sdir sdid tck tdo tdi tms sdbpr mux sdbsr shift register tap controller decoder local bus t rst figure 23.1 block diagram of h-udi
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 794 of 950 rej09b0079-0200 23.2 input/output pins table 23.1 shows the pin configuration of the h-udi. table 23.1 pin configuration pin name input/output description tck input serial data input/output clock pin data is serially supplied to the h-udi from the data input pin (tdi), and output from the data output pin (tdo), in synchronization with this clock. tms input mode select input pin the state of the tap control circuit is determined by changing this signal in synchronization with tck. the protocol conforms to the jtag standard (ieee std.1149.1). trst input reset input pin input is accepted asynchronously with respect to tck, and when low, the h-udi is reset. trst must be low for a constant period when power is turned on regardless of using the h-udi function. as the same as the resetp pin, the trst pin should be driven low at the power-on reset state and driven high after the power-on reset state is releas ed. this is different from the jtag standard. see section 23.4.2, reset confi guration, for more information. tdi input serial data input pin data transfer to the h-udi is executed by changing this signal in synchronization with tck. tdo output serial data output pin data read from the h-udi is executed by reading this pin in synchronization with tck. the data output timing depends on the command type set in the sdir. see section 23.4.3 tdo output timing, for more information. asemd0 input ase mode select pin if a low level is input at the asemd0 pin while the resetp pin is asserted, ase mode is entered; if a high level is input, normal mode is entered. in ase mode, dedicated emulator function can be used. the input level at the asemd0 pin should be held for at least one cycle after resetp negation.
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 795 of 950 rej09b0079-0200 pin name input/output description asebrkak audsync audata3 to 0 audck output output output output dedicated emulator pin 23.3 register descriptions the h-udi has the following registers. refer the s ection 24, list of registers, for the addresses and access size for registers. ? ? ? ? trst assertion or in the tap test-logic-reset state, and can be written to by the h- udi irrespective of the cp u mode. operation is not guaranteed if a reserved command is set in this register.
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 796 of 950 rej09b0079-0200 bit bit name initial value r/w description 15 to 13 ti7 to ti5 all 1 r 12 ti4 0 r 11 to 8 ti3 to ti0 all 1 r test instruction 7 to 0 the h-udi instruction is transferred to sdir by a serial input from tdi. for commands, see table 23.2. 7 to 2 ? all 1 r reserved these bits are always read as 1. 1 ? 0 r reserved this bit is always read as 0. 0 ? 1 r reserved this bit is always read as 1. table 23.2 h-udi commands bits 15 to 8 ti7 ti6 ti5 ti4 ti3 ti 2 ti1 ti0 description 0 0 0 0 ? ? ? ? jtag extest 0 0 1 0 ? ? ? ? jtag clamp 0 0 1 1 ? ? ? ? jtag highz 0 1 0 0 ? ? ? ? jtag sample/preload 0 1 1 0 ? ? ? ? h-udi reset negate 0 1 1 1 ? ? ? ? h-udi reset assert 1 0 1 ? ? ? ? ? h-udi interrupt 1 1 1 0 ? ? ? ? jtag idcode (initial value) 1 1 1 1 ? ? ? ? jtag bypass other than the above reserved 23.3.3 boundary scan register (sdbsr) sdbsr is a shift register, located on the pad, for controlling the input/output pins of this lsi. the initial value is undefined. sdbs r cannot be accessed by the cpu. using the extest, sample/preload, clamp, and highz commands, a boundary scan test conforming to the jtag standard can be carried out. table 23.3 s hows the correspondence between this lsi?s pins and boundary scan register bits.
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 797 of 950 rej09b0079-0200 table 23.3 this lsi?s pins and boundary scan register bits bit pin name i/o bit pin name i/o from tdi 334 d2 out 362 breq in 333 d3 out 361 wait in 332 d4 out 360 d0 in 331 d5 out 359 d1 in 330 d6 out 358 d2 in 329 d7 out 357 d3 in 328 d8 out 356 d4 in 327 d9 out 355 d5 in 326 d10 out 354 d6 in 325 d11 out 353 d7 in 324 d12 out 352 d8 in 323 d13 out 351 d9 in 322 d14 out 350 d10 in 321 d15 out 349 d11 in 320 we0 ( be0 )/dqmll out 348 d12 in 319 we1 ( be1 )/dqmlu/ we out 347 d13 in 318 rd/ wr out 346 d14 in 317 cas out 345 d15 in 316 cke out 344 refout / irqout / arbusy out 315 ras out 343 back out 314 cs2 out 342 cs0 out 313 cs3 out 341 cs4 out 312 a0 out 340 cs5a out 311 a1 out 339 cs6a out 310 a2 out 338 rd out 309 a3 out 337 bs out 308 a4 out 336 d0 out 307 a5 out 335 d1 out 306 a6 out
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 798 of 950 rej09b0079-0200 bit pin name i/o bit pin name i/o 305 a7 out 273 rd/ wr control 304 a8 out 272 cas control 303 a9 out 271 cke control 302 a10 out 270 ras control 301 a11 out 269 cs2 control 300 a12 out 268 cs3 control 299 refout / irqout / arbusy control 267 a0 control 298 back control 266 a1 control 297 cs0 control 265 a2 control 296 cs4 control 264 a3 control 295 cs5a control 263 a4 control 294 cs6a control 262 a5 control 293 rd control 261 a6 control 292 bs control 260 a7 control 291 d0 control 259 a8 control 290 d1 control 258 a9 control 289 d2 control 257 a10 control 288 d3 control 256 a11 control 287 d4 control 255 a12 control 286 d5 control 254 d16 in 285 d6 control 253 d17 in 284 d7 control 252 d18 in 283 d8 control 251 d19 in 282 d9 control 250 d20 in 281 d10 control 249 d21 in 280 d11 control 248 d22 in 279 d12 control 247 d23 in 278 d13 control 246 d24 in 277 d14 control 245 d25 in 276 d15 control 244 d26 in 275 we0 ( be0 )/dqmll control 243 d27 in 274 we1 ( be1 )/dqmlu/ we control 242 d28 in
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 799 of 950 rej09b0079-0200 bit pin name i/o bit pin name i/o 241 d29 in 210 d21 out 240 d30 in 209 d22 out 239 d31 in 208 d23 out 238 ptb0 in 207 d24 out 237 ptb1/ cts1 in 206 d25 out 236 ptb2/ rts1 in 205 d26 out 235 ptb3/rxd1 in 204 d27 out 234 ptb4/txd1 in 203 d28 out 233 ptb5/scif1ck in 202 d29 out 232 ptb6/ cts0 in 201 d30 out 231 ptb7/ rts0 in 200 d31 out 230 pta0/rxd0 in 199 a18 out 229 pta1/txd0 in 198 a19 out 228 pta2/scif0ck in 197 a20 out 227 pta3/sck_sio0 in 196 a21 out 226 pta4/siomclk0 in 195 a22 out 225 pta5/rxd_sio0 in 194 a23 out 224 pta6/txd_sio0 in 193 a24 out 223 pta7/siofsync0 in 192 a25 out 222 a13 out 191 ptb0 out 221 a14 out 190 ptb1/ cts1 out 220 a15 out 189 ptb2/ rts1 out 219 a16 out 188 ptb3/rxd1 out 218 a17 out 187 ptb4/txd1 out 217 we2 ( be2 )/dqmul/ iciord out 186 ptb5/scif1ck out 216 we3 ( be3 )/dqmuu/ iciowr out 185 ptb6/ cts0 out 215 d16 out 184 ptb7/ rts0 out 214 d17 out 183 pta0/rxd0 out 213 d18 out 182 pta1/txd0 out 212 d19 out 181 pta2/scif0ck out 211 d20 out 180 pta3/sck_sio0 out
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 800 of 950 rej09b0079-0200 bit pin name i/o bit pin name i/o 179 pta4/siomclk0 out 148 a22 control 178 pta5/rxd_sio0 out 147 a23 control 177 pta6/txd_sio0 out 146 a24 control 176 pta7/siofsync0 out 145 a25 control 175 a13 control 144 ptb0 control 174 a14 control 143 ptb1/ cts1 control 173 a15 control 142 ptb2/ rts1 control 172 a16 control 141 ptb3/rxd1 control 171 a17 control 140 ptb4/txd1 control 170 we2 ( be2 )/dqmul/ iciord control 139 ptb5/scif1ck control 169 we3 ( be3 )/dqmuu/ iciowr control 138 ptb6/ cts0 control 168 d16 control 137 ptb7/ rts0 control 167 d17 control 136 pta0/rxd0 control 166 d18 control 135 pta1/txd0 control 165 d19 control 134 pta2/scif0ck control 164 d20 control 133 pta3/sck_sio0 control 163 d21 control 132 pta4/siomclk0 control 162 d22 control 131 pta5/rxd_sio0 control 161 d23 control 130 pta6/txd_sio0 control 160 d24 control 129 pta7/siofsync0 control 159 d25 control 128 crs1 in 158 d26 control 127 col1 in 157 d27 control 126 tx-clk1 in 156 d28 control 125 rx-er1 in 155 d29 control 124 rx-clk1 in 154 d30 control 123 rx-dv1 in 153 d31 control 122 erxd10 in 152 a18 control 121 erxd11 in 151 a19 control 120 erxd12 in 150 a20 control 119 erxd13 in 149 a21 control 118 mdio1 in
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 801 of 950 rej09b0079-0200 bit pin name i/o bit pin name i/o 117 lnksta1 in 86 tx-en0 out 116 camsen1/irq5 in 85 tx-er0 out 115 crs0 in 84 mdc0 out 114 col0 in 83 mdio0 out 113 tx-clk0 in 82 wol0 out 112 rx-er0 in 81 exout0/tend0 out 111 rx-clk0 in 80 etxd13 control 110 rx-dv0 in 79 etxd12 control 109 erxd00 in 78 etxd11 control 108 erxd01 in 77 etxd10 control 107 erxd02 in 76 tx-en1 control 106 erxd03 in 75 tx-er1 control 105 mdio0 in 74 mdc1 control 104 lnksta0 in 73 mdio1 control 103 camsen0/irq4 in 72 wol1 control 102 md4 in 71 exout1 control 101 md5 in 70 etxd03 control 100 etxd13 out 69 etxd02 control 99 etxd12 out 68 etxd01 control 98 etxd11 out 67 etxd00 control 97 etxd10 out 66 tx-en0 control 96 tx-en1 out 65 tx-er0 control 95 tx-er1 out 64 mdc0 control 94 mdc1 out 63 mdio0 control 93 mdio1 out 62 wol0 control 92 wol1 out 61 exout0 control 91 exout1/tend1 out 60 nmi in 90 etxd03 out 59 irq0/ irl0 in 89 etxd02 out 58 irq1/ irl1 in 88 etxd01 out 57 irq2/ irl2 in 87 etxd00 out 56 irq3/ irl3 in
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 802 of 950 rej09b0079-0200 bit pin name i/o bit pin name i/o 55 dreq0 in 26 ptc4/siofsync1 out 54 dreq1 in 25 ptc5/ ce2a out 53 ptc0/sck_sio1 in 24 ptc6/ ce2b out 52 ptc1/siomclk1 in 23 ptc7/ iois16 out 51 ptc2/rxd_sio1 in 22 cs5b / ce1a out 50 ptc3/txd_sio1 in 21 cs6b / ce1b out 49 ptc4/siofsync1 in 20 asebrkak control 48 ptc5/ ce2a in 19 audsync control 47 ptc6/ ce2b in 18 audck control 46 ptc7/ iois16 in 17 audata3 control 45 md0 in 16 audata2 control 44 md1 in 15 audata1 control 43 md2 in 14 audata0 control 42 md3 in 13 status0 control 41 asebrkak out 12 status1 control 40 audsync out 11 dack0 control 39 audck out 10 dack1 control 38 audata3 out 9 ptc0/sck_sio1 control 37 audata2 out 8 ptc1/siomclk1 control 36 audata1 out 7 ptc2/rxd_sio1 control 35 audata0 out 6 ptc3/txd_sio1 control 34 status0 out 5 ptc4/siofsync1 control 33 status1 out 4 ptc5/ ce2a control 32 dack0 out 3 ptc6/ ce2b control 31 dack1 out 2 ptc7/ iois16 control 30 ptc0/sck_sio1 out 1 cs5b / ce1a control 29 ptc1/siomclk1 out 0 cs6b / ce1b control 28 ptc2/rxd_sio1 out 27 ptc3/txd_sio1 out to tdo note: control is an active-low signal. when control is driven low, the correspondin g pin is driven by the value of out.
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 803 of 950 rej09b0079-0200 23.3.4 id register (sdid) the id register (sdid) is a 32-bit read-only re gister in which sdidh and sdidl are connected. each register is a 16-bit that can be read by cpu. the idcode command is set from the h-udi pin. this register can be read from the tdo when the tap state is shift-dr. writing is disabled. bit bit name initial value r/w description 31 to 0 did31 to did0 refer to description r device id31 to 0 device id register that is stipulated by jtag. device id in this lsi is h'001e200f. upper four bits may be changed by the chip version. sdidh corresponds to bits 31 to 16. sdidl corresponds to bits 15 to 0.
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 804 of 950 rej09b0079-0200 23.4 operation 23.4.1 tap controller figure 23.2 shows the internal states of the tap controller. state transitions basically conform with the jtag standard. test-logic-reset capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-dr-scan run-test/idle 1 0 0 0 0 1 1 1 1 0 0 0 1 11 0 1 1 1 0 capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-ir-scan 0 0 1 0 0 1 0 1 1 10 0 figure 23.2 tap controller state transitions note: the transition condition is the tms value at the rising edge of tck. the tdi value is sampled at the rising edge of tck; shifting occurs at the falling edge of tck. for details on change timing of the tdo value, see sect ion 23.4.3, tdo output timing. the tdo is at high impedance, except with shift-dr and shift-ir states. during the change to trst = 0, there is a transition to test-logic-reset asynchronously with tck.
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 805 of 950 rej09b0079-0200 23.4.2 reset configuration table 23.4 reset configuration asemd0 * 1 resetp trst chip state h l l normal reset and h-udi reset * 4 h normal reset * 4 h l h-udi reset only h normal operation l l l reset hold * 2 h in ase user mode * 3 : normal reset in ase break mode * 3 : resetp assertion is masked h l h-udi reset only h normal operation notes: 1. performs normal mode and ase mode settings asemd0 = h, normal mode asemd0 = l, ase mode 2. in ase mode, reset hold is enabled by driving the resetp and trst pins low for a constant cycle. in this state, th e cpu does not activate, even if resetp is driven high. when trst is driven high, h-udi operation is enab led, but the cpu does not activate. the reset hold state is canceled by the following conditions: ? another resetp assertion (power-on reset) ? trst reassertion 3. ase mode is classified into two modes; ase break mode to execute the firmware program of an emulator and ase user mode to execute the user program. 4. make sure the trst pin is low when the power is turned on. 23.4.3 tdo output timing the timing of data output from the tdo is switched by the command type set in the sdir. the timing changes at the tck falling edge when jtag commands (extest, clamp, highz, sample/preload, idcode, and bypass) are set. this is a timing of the jtag standard. when the h-udi commands (h-udi reset negate, h-udi reset assert, and h-udi interrupt) are set, tdo is output at the tck rising edge ear lier than the jtag standa rd by a half cycle.
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 806 of 950 rej09b0079-0200 tdo (when the h-udi command is set) tck tdo (when the jtag command is set) t tdo t tdo figure 23.3 h-udi data transfer timing 23.4.4 h-udi reset an h-udi reset is executed by inputting an h-udi reset assert command in sdir. an h-udi reset is of the same kind as a power-on reset. an h-udi reset is released by inputting an h-udi reset negate command. the required time between the h-udi reset assert command and h-udi reset negate command is the same as time for keeping the resetp pin low to apply a power-on reset. h-udi reset assert h-udi reset negate sdir chip internal reset cpu state branch to h'a0000000 figure 23.4 h-udi reset 23.4.5 h-udi interrupt the h-udi interrupt function generates an interrupt by setting a command from the h-udi in the sdir. an h-udi interrupt is a general exception/interrupt operation, resulting in a branch to an address based on the vbr value plus offset, and with return by the rte instruction. this interrupt request has a fixed priority level of 15. h-udi interrupts are accepted in sleep mode.
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 807 of 950 rej09b0079-0200 23.5 boundary scan a command can be set in sdir by the h-udi to place the h-udi pins in the boundary scan mode stipulated by jtag. 23.5.1 supported instructions this lsi supports the three essential instructi ons defined in the jtag standard (bypass, sample/preload, and extest) and three op tion instructions (idcode, clamp, and highz). bypass: the bypass instruction is an essential standard instruction that operates the bypass register. this instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. while this instru ction is executing, the test circuit has no effect on the system circuits. the upper four bits of the instruction code are b'1111. sample/preload: the sample/preload instruction inputs values from this lsi?s internal circuitry to the boundary scan register, outputs values fr om the scan path, and loads data onto the scan path. when this instruction is execu ting, this lsi?s input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. this lsi?s system circuits are not affected by execution of this instruction. the upper four bits of the instruction code are 0100. in a sample operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the intern al circuitry to an output pin, is latched into the boundary scan register and read from the scan path. snapshot latching is performed in synchronization with the rise of tck in the capture-dr state. snapshot latching does not affect normal operation of this lsi. in a preload operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the extest instruction. without a preload operation, when the extest instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the extest instruction, the parallel output latch value is constantly output to the output pin). extest: this instruction is provided to test external circuitry when the this lsi is mounted on a printed circuit board. when this instruction is executed, output pins are used to output test data (previously set by the sample/preload instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. if testing is carri ed out by using the extest instruction n times, the nth test data is scanned-in when test data (n-1) is scanned out.
section 23 user debugging interface (h-udi) rev. 2.00 dec. 07, 2005 page 808 of 950 rej09b0079-0200 data loaded into the output pin boundary scan register in the capture-dr state is not used for external circuit testing (it is replaced by a shift operation). the upper four bits of the instruction code are b'0000. idcode: a command can be set in sdir by the h- udi pins to place the h-udi pins in the idcode mode stipulated by jtag. when the h-udi is initialized ( trst is asserted or tap is in the test-logic-reset state), th e idcode mode is entered. clamp, highz: a command can be set in sdir by the h-udi pins to place the h-udi pins in the clamp or highz mode stipulated by jtag. 23.5.2 points for attention 1. boundary scan mode does not cover clock-related signals (extal, extal2, xtal, xtal2, ckio, ckio2). 2. boundary scan mode does not cover reset-related signals ( resetp , resetm ). 3. boundary scan mode does not cover h-udi -related signals (tck, tdi, tdo, tms, trst ). 4. boundary scan mode does not cover the asemd0 pin. 5. when the extest, clamp, and highz commands are set, fix the resetp pin low. 6. when a boundary scan test for other than bypass and idcode is carried out, fix the asemd0 pin high. 23.6 usage notes 1. an h-udi command, once set, will not be modified as long as another command is not re- issued from the h-udi. if the same command is given continuously, the command must be set after a command (bypass, etc.) that does not affect chip operations is once set. 2. in standby mode, the h-udi function cannot be used. to retain the tap status before and after standby mode, keep tck high before entering standby mode. 3. the h-udi is used for emulator connection. therefore, h-udi functions cannot be used when using an emulator. 23.7 advanced user debugger (aud) the aud is a function only for an emulator. for details on the aud, refer to each emulator?s user?s manual.
section 24 list of registers rev. 2.00 dec. 07, 2005 page 809 of 950 rej09b0079-0200 section 24 list of registers the address map gives information on the on-chip i/o registers and is configured as described below. register addresses (by function al module, in order of the corresponding section numbers): ? descriptions by functional module, in order of the corresponding section numbers. ? access to reserved addresses which are not described in this list is prohibited. ? when registers consist of 16 or 32 bits, the addresses of the msbs are given, on the presumption of a big-endian system. register bits: ? bit configurations of the registers are describe d in the same order as the register addresses (by functional module, in order of the corresponding section numbers). ? reserved bits are indicated by ? in the bit name. ? no entry in the bit-name column indicates that the whole register is al located as a counter or for holding data. ? when registers consist of 16 or 32 bits, bits are described from the msb side. the order in which bytes are described is on the presumption of a big-endian system. register states in each operating mode: ? register states are described in the same or der as the register addresses (by functional module, in order of the corresponding section numbers). ? for the initial state of each bit, refer to the de scription of the register in the corresponding section. ? the register states described are for the basic operating modes. if there is a specific reset for an on-chip module, refer to the section on that on-chip module.
section 24 list of registers rev. 2.00 dec. 07, 2005 page 810 of 950 rej09b0079-0200 24.1 register addresses (by functional module, in order of the corresponding section numbers) entries under access size in dicates number of bits. note: access to undefined or reserved addresses is prohibited. since operation or continued operation is not guaranteed when these regist ers are accessed, do not attempt such access. abbreviation module * 1 bus * 2 address size (bit) access size (bit) * 3 intevt l h'ffff ffd8 32 32 intevt2 l h'a400 0000 32 32 tra l h'ffff ffd0 32 32 expevt l h'ffff ffd4 32 32 tea exception handling l h'ffff fffc 32 32 mmucr l h'ffff ffe0 32 32 pteh l h'ffff fff0 32 32 ptel l h'ffff fff4 32 32 ttb mmu l h'ffff fff8 32 32 ccr1 l h'ffff ffec 32 32 ccr2 l h'a400 00b0 32 32 ccr3 cache l h'a400 00b4 32 32 ipra p h'a414 fee2 16 16 iprb p h'a414 fee4 16 16 iprc p h'a414 0016 16 16 iprd p h'a414 0018 16 16 ipre p h'a414 001a 16 16 iprf p h'a408 0000 16 16 iprg p h'a408 0002 16 16 iprh p h'a408 0004 16 16 ipri p h'a408 0006 16 16 icr0 p h'a414 fee0 16 16 icr1 intc p h'a414 0010 16 16
section 24 list of registers rev. 2.00 dec. 07, 2005 page 811 of 950 rej09b0079-0200 abbreviation module * 1 bus * 2 address size (bit) access size (bit) * 3 irr0 p h'a414 0004 8 8 irr1 p h'a414 0006 8 8 irr2 p h'a414 0008 8 8 irr3 p h'a414 000a 8 8 irr4 p h'a414 000c 8 8 irr5 p h'a408 0020 8 8 irr7 p h'a408 0024 8 8 irr8 intc p h'a408 0026 8 8 bara l h'a4ff ffb0 32 32 bamra l h'a4ff ffb4 32 32 bbra l h'a4ff ffb8 16 16 barb l h'a4ff ffa0 32 32 bamrb l h'a4ff ffa4 32 32 bbrb l h'a4ff ffa8 16 16 bdrb l h'a4ff ff90 32 32 bdmrb l h'a4ff ff94 32 32 brcr l h'a4ff ff98 32 32 betr l h'a4ff ff9c 16 16 brsr l h'a4ff ffac 32 32 brdr l h'a4ff ffbc 32 32 basra l h'ffff ffe4 8 8 basrb ubc l h'ffff ffe8 8 8 stbcr p h'a415 ff82 8 8 stbcr2 p h'a415 ff88 8 8 stbcr3 power-down mode p h'a40a 0000 8 8 frqcr p h'a415 ff80 16 16 wtcnt p h'a415 ff84 8 8/16 * 4 wtcsr cpg p h'a415 ff86 8 8/16 * 4 cmncr i h'a4fd 0000 32 32 cs0bcr i h'a4fd 0004 32 32 cs2bcr bsc i h'a4fd 0008 32 32
section 24 list of registers rev. 2.00 dec. 07, 2005 page 812 of 950 rej09b0079-0200 abbreviation module * 1 bus * 2 address size (bit) access size (bit) * 3 cs3bcr i h'a4fd 000c 32 32 cs4bcr i h'a4fd 0010 32 32 cs5abcr i h'a4fd 0014 32 32 cs5bbcr i h'a4fd 0018 32 32 cs6abcr i h'a4fd 001c 32 32 cs6bbcr i h'a4fd 0020 32 32 cs0wcr i h'a4fd 0024 32 32 cs2wcr i h'a4fd 0028 32 32 cs3wcr i h'a4fd 002c 32 32 cs4wcr i h'a4fd 0030 32 32 cs5awcr i h'a4fd 0034 32 32 cs5bwcr i h'a4fd 0038 32 32 cs6awcr i h'a4fd 003c 32 32 cs6bwcr i h'a4fd 0040 32 32 sdcr i h'a4fd 0044 32 32 rtcsr i h'a4fd 0048 32 32 rtcnt i h'a4fd 004c 32 32 rtcor i h'a4fd 0050 32 32 sdmr2 i h'a4fd 4xxx ? 16 sdmr3 bsc i h'a4fd 5xxx ? 16 sar_0 p h'a401 0020 32 16/32 dar_0 p h'a401 0024 32 16/32 dmatcr_0 p h'a401 0028 32 16/32 chcr_0 p h'a401 002c 32 8/16/32 sar_1 p h'a401 0030 32 16/32 dar_1 p h'a401 0034 32 16/32 dmatcr_1 p h'a401 0038 32 16/32 chcr_1 p h'a401 003c 32 8/16/32 sar_2 p h'a401 0040 32 16/32 dar_2 p h'a401 0044 32 16/32 dmatcr_2 dmac p h'a401 0048 32 16/32
section 24 list of registers rev. 2.00 dec. 07, 2005 page 813 of 950 rej09b0079-0200 abbreviation module * 1 bus * 2 address size (bit) access size (bit) * 3 chcr_2 p h'a401 004c 32 8/16/32 sar_3 p h'a401 0050 32 16/32 dar_3 p h'a401 0054 32 16/32 dmatcr_3 p h'a401 0058 32 16/32 chcr_3 p h'a401 005c 32 8/16/32 sar_4 dmac p h'a401 0070 32 16/32 dar_4 p h'a401 0074 32 16/32 dmatcr_4 p h'a401 0078 32 16/32 chcr_4 p h'a401 007c 32 8/16/32 sar_5 p h'a401 0080 32 16/32 dar_5 p h'a401 0084 32 16/32 dmatcr_5 p h'a401 0088 32 16/32 chcr_5 p h'a401 008c 32 8/16/32 dmaor p h'a401 0060 16 8/16 dmars0 p h'a409 0000 16 16 dmars1 p h'a409 0004 16 16 dmars2 p h'a409 0008 16 16 tstr p h'a412 fe92 8 8 tcor0 p h'a412 fe94 32 32 tcnt0 p h'a412 fe98 32 32 tcr0 p h'a412 fe9c 16 16 tcor1 p h'a412 fea0 32 32 tcnt1 p h'a412 fea4 32 32 tcr1 p h'a412 fea8 16 16 tcor2 p h'a412 feac 32 32 tcnt2 p h'a412 feb0 32 32 tcr2 tmu p h'a412 feb4 16 16 r64cnt p h'a413 fec0 8 8 rseccnt p h'a413 fec2 8 8 rmincnt p h'a413 fec4 8 8 rhrcnt rtc p h'a413 fec6 8 8
section 24 list of registers rev. 2.00 dec. 07, 2005 page 814 of 950 rej09b0079-0200 abbreviation module * 1 bus * 2 address size (bit) access size (bit) * 3 rwkcnt p h'a413 fec8 8 8 rdaycnt p h'a413 feca 8 8 rmoncnt p h'a413 fecc 8 8 ryrcnt p h'a413 fece 16 16 rsecar p h'a413 fed0 8 8 rminar p h'a413 fed2 8 8 rhrar p h'a413 fed4 8 8 rwkar p h'a413 fed6 8 8 rdayar p h'a413 fed8 8 8 rmonar p h'a413 feda 8 8 rcr1 p h'a413 fedc 8 8 rcr2 p h'a413 fede 8 8 ryrar p h'a413 fee0 16 16 rcr3 rtc p h'a413 fee4 8 8 scsmr_0 p h'a440 0000 16 16 scbrr_0 p h'a440 0004 8 8 scscr_0 p h'a440 0008 16 16 scftdr_0 p h'a440 000c 8 8 scfsr_0 p h'a440 0010 16 16 scfrdr_0 p h'a440 0014 8 8 scfcr_0 p h'a440 0018 16 16 scfdr_0 p h'a440 001c 16 16 sclsr_0 p h'a440 0024 16 16 scsmr_1 p h'a441 0000 16 16 scbrr_1 p h'a441 0004 8 8 scscr_1 p h'a441 0008 16 16 scftdr_1 p h'a441 000c 8 8 scfsr_1 p h'a441 0010 16 16 scfrdr_1 p h'a441 0014 8 8 scfcr_1 scif p h'a441 0018 16 16
section 24 list of registers rev. 2.00 dec. 07, 2005 page 815 of 950 rej09b0079-0200 abbreviation module * 1 bus * 2 address size (bit) access size (bit) * 3 scfdr_1 p h'a441 001c 16 16 sclsr_1 scif p h'a441 0024 16 16 simdr_0 p h'a442 0000 16 16 siscr_0 p h'a442 0002 16 16 sitdar_0 p h'a442 0004 16 16 sirdar_0 p h'a442 0006 16 16 sicdar_0 p h'a442 0008 16 16 sictr_0 p h'a442 000c 16 16 sifctr_0 p h'a442 0010 16 16 sistr_0 p h'a442 0014 16 16 siier_0 p h'a442 0016 16 16 sitdr_0 p h'a442 0020 32 32 sirdr_0 p h'a442 0024 32 32 sitcr_0 p h'a442 0028 32 32 sircr_0 p h'a442 002c 32 32 simdr_1 p h'a443 0000 16 16 siscr_1 p h'a443 0002 16 16 sitdar_1 p h'a443 0004 16 16 sirdar_1 p h'a443 0006 16 16 sicdar_1 p h'a443 0008 16 16 sictr_1 p h'a443 000c 16 16 sifctr_1 p h'a443 0010 16 16 sistr_1 p h'a443 0014 16 16 siier_1 p h'a443 0016 16 16 sitdr_1 p h'a443 0020 32 32 sirdr_1 p h'a443 0024 32 32 sitcr_1 p h'a443 0028 32 32 sircr_1 siof p h'a443 002c 32 32 ecmr0 i h'a700 0160 32 32 ecsr0 i h'a700 0164 32 32 ecsipr0 etherc (mac-0) i h'a700 0168 32 32
section 24 list of registers rev. 2.00 dec. 07, 2005 page 816 of 950 rej09b0079-0200 abbreviation module * 1 bus * 2 address size (bit) access size (bit) * 3 pir0 i h'a700 016c 32 32 mahr0 i h'a700 0170 32 32 malr0 i h'a700 0174 32 32 rflr0 i h'a700 0178 32 32 psr0 i h'a700 017c 32 32 trocr0 i h'a700 0180 32 32 cdcr0 i h'a700 0184 32 32 lccr0 i h'a700 0188 32 32 cndcr0 i h'a700 018c 32 32 cefcr0 i h'a700 0194 32 32 frecr0 i h'a700 0198 32 32 tsfrcr0 i h'a700 019c 32 32 tlfrcr0 i h'a700 01a0 32 32 rfcr0 i h'a700 01a4 32 32 mafcr0 i h'a700 01a8 32 32 ipgr0 etherc (mac-0) i h'a700 01b4 32 32 ecmr1 i h'a700 0560 32 32 ecsr1 i h'a700 0564 32 32 ecsipr1 i h'a700 0568 32 32 pir1 i h'a700 056c 32 32 mahr1 i h'a700 0570 32 32 malr1 i h'a700 0574 32 32 rflr1 i h'a700 0578 32 32 psr1 i h'a700 057c 32 32 trocr1 i h'a700 0580 32 32 cdcr1 i h'a700 0584 32 32 lccr1 i h'a700 0588 32 32 cndcr1 i h'a700 058c 32 32 cefcr1 i h'a700 0594 32 32 frecr1 i h'a700 0598 32 32 tsfrcr1 etherc (mac-1) i h'a700 059c 32 32
section 24 list of registers rev. 2.00 dec. 07, 2005 page 817 of 950 rej09b0079-0200 abbreviation module * 1 bus * 2 address size (bit) access size (bit) * 3 tlfrcr1 i h'a700 05a0 32 32 rfcr1 i h'a700 05a4 32 32 mafcr1 i h'a700 05a8 32 32 ipgr1 etherc (mac-1) i h'a700 05b4 32 32 arstr etherc i h'a700 0800 32 32 tsu_ctrst i h'a700 0804 32 32 tsu_fwen0 i h'a700 0810 32 32 tsu_fwen1 i h'a700 0814 32 32 tsu_fcm i h'a700 0818 32 32 tsu_bsysl0 i h'a700 0820 32 32 tsu_bsysl1 i h'a700 0824 32 32 tsu_prisl0 i h'a700 0828 32 32 tsu_prisl1 i h'a700 082c 32 32 tsu_fwsl0 i h'a700 0830 32 32 tsu_fwsl1 i h'a700 0834 32 32 tsu_fwslc i h'a700 0838 32 32 tsu_qtagm0 i h'a700 0840 32 32 tsu_qtagm1 i h'a700 0844 32 32 tsu_adqt0 i h'a700 0848 32 32 tsu_adqt1 i h'a700 084c 32 32 tsu_fwsr i h'a700 0850 32 32 tsu_fwinmk i h'a700 0854 32 32 tsu_adsbsy i h'a700 0860 32 32 tsu_ten i h'a700 0864 32 32 tsu_post1 i h'a700 0870 32 32 tsu_post2 i h'a700 0874 32 32 tsu_post3 i h'a700 0878 32 32 tsu_post4 i h'a700 087c 32 32 txnlcr0 i h'a700 0880 32 32 txalcr0 etherc (tsu) i h'a700 0884 32 32
section 24 list of registers rev. 2.00 dec. 07, 2005 page 818 of 950 rej09b0079-0200 abbreviation module * 1 bus * 2 address size (bit) access size (bit) * 3 rxnlcr0 i h'a700 0888 32 32 rxalcr0 i h'a700 088c 32 32 fwnlcr0 i h'a700 0890 32 32 fwalcr0 i h'a700 0894 32 32 txnlcr1 i h'a700 08a0 32 32 txalcr1 i h'a700 08a4 32 32 rxnlcr1 i h'a700 08a8 32 32 rxalcr1 i h'a700 08ac 32 32 fwnlcr1 i h'a700 08b0 32 32 fwalcr1 i h'a700 08b4 32 32 tsu_adrh0 i h'a700 0900 32 32 tsu_adrl0 i h'a700 0904 32 32 tsu_adrh1 i h'a700 0908 32 32 tsu_adrl1 i h'a700 090c 32 32 tsu_adrh2 i h'a700 0910 32 32 tsu_adrl2 i h'a700 0914 32 32 tsu_adrh3 i h'a700 0918 32 32 tsu_adrl3 i h'a700 091c 32 32 tsu_adrh4 i h'a700 0920 32 32 tsu_adrl4 i h'a700 0924 32 32 tsu_adrh5 i h'a700 0928 32 32 tsu_adrl5 i h'a700 092c 32 32 tsu_adrh6 i h'a700 0930 32 32 tsu_adrl6 i h'a700 0934 32 32 tsu_adrh7 i h'a700 0938 32 32 tsu_adrl7 i h'a700 093c 32 32 tsu_adrh8 i h'a700 0940 32 32 tsu_adrl8 i h'a700 0944 32 32 tsu_adrh9 i h'a700 0948 32 32 tsu_adrl9 i h'a700 094c 32 32 tsu_adrh10 etherc (tsu) i h'a700 0950 32 32
section 24 list of registers rev. 2.00 dec. 07, 2005 page 819 of 950 rej09b0079-0200 abbreviation module * 1 bus * 2 address size (bit) access size (bit) * 3 tsu_adrl10 i h'a700 0954 32 32 tsu_adrh11 i h'a700 0958 32 32 tsu_adrl11 i h'a700 095c 32 32 tsu_adrh12 i h'a700 0960 32 32 tsu_adrl12 i h'a700 0964 32 32 tsu_adrh13 i h'a700 0968 32 32 tsu_adrl13 i h'a700 096c 32 32 tsu_adrh14 i h'a700 0970 32 32 tsu_adrl14 i h'a700 0974 32 32 tsu_adrh15 i h'a700 0978 32 32 tsu_adrl15 i h'a700 097c 32 32 tsu_adrh16 i h'a700 0980 32 32 tsu_adrl16 i h'a700 0984 32 32 tsu_adrh17 i h'a700 0988 32 32 tsu_adrl17 i h'a700 098c 32 32 tsu_adrh18 i h'a700 0990 32 32 tsu_adrl18 i h'a700 0994 32 32 tsu_adrh19 i h'a700 0998 32 32 tsu_adrl19 i h'a700 099c 32 32 tsu_adrh20 i h'a700 09a0 32 32 tsu_adrl20 i h'a700 09a4 32 32 tsu_adrh21 i h'a700 09a8 32 32 tsu_adrl21 i h'a700 09ac 32 32 tsu_adrh22 i h'a700 09b0 32 32 tsu_adrl22 i h'a700 09b4 32 32 tsu_adrh23 i h'a700 09b8 32 32 tsu_adrl23 i h'a700 09bc 32 32 tsu_adrh24 i h'a700 09c0 32 32 tsu_adrl24 i h'a700 09c4 32 32 tsu_adrh25 i h'a700 09c8 32 32 tsu_adrl25 etherc (tsu) i h'a700 09cc 32 32
section 24 list of registers rev. 2.00 dec. 07, 2005 page 820 of 950 rej09b0079-0200 abbreviation module * 1 bus * 2 address size (bit) access size (bit) * 3 tsu_adrh26 i h'a700 09d0 32 32 tsu_adrl26 i h'a700 09d4 32 32 tsu_adrh27 i h'a700 09d8 32 32 tsu_adrl27 i h'a700 09dc 32 32 tsu_adrh28 i h'a700 09e0 32 32 tsu_adrl28 i h'a700 09e4 32 32 tsu_adrh29 i h'a700 09e8 32 32 tsu_adrl29 i h'a700 09ec 32 32 tsu_adrh30 i h'a700 09f0 32 32 tsu_adrl30 i h'a700 09f4 32 32 tsu_adrh31 i h'a700 09f8 32 32 tsu_adrl31 etherc (tsu) i h'a700 09fc 32 32 edmr0 i h'a700 0000 32 32 edtrr0 i h'a700 0004 32 32 edrrr0 i h'a700 0008 32 32 tdlar0 i h'a700 000c 32 32 rdlar0 i h'a700 0010 32 32 eesr0 i h'a700 0014 32 32 eesipr0 i h'a700 0018 32 32 trscer0 i h'a700 001c 32 32 rmfcr0 i h'a700 0020 32 32 tftr0 i h'a700 0024 32 32 fdr0 i h'a700 0028 32 32 rmcr0 i h'a700 002c 32 32 edocr0 i h'a700 0030 32 32 fcftr0 i h'a700 0034 32 32 trimd0 i h'a700 003c 32 32 rbwar0 i h'a700 0040 32 32 rdfar0 e-dmac0 i h'a700 0044 32 32
section 24 list of registers rev. 2.00 dec. 07, 2005 page 821 of 950 rej09b0079-0200 abbreviation module * 1 bus * 2 address size (bit) access size (bit) * 3 tbrar0 i h'a700 004c 32 32 tdfar0 e-dmac0 i h'a700 0050 32 32 edmr1 i h'a700 0400 32 32 edtrr1 i h'a700 0404 32 32 edrrr1 i h'a700 0408 32 32 tdlar1 i h'a700 040c 32 32 rdlar1 i h'a700 0410 32 32 eesr1 i h'a700 0414 32 32 eesipr1 i h'a700 0418 32 32 trscer1 i h'a700 041c 32 32 rmfcr1 i h'a700 0420 32 32 tftr1 i h'a700 0424 32 32 fdr1 i h'a700 0428 32 32 rmcr1 i h'a700 042c 32 32 edocr1 i h'a700 0430 32 32 fcftr1 i h'a700 0434 32 32 trimd1 i h'a700 043c 32 32 rbwar1 i h'a700 0440 32 32 rdfar1 i h'a700 0444 32 32 tbrar1 i h'a700 044c 32 32 tdfar1 e-dmac1 i h'a700 0450 32 32 pacr p h'a405 0100 16 16 pbcr p h'a405 0102 16 16 pccr p h'a405 0104 16 16 petcr pfc p h'a405 0106 16 16 padr p h'a405 0120 8 8 pbdr p h'a405 0122 8 8 pcdr i/o port p h'a405 0124 8 8 sdir p h'a410 0200 16 16 sdid/sdidh p h'a410 0214 32/16 32/16 sdidl h-udi p h'a410 0216 16 16
section 24 list of registers rev. 2.00 dec. 07, 2005 page 822 of 950 rej09b0079-0200 notes: 1. module: mmu: memory management unit intc: interrupt controller ubc: user break controller cpg: clock pulse generator bsc: bus state controller dmac: direct memory access controller tmu: timer unit rtc: realtime clock scif0: serial communicati on interface with fifo 0 scif1: serial communicati on interface with fifo 1 siof0: serial i/o with fifo 0 siof1: serial i/o with fifo 1 etherc (mac-0): ethernet controller 0 etherc (mac-1): ethernet controller 1 etherc (tsu): transfer unit for ethernet controller e-dmac0: ethernet controller direct memory access controller 0 e-dmac1: ethernet controller direct memory access controller 1 ipsec: ip security accelerator pfc: pin function controller h-udi: user debugging interface 2. bus: l: connected to the cpu, d sp, ccn, cache, mmu, and ubc. i: connected to the bsc, ccn, cache, dmac, e-dmac0, e-dmac1, and ipsec. p: connected to the bsc and peripheral modules (rtc, tmu, scif0, scif1, siof0, siof1, dmac, port, intc, h-udi, cpg). 3. the access size indicates the size when accessing (read/write) the control registers. if an access is performed in the different size as shown above, the result is not correct data. 4. 16 bits when writing and 8 bits when reading.
section 24 list of registers rev. 2.00 dec. 07, 2005 page 823 of 950 rej09b0079-0200 24.2 register bits register bit names of the on-chip peripheral modules are described below. each line covers eight bits, and 16-bit and 32-bit re gisters are shown as 2 or 4 lines, respectively. register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tra tra tra tra tra tra tra tra tra ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? expevt expevt expevt expevt expevt expevt expevt expevt expevt expevt expevt expevt expevt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? intevt intevt intevt intevt intevt intevt intevt intevt intevt intevt intevt intevt intevt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? intevt2 intevt2 intevt2 intevt2 intevt2 intevt2 intevt2 intevt 2 intevt2 intevt2 intevt2 ? ? tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea excep- tion handl-ing vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn ? ? pteh asid asid asid asid asid asid asid asid mmu
section 24 list of registers rev. 2.00 dec. 07, 2005 page 824 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ? ? ? ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ? v ptel ? pr pr sz c d sh ? ttb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sv mmucr ? ? rc rc ? tf ix at mmu ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ccr1 ? ? ? ? cf cb wt ce ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? le ? ? ? ? ? ? w3load w3lock ccr2 ? ? ? ? ? ? w2load w2lock ? ? ? ? ? ? ? ? csize7 csize6 csize5 csize4 csize3 csize2 csize1 csize0 ? ? ? ? ? ? ? ? ccr3 ? ? ? ? ? ? ? ? cache tmu0 tmu1 ipra tmu2 rtc wdt ref iprb ? ? ? ? ? ? ? ? irq3 irq2 iprc irq1 irq0 intc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 825 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ? ? ? ? ? ? ? ? iprd irq5 irq4 dmac(1) scif0 ipre scif1 ? ? ? ? ipsec dmac(2) iprf ? ? ? ? ? ? ? ? e-dmac(1) e-dmac(2) iprg e-dmac(3) ? ? ? ? ? ? ? ? ? ? ? ? iprh ? ? ? ? siof0 ? ? ? ? ? ? ? ? ipri siof1 ? ? ? ? nmil ? ? ? ? ? ? nmie icr0 ? ? ? ? ? ? ? ? mai irqlvl blmask irlsen irq 51s irq50s irq41s irq40s icr1 irq31s irq30s irq21s irq20s irq11s irq10s irq01s irq00s irr0 ? ? irq5r irq4r irq3r irq2r irq1r irq0r irr1 txi0r bri0r rxi0r eri0r dei3r dei2r dei1r dei0r irr2 ? ? ? ? txi1r bri1r rxi1r eri1r irr3 ? ? ? ? ? cuir prir atir irr4 ? tuni2r tuni1r tuni0r itir ? ? rcmir irr5 ipseci r ? dei5r dei4r ? eint2r eint1r eint0r irr7 cci0r rxi0r txi0r eri0r ? ? ? ? irr8 cci1r rxi1r txi1r eri1r ? ? ? ? intc baa31 baa30 baa29 baa28 baa27 baa26 baa25 baa24 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 bara baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 ubc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 826 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module bama31 bama30 bama29 bama28 bama27 bama26 bama25 bama24 bama23 bama22 bama21 bama20 bama19 bama18 bama17 bama16 bama15 bama14 bama13 bama12 bama11 bama10 bama9 bama8 bamra bama7 bama6 bama5 bama4 bama3 bama2 bama1 bama0 ? ? ? ? ? ? ? ? bbra cda1 cda0 ida1 ida0 rwa1 rwa0 sza1 sza0 bab31 bab30 bab29 bab28 bab27 bab26 bab25 bab24 bab23 bab22 bab21 bab20 bab19 bab18 bab17 bab16 bab15 bab14 bab13 bab12 bab11 bab10 bab9 bab8 barb bab7 bab6 bab5 bab4 bab3 bab2 bab1 bab0 bamb31 bamb30 bamb29 bamb28 bamb27 bamb26 bamb25 bamb24 bamb23 bamb22 bamb21 bamb20 bamb19 bamb18 bamb17 bamb16 bamb15 bamb14 bamb13 bamb12 bamb11 bamb10 bamb9 bamb8 bamrb bamb7 bamb6 bamb5 bamb4 bamb3 bamb2 bamb1 bamb0 bdb31 bdb30 bdb29 bdb28 bdb27 bdb26 bdb25 bdb24 bdb23 bdb22 bdb21 bdb20 bdb19 bdb18 bdb17 bdb16 bdb15 bdb14 bdb13 bdb12 bdb11 bdb10 bdb9 bdb8 bdrb bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 bdb0 bdmb31 bdmb30 bdmb29 bdmb28 bdmb27 bdmb26 bdmb25 bdmb24 bdmb23 bdmb22 bdmb21 bdmb20 bdmb19 bdmb18 bdmb17 bdmb16 bdmb15 bdmb14 bdmb13 bdmb12 bdmb11 bdmb10 bdmb9 bdmb8 bdmrb bdmb7 bdmb6 bdmb5 bdmb4 bdmb3 bdmb2 bdmb1 bdmb0 ? ? ? ? ? ? xye xys bbrb cdb1 cdb0 idb1 idb0 rwb1 rwb0 szb1 szb0 ? ? ? ? ? ? ? ? ? ? basma basmb ? ? ? ? scmfca scmfcb scmfda scmfdb pcte pcba ? ? brcr dbeb pcbb ? ? seq ? ? etbe ? ? ? ? bet11 bet10 bet9 bet8 betr bet7 bet6 bet5 bet4 bet3 bet2 bet1 bet0 ubc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 827 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module svf ? ? ? bsa27 bsa26 bsa25 bsa24 bsa23 bsa22 bsa21 bsa20 bsa19 bsa18 bsa17 bsa16 bsa15 bsa14 bsa13 bsa12 bsa11 bsa10 bsa9 bsa8 brsr bsa7 bsa6 bsa5 bsa4 bsa3 bsa2 bsa1 bsa0 dvf ? ? ? bda27 bda26 bda25 bda24 bda23 bda22 bda21 bda20 bda19 bda18 bda17 bda16 bda15 bda14 bda13 bda12 bda11 bda10 bda9 bda8 brdr bda7 bda6 bda5 bda4 bda3 bda2 bda1 bda0 basra basa7 basa6 basa5 basa4 basa3 basa2 basa1 basa0 basrb basb7 basb6 basb5 basb4 basb3 basb2 basb1 basb0 ubc stbcr stby ? ? ? ? mstp2 mstp1 ? stbcr2 mstp10 mstp9 mstp8 mstp7 mstp6 mstp5 ? mstp3 stbcr3 mstp37 ? ? ? mstp33 mest32 mstp31 mstp30 power- down mode ? ? ? ckoen ? ? stc1 stc0 frqcr ? ? ifc1 ifc0 ? pfc2 pfc1 pfc0 wtcnt wtcsr tme wt/it rsts wovf iovf cks2 cks1 cks0 cpg ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? waitsel bsd ? map block dprty1 dprty0 dmaiw2 cmncr dmaiw1 dmaiw0 dmaiwa ? endian ck2drv hizmem hizcnt ? iww2 iww1 iww0 iwrwd2 iwrwd1 iwrwd0 iwrws2 iwrws1 iwrws0 iwrrd2 iwrrd1 iwrrd0 iwrrs2 iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? csnbcr (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) ? ? ? ? ? ? ? ? bsc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 828 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bas ben ? ? ? ? ? ? ? ? bw1 bw1 ? bw0 bw0 ? ? ? ? ? ? ? ? ? sw1 ? ? sw0 ? ? wr3 w3 w3 wr2 w2 w2 wr1 w1 w1 cs0wcr * 1 wr0 w0 w0 wm wm wm ? ? ? ? ? ? ? ? ? ? ? ? hw1 ? ? hw0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bas ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? wr3 ? wr2 ? wr1 a2cl1 cs2wcr * 2 wr0 a2cl0 wm ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cs3wcr * 2 ? ? ? ? ? ? bas ? ? ? ? ? ? ? ? ? bsc ? ? ? trp1 ? trp0 ? ? ? trcd1 wr3 trcd0 wr2 ? wr1 a3cl1 cs3wcr * 2 wr0 a3cl0 wm ? ? ? ? trwl1 ? trwl0 ? ? ? trc1 ? trc0
section 24 list of registers rev. 2.00 dec. 07, 2005 page 829 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bas ben ? ? ww2 ? ww1 bw1 ww0 bw0 ? ? ? ? ? ? sw1 sw1 sw0 sw0 wr3 pcw3w3 wr2 pcw2w2 wr1 pcw1w1 c s4wcr * 3 wr0 pcw0w0 wm wm ? ? ? ? ? ? ? ? hw1 hw1 hw0 hw0 ? ? ? ? ? ? ? ? ? ? ? ? ? ww2 ww1 ww0 ? ? ? sw1 sw0 wr3 wr2 wr1 cs5a wcr * 4 wr0 wm ? ? ? ? hw1 hw0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sa1 bas sa0 ? ? ww2 ? ww1 ? ww0 ? ? ? ? ted3 ? ted2 sw1 ted1 sw0 ted0 wr3 pcw3 wr2 pcw2 wr1 pcw1 cs5bwcr * 5 wr0 pcw0 wm wm ? ? ? ? ? teh3 ? teh2 hw1 teh1 hw0 teh0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sw1 sw0 wr3 wr2 wr1 cs6awcr * 4 wr0 wm ? ? ? ? hw1 hw0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sa1 bas sa0 ? ? ? ? ? ? ? ? ? ? ? ted3 ? ted2 sw1 ted1 sw0 ted0 wr3 pcw3 wr2 pcw2 wr1 pcw1 cs6bwcr * 6 wr0 pcw0 wm wm ? ? ? ? ? teh3 ? teh2 hw1 teh1 hw0 teh0 bsc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 830 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ? ? ? ? ? ? ? ? ? ? ? a2row1 a2row0 ? a2col1 a2col0 ? ? deep slow rfsh rmode pdown bactv sdcr ? ? ? a3row1 a3row0 ? a3col1 a3col0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rtcsr cmf cmie cks2 cks1 cks0 rrc2 rrc1 rrc0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rtcnt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rtcor bsc sar_n (n = 0 to 5) dar_n (n = 0 to 5) dmatcr_n (n = 0 to 5) dmac
section 24 list of registers rev. 2.00 dec. 07, 2005 page 831 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ? ? ? ? ? ? ? ? do tl ? ? ? ? am al dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 chcr_n (n = 0, 1) dl ds tb ts1 ts0 ie te de ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 chcr_m (m = 2 to 5) ? ? tb ts1 ts0 ie te de ? ? ? ? ? ? pr1 pr0 dmaor ? ? ? ? ? ae nmif dme c1mid5 c1mid4 c1mid3 c1mid2 c1mid1 c1mid0 c1rid1 c1rid0 dmars0 c0mid5 c0mid4 c0mid3 c0mid2 c0mid1 c0mid0 c0rid1 c0rid0 c3mid5 c3mid4 c3mid3 c3mid2 c3mid1 c3mid0 c3rid1 c3rid0 dmars1 c2mid5 c2mid4 c2mid3 c2mid2 c2mid1 c2mid0 c2rid1 c2rid0 c5mid5 c5mid4 c5mid3 c5mid2 c5mid1 c5mid0 c5rid1 c5rid0 dmars2 c4mid5 c4mid4 c4mid3 c4mid2 c4mid1 c4mid0 c4rid1 c4rid0 dmac tstr ? ? ? ? ? str2 str1 str0 ? ? ? ? ? ? ? unf tcrn (n = 0 to 2) ? ? unie ? ? tpsc2 tpsc1 tpsc0 tcorn (n = 0 to 2) tcntn (n = 0 to 2) tmu
section 24 list of registers rev. 2.00 dec. 07, 2005 page 832 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module r64cnt ? 1hz 2hz 4hz 8hz 16hz 32hz 64hz rseccnt ? 10-unit of second 1-unit of second rmincnt ? 10-unit of minute 1-unit of minute rhrcnt ? ? 10-unit of hour 1-unit of hour rwkcnt ? ? ? ? ? day of week code rdaycnt ? ? 10-unit of date 1-unit of date rmoncnt ? ? ? 10-unit of month 1-unit of month 1000-unit of year 100-unit of year ryrcnt 10-unit of year 1-unit of year rsecar enb 10-unit of second 1-unit of second rminar enb 10-unit of minute 1-unit of minute rhrar enb ? 10-unit of hour 1-unit of hour rwkar enb ? ? ? ? day of week code rdayar enb ? 10-unit of date 1-unit of date rmonar enb ? ? 10-unit of month 1-unit of month 1000-unit of year 100-unit of year ryrar 10-unit of year 1-unit of year rcr1 cf ? ? cie aie ? ? af rcr2 pef pes2 pes1 pes0 rtcen adj reset start rcr3 yaen ? ? ? ? ? ? ? rtc scfrdr_n (n = 0, 1) scftdr_n (n = 0, 1) ? ? ? ? ? ? ? ? scsmr_n (n = 0, 1) c/ a chr pe o/ e stop ? cks1 cks0 ? ? ? ? ? ? ? ? scscr_n (n = 0, 1) tie rie te re reie ? cke1 cke0 scif
section 24 list of registers rev. 2.00 dec. 07, 2005 page 833 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module per3 per2 per1 per0 fer3 fer2 fer1 fer0 scfsr_n (n = 0, 1) er tend tdfe brk fer per rdf dr scbrr_n (n = 0, 1) ? ? ? ? ? rstrg2 rstrg1 rstrg0 scfcr_n (n = 0, 1) rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop ? ? ? t4 t3 t2 t1 t0 scfdr_n (n = 0, 1) ? ? ? r4 r3 r2 r1 r0 ? ? ? ? ? ? ? ? sclsr_n (n = 0, 1) ? ? ? ? ? ? ? orer scif trmd1 trmd0 ? redg fl3 fl2 fl1 fl0 simdr_n (n = 0, 1) txdiz lsbf rcim ? ? ? ? ? mssel msimm ? brps4 brps3 brps2 brps1 brps0 siscr_n (n = 0, 1) ? ? ? ? ? brdv2 brdv1 brdv0 tdle ? ? ? tdla3 tdla2 tdla1 tdla0 sitdar_n (n = 0, 1) tdre tlrep ? ? tdra3 tdra2 tdra1 tdra0 rdle ? ? ? rdla3 rdla2 rdla1 rdla0 sirdar_n (n = 0, 1) rdre ? ? ? rdra3 rdra2 rdra1 rdra0 cd0e ? ? ? cd0a3 cd0a2 cd0a1 cd0a0 sicdar_n (n = 0, 1) cd1e ? ? ? cd1a3 cd1a2 cd1a1 cd1a0 scke fse ? ? ? ? txe rxe sictr_n (n = 0, 1) ? ? ? ? ? ? txrst rxrst tfwm2 tfwm1 tfwm0 tfua4 tfua3 tfua2 tfua1 tfua0 sifctr_n (n = 0, 1) rfwm2 rfwm1 rfwm0 rfua4 rfua3 rfua2 rfua1 rfua0 ? tcrdy tfemp tdreq ? rcrdy rfful rdreq sistr_n (n = 0, 1) ? ? ? fserr tfovr tfudr rfudr rfovr ? tcrdye tfempe tdreqe ? rcrdye rffule rdreqe siier_n (n = 0, 1) ? ? ? fserre tfovre tfudre rfudre rfovre siof
section 24 list of registers rev. 2.00 dec. 07, 2005 page 834 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module sitdl15 sitdl14 sitdl13 sitdl12 sitdl11 sitdl10 sitdl9 sitdl8 sitdl7 sitdl6 sitdl5 sitdl4 sitdl3 sitdl2 sitdl1 sitdl0 sitdr15 sitdr14 sitdr13 sitdr12 sitdr11 sitdr10 sitdr9 sitdr8 sitdr_n (n = 0, 1) sitdr7 sitdr6 sitdr5 sitdr4 sitdr3 sitdr2 sitdr1 sitdr0 sirdl15 sirdl14 sirdl13 sirdl12 sirdl11 sirdl10 sirdl9 sirdl8 sirdl7 sirdl6 sirdl5 sirdl4 sirdl3 sirdl2 sirdl1 sirdl0 sirdr15 sirdr14 sirdr13 sirdr12 sirdr11 sirdr10 sirdr9 sirdr8 sirdr_n (n = 0, 1) sirdr7 sirdr6 sirdr5 sirdr4 sirdr3 sirdr2 sirdr1 sirdr0 sitc015 sitc014 sitc013 sitc012 sitc011 sitc010 sitc09 sitc08 sitc07 sitc06 sitc05 sitc04 sitc03 sitc02 sitc01 sitc00 sitc115 sitc114 sitc113 sitc112 sitc111 sitc110 sitc19 sitc18 sitcr_n (n = 0, 1) sitc17 sitc16 sitc15 sitc14 sitc13 sitc12 sitc11 sitc10 sirc015 sirc014 sirc013 sirc012 sirc011 sirc010 sirc09 sirc08 sirc07 sirc06 sirc05 sirc04 sirc03 sirc02 sirc01 sirc00 sirc115 sirc114 sirc113 sirc112 sirc111 sirc110 sirc19 sirc18 sircr_n (n = 0, 1) sirc17 sirc16 sirc15 sirc14 sirc13 sirc12 sirc11 sirc10 siof ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? arstr ? ? ? ? ? ? ? arst ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mct prcef ? ? mpde ? ecmrn (n = 0, 1) ? re te ? ilb elb dm prm ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ecsrn (n = 0, 1) ? ? ? ? ? lchng mpd icd etherc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 835 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ecsiprn (n = 0, 1) ? ? ? ? ? lchngip mpdip icdip ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pirn (n = 0, 1) ? ? ? ? mdi mdo mmd mdc ma47 ma46 ma45 ma44 ma43 ma42 ma41 ma40 ma39 ma38 ma37 ma36 ma35 ma34 ma33 ma32 ma31 ma30 ma29 ma28 ma27 ma26 ma25 ma24 mahrn (n = 0, 1) ma23 ma22 ma21 ma20 ma19 ma18 ma17 ma16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ma15 ma14 ma13 ma12 ma11 ma10 ma9 ma8 malrn (n = 0, 1) ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rfl11 rfl10 rfl9 rfl8 rflrn (n = 0, 1) rfl7 rfl6 rfl5 rfl4 rfl3 rfl2 rfl1 rfl0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? psrn (n = 0, 1) ? ? ? ? ? ? ? lmon troc31 troc30 troc29 troc28 troc27 troc26 troc25 troc24 troc23 troc22 troc21 troc20 troc19 troc18 troc17 troc16 troc15 troc14 troc13 troc12 troc11 troc10 troc9 troc8 trocrn (n = 0, 1) troc7 troc6 troc5 troc4 troc3 troc2 troc1 troc0 etherc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 836 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module cosdc31 cosdc30 cosdc29 cosdc28 c osdc27 cosdc26 cosdc25 cosdc24 cosdc23 cosdc22 cosdc21 cosdc20 c osdc19 cosdc18 cosdc17 cosdc16 cosdc15 cosdc14 cosdc13 cosdc12 cosdc11 cosdc10 cosdc9 cosdc8 cdcrn (n = 0, 1) cosdc7 cosdc6 cosdc5 cosdc4 cosdc3 cosdc2 cosdc1 cosdc0 lcc31 lcc30 lcc29 lcc28 lcc27 lcc26 lcc25 lcc24 lcc23 lcc22 lcc21 lcc20 lcc19 lcc18 lcc17 lcc16 lcc15 lcc14 lcc13 lcc12 lcc11 lcc10 lcc9 lcc8 lccrn (n = 0, 1) lcc7 lcc6 lcc5 lcc4 lcc3 lcc2 lcc1 lcc0 cndc31 cndc30 cndc29 cndc28 cndc27 cndc26 cndc25 cndc24 cndc23 cndc22 cndc21 cndc20 cndc19 cndc18 cndc17 cndc16 cndc15 cndc14 cndc13 cndc12 cndc11 cndc10 cndc9 cndc8 cndcrn (n = 0, 1) cndc7 cndc6 cndc5 cndc4 cndc3 cndc2 cndc1 cndc0 cefc31 cefc30 cefc29 cefc28 cefc27 cefc26 cefc25 cefc24 cefc23 cefc22 cefc21 cefc20 cefc19 cefc18 cefc17 cefc16 cefc15 cefc14 cefc13 cefc12 cefc11 cefc10 cefc9 cefc8 cefcrn (n = 0, 1) cefc7 cefc6 cefc5 cefc4 cefc3 cefc2 cefc1 cefc0 frec31 frec30 frec29 frec28 frec27 frec26 frec25 frec24 frec23 frec22 frec21 frec20 frec19 frec18 frec17 frec16 frec15 frec14 frec13 frec12 frec11 frec10 frec9 frec8 frecrn (n = 0, 1) frec7 frec6 frec5 frec4 frec3 frec2 frec1 frec0 tsfc31 tsfc30 tsfc29 tsfc28 tsfc27 tsfc26 tsfc25 tsfc24 tsfc23 tsfc22 tsfc21 tsfc20 tsfc19 tsfc18 tsfc17 tsfc16 tsfc15 tsfc14 tsfc13 tsfc12 tsfc11 tsfc10 tsfc9 tsfc8 tsfrcrn (n = 0, 1) tsfc7 tsfc6 tsfc5 tsfc4 tsfc3 tsfc2 tsfc1 tsfc0 etherc tlfc31 tlfc30 tlfc29 tlfc28 tlfc27 tlfc26 tlfc25 tlfc24 tlfc23 tlfc22 tlfc21 tlfc20 tlfc19 tlfc18 tlfc17 tlfc16 tlfc15 tlfc14 tlfc13 tlfc12 tlfc11 tlfc10 tlfc9 tlfc8 tlfrcrn (n = 0, 1) tlfc7 tlfc6 tlfc5 tlfc4 tlfc3 tlfc2 tlfc1 tlfc0
section 24 list of registers rev. 2.00 dec. 07, 2005 page 837 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module rfc31 rfc30 rfc29 rfc28 rfc27 rfc26 rfc25 rfc24 rfc23 rfc22 rfc21 rfc20 rfc19 rfc18 rfc17 rfc16 rfc15 rfc14 rfc13 rfc12 rfc11 rfc10 rfc9 rfc8 rfcrn (n = 0, 1) rfc7 rfc6 rfc5 rfc4 rfc3 rfc2 rfc1 rfc0 mafc31 mafc30 mafc29 mafc28 mafc27 mafc26 mafc25 mafc24 mafc23 mafc22 mafc21 mafc20 mafc19 mafc18 mafc17 mafc16 mafc15 mafc14 mafc13 mafc12 mafc11 mafc10 mafc9 mafc8 mafcrn (n = 0, 1) mafc7 mafc6 mafc5 mafc4 mafc3 mafc2 mafc1 mafc0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ipgrn (n = 0, 1) ? ? ? ipg4 ipg3 ipg2 ipg1 ipg0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ctrst tsu_ctrs t ? ? ? ? ? ? ? ? fwen0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tsu_fwen 0 ? ? ? ? ? ? ? ? fwen1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tsu_ fwen1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tsu_fcm ? ? ? ? ? fcm2 fcm1 fcm0 etherc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 838 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tsu_ bsysl0 ? ? bsysl05 bsysl04 bsysl03 bsysl02 bsysl01 bsysl00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tsu_ bsysl1 ? ? bsysl15 bsysl14 bsysl13 bsysl12 bsysl11 bsysl10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? primd02 prim d01 primd00 ? ? ? ? tsu_ prisl0 prisl07 prisl06 prisl05 prisl04 prisl03 prisl02 prisl01 prisl00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? primd12 prim d11 primd10 ? ? ? ? tsu_ prisl1 prisl17 prisl16 prisl15 prisl14 prisl13 prisl12 prisl11 prisl10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? fw40 fw30 fw20 fw10 tsu_ fwsl0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? fw41 fw31 fw21 fw11 tsu_ fwsl1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? postenu postenl ? ? ? ? tsu_ fwslc camsel03 camsel02 camsel01 camsel00 camsel13 camsel12 camsel11 camsel10 etherc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 839 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tsu_ qtagm0 ? ? ? ? ? ? qtagm01 qtagm00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tsu_ qtagm1 ? ? ? ? ? ? qtagm11 qtagm10 ? ? ? ? tint40 tint30 tint20 tint10 ovf0 rbsy0 ? rint50 rint40 rint30 rint20 rint10 ? ? ? ? tint41 tint31 tint21 tint11 tsu_ fwsr ovf1 rbsy1 ? rint51 rint41 rint31 rint21 rint11 ? ? ? ? tintm40 tintm30 tintm20 tintm10 ovfm0 rbsym0 ? rintm50 rintm40 rintm30 rintm20 rintm10 ? ? ? ? tintm41 tintm31 tintm21 tintm11 tsu_ fwinmk ovfm1 rbsym1 ? rintm51 rintm41 rintm31 rintm21 rintm11 qtag031 qtag030 qtag029 qtag028 qt ag027 qtag026 qtag025 qtag024 qtag023 qtag022 qtag021 qtag020 qt ag019 qtag018 qtag017 qtag016 qtag015 qtag014 qtag013 ? qtag011 qtag010 qtag009 qtag008 tsu_ adqt0 qtag007 qtag006 qtag005 qtag004 qt ag003 qtag002 qtag001 qtag000 qtag131 qtag130 qtag129 qtag128 qt ag127 qtag126 qtag125 qtag124 qtag123 qtag122 qtag121 qtag120 qt ag119 qtag118 qtag117 qtag116 qtag115 qtag114 qtag113 ? qtag111 qtag110 qtag109 qtag108 tsu_ adqt1 qtag107 qtag106 qtag105 qtag104 qt ag103 qtag102 qtag101 qtag100 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tsu_ adsbsy ? ? ? ? ? ? ? adsbsy etherc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 840 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ten0 ten1 ten2 ten3 ten4 ten5 ten6 ten7 ten8 ten9 ten10 ten11 ten12 ten13 ten14 ten15 ten16 ten17 ten18 ten19 ten20 ten21 ten22 ten23 tsu_ten ten24 ten25 ten26 ten27 ten28 ten29 ten30 ten31 post03 post02 post01 post00 post13 post12 post11 post10 post23 post22 post21 post20 post33 post32 post31 post30 post43 post42 post41 post40 post53 post52 post51 post50 tsu_ post1 post63 post62 post61 post60 post73 post72 post71 post70 post83 post82 post81 post80 post93 post92 post91 post90 post103 post102 post101 post100 post113 post112 post111 post110 post123 post122 post121 post120 post133 post132 post131 post130 tsu_ post2 post143 post142 post141 post140 post153 post152 post151 post150 post163 post162 post161 post160 post173 post172 post171 post170 post183 post182 post181 post180 post193 post192 post191 post190 post203 post202 post201 post200 post213 post212 post211 post210 tsu_ post3 post223 post222 post221 post220 post233 post232 post231 post230 post243 post242 post241 post240 post253 post252 post251 post250 post263 post262 post261 post260 post273 post272 post271 post270 post283 post282 post281 post280 post293 post292 post291 post290 tsu_ post4 post303 post302 post301 post300 post313 post312 post311 post310 adrhn31 adrhn30 adrhn29 adrhn28 a drhn27 adrhn26 adrhn25 adrhn24 adrhn23 adrhn22 adrhn21 adrhn20 a drhn19 adrhn18 adrhn17 adrhn16 adrhn15 adrhn14 adrhn13 adrhn12 adrhn11 adrhn10 adrhn9 adrhn8 tsu_ adrhn (n = 0 to 31) adrhn7 adrhn6 adrhn5 adrhn4 adrhn3 adrhn2 adrhn1 adrhn0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? adrln15 adrln14 adrln13 adrln12 adrln11 adrln10 adrln9 adrln8 tsu_ adrln (n = 0 to 31) adrln7 adrln6 adrln5 adrln4 adrln3 adrln2 adrln1 adrln0 etherc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 841 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ntc031 ntc030 ntc029 ntc028 ntc027 ntc026 ntc025 ntc024 ntc023 ntc022 ntc021 ntc020 ntc019 ntc018 ntc017 ntc016 ntc015 ntc014 ntc013 ntc012 ntc011 ntc010 ntc009 ntc008 txnlcr0 ntc007 ntc006 ntc005 ntc004 ntc003 ntc002 ntc001 ntc000 tc031 tc030 tc029 tc028 tc027 tc026 tc025 tc024 tc023 tc022 tc021 tc020 tc019 tc018 tc017 tc016 tc015 tc014 tc013 tc012 tc011 tc010 tc009 tc008 txalcr0 tc007 tc006 tc005 tc004 tc003 tc002 tc001 tc000 nrc031 nrc030 nrc029 nrc028 nrc027 nrc026 nrc025 nrc024 nrc023 nrc022 nrc021 nrc020 nrc019 nrc018 nrc017 nrc016 nrc015 nrc014 nrc013 nrc012 nrc011 nrc010 nrc009 nrc008 rxnlcr0 nrc007 nrc006 nrc005 nrc004 nrc003 nrc002 nrc001 nrc000 rc031 rc030 rc029 rc028 rc027 rc026 rc025 rc024 rc023 rc022 rc021 rc020 rc019 rc018 rc017 rc016 rc015 rc014 rc013 rc012 rc011 rc010 rc009 rc008 rxalcr0 rc007 rc006 rc005 rc004 rc003 rc002 rc001 rc000 nfc031 nfc030 nfc029 nfc028 nfc027 nfc026 nfc025 nfc024 nfc023 nfc022 nfc021 nfc020 nfc019 nfc018 nfc017 nfc016 nfc015 nfc014 nfc013 nfc012 nfc011 nfc010 nfc009 nfc008 fwnlcr0 nfc007 nfc006 nfc005 nfc004 nfc003 nfc002 nfc001 nfc000 fc031 fc030 fc029 fc028 fc027 fc026 fc025 fc024 fc023 fc022 fc021 fc020 fc019 fc018 fc017 fc016 fc015 fc014 fc013 fc012 fc011 fc010 fc009 fc008 fwalcr0 fc007 fc006 fc005 fc004 fc003 fc002 fc001 fc000 ntc131 ntc130 ntc129 ntc128 ntc127 ntc126 ntc125 ntc124 ntc123 ntc122 ntc121 ntc120 ntc119 ntc118 ntc117 ntc116 ntc115 ntc114 ntc113 ntc112 ntc111 ntc110 ntc109 ntc108 txnlcr1 ntc107 ntc106 ntc105 ntc104 ntc103 ntc102 ntc101 ntc100 etherc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 842 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module tc131 tc130 tc129 tc128 tc127 tc126 tc125 tc124 tc123 tc122 tc121 tc120 tc119 tc118 tc117 tc116 tc115 tc114 tc113 tc112 tc111 tc110 tc109 tc108 txalcr1 tc107 tc106 tc105 tc104 tc103 tc102 tc101 tc100 nrc131 nrc130 nrc129 nrc128 nrc127 nrc126 nrc125 nrc124 nrc123 nrc122 nrc121 nrc120 nrc119 nrc118 nrc117 nrc116 nrc115 nrc114 nrc113 nrc112 nrc111 nrc110 nrc109 nrc108 rxnlcr1 nrc107 nrc106 nrc105 nrc104 nrc103 nrc102 nrc101 nrc100 rc131 rc130 rc129 rc128 rc127 rc126 rc125 rc124 rc123 rc122 rc121 rc120 rc119 rc118 rc117 rc116 rc115 rc114 rc113 rc112 rc111 rc110 rc109 rc108 rxalcr1 rc107 rc106 rc105 rc104 rc103 rc102 rc101 rc100 nfc131 nfc130 nfc129 nfc128 nfc127 nfc126 nfc125 nfc124 nfc123 nfc122 nfc121 nfc120 nfc119 nfc118 nfc117 nfc116 nfc115 nfc114 nfc113 nfc112 nfc111 nfc110 nfc109 nfc108 fwnlcr1 nfc107 nfc106 nfc105 nfc104 nfc103 nfc102 nfc101 nfc100 fc131 fc130 fc129 fc128 fc127 fc126 fc125 fc124 fc123 fc122 fc121 fc120 fc119 fc118 fc117 fc116 fc115 fc114 fc113 fc112 fc111 fc110 fc109 fc108 fwalcr1 fc107 fc106 fc105 fc104 fc103 fc102 fc101 fc100 etherc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? edmrn (n = 0, 1) ? ? dl1 dl0 ? ? ? swr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? edtrrn (n = 0, 1) ? ? ? ? ? ? ? tr e-dmac
section 24 list of registers rev. 2.00 dec. 07, 2005 page 843 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? edrrrn (n = 0, 1) ? ? ? ? ? ? ? rr tdla31 tdla30 tdla29 tdla28 tdla27 tdla26 tdla25 tdla24 tdla23 tdla22 tdla21 tdla20 tdla19 tdla18 tdla17 tdla16 tdla15 tdla14 tdla13 tdla12 tdla11 tdla10 tdla9 tdla8 tdlarn (n = 0, 1) tdla7 tdla6 tdla5 tdla4 tdla3 tdla2 tdla1 tdla0 rdla31 rdla30 rdla29 rdla28 rdla27 rdla26 rdla25 rdla24 rdla23 rdla22 rdla21 rdla20 rdla19 rdla18 rdla17 rdla16 rdla15 rdla14 rdla13 rdla12 rdla11 rdla10 rdla9 rdla8 rdlarn (n = 0, 1) rdla7 rdla6 rdla5 rdla4 rdla3 rdla2 rdla1 rdla0 ? twb ? ? ? tabt rabt rfcof ade eci tc tde tfuf fr rde rfof ? ? ? ? cnd dlc cd tro eesrn (n = 0, 1) rmaf ? ? rrf rtlf rtsf pre cerf ? twbip ? ? ? tabtip rabtip rfcofip adeip eciip tcip tdeip tfufip frip rdeip rfofip ? ? ? ? cndip dlcip cdip troip eesiprn (n = 0, 1) rmafip ? ? rrfip rtlfip rtsfip preip cerfip ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? trscern (n = 0, 1) rmafce ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mfc15 mfc14 mfc13 mfc12 mfc11 mfc10 mfc9 mfc8 rmfcrn (n = 0, 1) mfc7 mfc6 mfc5 mfc4 mfc3 mfc2 mfc1 mfc0 e-dmac
section 24 list of registers rev. 2.00 dec. 07, 2005 page 844 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tft10 tft9 tft8 tftrn (n = 0, 1) tft7 tft6 tft5 tft4 tft3 tft2 tft1 tft0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tfd2 tfd1 tfd0 fdrn (n = 0, 1) ? ? ? ? ? rfd2 rfd1 rfd0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rmcrn (n = 0, 1) ? ? ? ? ? ? ? rnc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? edocrn (n = 0, 1) ? ? ? ? fec aec ? ? rbwa31 rbwa30 rbwa29 rbwa28 rbwa27 rbwa26 rbwa25 rbwa24 rbwa23 rbwa22 rbwa21 rbwa20 rbwa19 rbwa18 rbwa17 rbwa16 rbwa15 rbwa14 rbwa13 rbwa12 rbwa11 rbwa10 rbwa9 rbwa8 rbwarn (n = 0, 1) rbwa7 rbwa6 rbwa5 rbwa4 rbwa3 rbwa2 rbwa1 rbwa0 rdfa31 rdfa30 rdfa29 rdfa28 rdfa27 rdfa26 rdfa25 rdfa24 rdfa23 rdfa22 rdfa21 rdfa20 rdfa19 rdfa18 rdfa17 rdfa16 rdfa15 rdfa14 rdfa13 rdfa12 rdfa11 rdfa10 rdfa9 rdfa8 rdfarn (n = 0, 1) rdfa7 rdfa6 rdfa5 rdfa4 rdfa3 rdfa2 rdfa1 rdfa0 tbra31 tbra30 tbra29 tbra28 tbra27 tbra26 tbra25 tbra24 tbra23 tbra22 tbra21 tbra20 tbra19 tbra18 tbra17 tbra16 tbra15 tbra14 tbra13 tbra12 tbra11 tbra10 tbra9 tbra8 tbrarn (n = 0, 1) tbra7 tbra6 tbra5 tbra4 tbra3 tbra2 tbra1 tbra0 e-dmac
section 24 list of registers rev. 2.00 dec. 07, 2005 page 845 of 950 rej09b0079-0200 register abbrevia- tion bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module tdfa31 tdfa30 tdfa29 tdfa28 tdfa27 tdfa26 tdfa25 tdfa24 tdfa23 tdfa22 tdfa21 tdfa20 tdfa19 tdfa18 tdfa17 tdfa16 tdfa15 tdfa14 tdfa13 tdfa12 tdfa11 tdfa10 tdfa9 tdfa8 tdfarn (n = 0, 1) tdfa7 tdfa6 tdfa5 tdfa4 tdfa3 tdfa2 tdfa1 tdfa0 ? ? ? ? ? ? ? ? ? ? ? ? ? rff2 rff1 rff0 ? ? ? ? ? ? ? ? fcftrn (n = 0, 1) ? ? ? ? ? rfd2 rfd1 rfd0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? trimdn (n = 0, 1) ? ? ? ? ? ? ? tis e-dmac padr pa7dt pa6dt pa5dt pa4dt pa3dt pa2dt pa1dt pa0dt pbdr pb7dt pb6dt pb5dt pb4dt pb3dt pb2dt pb1dt pb0dt pcdr pc7dt pc6dt pc5dt pc4dt pc3dt pc2dt pc1dt pc0dt i/o port ti7 ti6 ti5 ti4 ti3 ti2 ti1 ti0 sdir ? ? ? ? ? ? ? ? did31 did30 did29 did28 did27 did26 did25 did24 sdid/ sdidh did23 did22 did21 did20 did19 did18 did17 did16 did15 did14 did13 did12 did11 did10 did9 did8 sdidl did7 did6 did5 did4 did3 did2 did1 did0 h-udi notes: 1. bit names in the first row of cs0w cr show the names for the normal/byte-selection sram interface, in the second row for t he burst rom (asynchronous) interface, and in the third row for the burst ro m (synchronous) interface. 2. bit names in the first rows of cs2wcr and cs3wcr show the names for the normal/byte-selection sram interface and in the second rows for the sdram interface. 3. bit names in the first row of cs4wcr show the names for the normal/byte-selection sram interface and in the second row for the burst rom (asynchronous) interface. 4. bit names of cs5awcr and cs6awcr sh ow the names for the normal/byte-selection sram interface. 5. bit names in the first rows of cs5bwcr and cs6bwcr show the names for the normal/byte-selection sram interface and in the second rows for the pcmcia interface.
section 24 list of registers rev. 2.00 dec. 07, 2005 page 846 of 950 rej09b0079-0200 24.3 register states in each operating mode register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module intevt initialized initialized retained ? retained intevt2 initialized initialized retained ? retained tra initialized initialized retained ? retained expevt initialized initialized retained ? retained tea initialized initialized retained ? retained exception handling mmucr initialized initialized retained retained retained pteh initialized initialized retained retained retained ptel initialized initialized retained retained retained ttb initialized initialized retained retained retained mmu ccr1 initialized initialized retained retained retained ccr2 initialized initialized retained retained retained ccr3 initialized initialized retained retained retained cache ipra initialized initialized retained ? retained iprb initialized initialized retained ? retained iprc initialized initialized retained ? retained iprd initialized initialized retained ? retained ipre initialized initialized retained ? retained iprf initialized initialized retained ? retained iprg initialized initialized retained ? retained iprh initialized initialized retained ? retained ipri initialized initialized retained ? retained icr0 initialized initialized retained ? retained icr1 initialized initialized retained ? retained irr0 initialized initialized retained ? retained irr1 initialized initialized retained ? retained irr2 initialized initialized retained ? retained irr3 initialized initialized retained ? retained irr4 initialized initialized retained ? retained intc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 847 of 950 rej09b0079-0200 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module irr5 initialized initialized retained * 2 ? retained irr7 initialized initialized retained ? retained irr8 initialized initialized retained ? retained intc bara initialized initialized retained retained retained bamra initialized initialized retained retained retained bbra initialized initialized retained retained retained barb initialized initialized retained retained retained bamrb initialized initialized retained retained retained bbrb initialized initialized retained retained retained bdrb initialized initialized retained retained retained bdmrb initialized initialized retained retained retained brcr initialized initialized retained retained retained betr initialized initialized retained retained retained brsr initialized initialized retained retained retained brdr initialized initialized retained retained retained basra initialized initialized retained retained retained basrb initialized initialized retained retained retained ubc stbcr initialized retained retained ? retained stbcr2 initialized retained retained ? retained stbcr3 initialized retained retained ? retained power-down mode frqcr initialized retained retained ? retained wtcnt initialized initialized retained ? retained wtcsr initialized initialized retained ? retained cpg cmncr initialized retained retained ? retained cs0bcr initialized retained retained ? retained cs2bcr initialized retained retained ? retained cs3bcr initialized retained retained ? retained cs4bcr initialized retained retained ? retained cs5abcr initialized retained retained ? retained cs5bbcr initialized retained retained ? retained cs6abcr initialized retained retained ? retained bsc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 848 of 950 rej09b0079-0200 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module cs6bbcr initialized retained retained ? retained cs0wcr initialized retained retained ? retained cs2wcr initialized retained retained ? retained cs3wcr initialized retained retained ? retained cs4wcr initialized retained retained ? retained cs5awcr initialized retained retained ? retained cs5bwcr initialized retained retained ? retained cs6awcr initialized retained retained ? retained cs6bwcr initialized retained retained ? retained sdcr initialized retained retained ? retained rtcsr initialized retained retained ? retained rtcnt initialized retained retained ? retained rtcor initialized retained retained ? retained bsc sar_n (n = 0 to 5) initialized initialized retained retained retained dar_n (n = 0 to 5) initialized initialized retained retained retained dmatcr_n (n = 0 to 5) initialized initialized retained retained retained chcr_n (n = 0 to 5) initialized initialized retained retained retained dmaor initialized initialized retained retained retained dmars0 initialized initialized retained retained retained dmars1 initialized initialized retained retained retained dmars2 initialized initialized retained retained retained dmac tstr initialized initialized initialized * 3 initialized retained tcor_n (n = 0 to 2) initialized initialized retained retained retained tcnt_n (n = 0 to 2) initialized initialized retained retained retained tcr_n (n = 0 to 2) initialized initialized retained retained retained tmu
section 24 list of registers rev. 2.00 dec. 07, 2005 page 849 of 950 rej09b0079-0200 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module r64cnt retained retained retained retained retained rseccnt retained retained retained retained retained rmincnt retained retained retained retained retained rhrcnt retained retained retained retained retained rwkcnt retained retained retained retained retained rdaycnt retained retained retained retained retained rmoncnt retained retained retained retained retained ryrcnt retained retained retained retained retained rsecar retained * 4 retained retained retained retained rminar retained * 4 retained retained retained retained rhrar retained * 4 retained retained retained retained rwkar retained * 4 retained retained retained retained rdayar retained * 4 retained retained retained retained rmonar retained * 4 retained retained retained retained ryrar retained retained retained retained retained rcr1 initialized initialized retained retained retained rcr2 initialized initialized * 5 retained retained retained rcr3 initialized retained retained retained retained rtc scsmr_n (n = 0, 1) initialized initialized retained retained retained scbrr_n (n = 0, 1) initialized initialized retained retained retained scscr_n (n = 0, 1) initialized initialized retained retained retained scftdr_n (n = 0, 1) initialized initialized retained retained retained scfsr_n (n = 0, 1) initialized initialized retained retained retained scfrdr_n (n = 0, 1) initialized initialized retained retained retained scfcr_n (n = 0, 1) initialized initialized retained retained retained scif
section 24 list of registers rev. 2.00 dec. 07, 2005 page 850 of 950 rej09b0079-0200 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module scfdr_n (n = 0, 1) initialized initialized retained retained retained sclsr_n (n = 0, 1) initialized initialized retained retained retained scif simdr_n (n = 0, 1) initialized initialized retained retained retained siscr_n (n = 0, 1) initialized initialized retained retained retained sitdar_n (n = 0, 1) initialized initialized retained retained retained sirdar_n (n = 0, 1) initialized initialized retained retained retained sicdar_n (n = 0, 1) initialized initialized retained retained retained sictr_n (n = 0, 1) initialized initialized retained retained retained sifctr_n (n = 0, 1) initialized initialized retained retained retained sistr_n (n = 0, 1) initialized initialized retained retained retained siier_n (n = 0, 1) initialized initialized retained retained retained sitdr_n (n = 0, 1) initialized initialized retained retained retained sirdr_n (n = 0, 1) initialized initialized retained retained retained sitcr_n (n = 0, 1) initialized initialized retained retained retained sircr_n (n = 0, 1) initialized initialized retained retained retained siof ecmrn (n = 0, 1) initialized initialized retained ? retained ecsrn (n = 0, 1) initialized initialized retained ? retained ecsiprn (n = 0, 1) initialized initialized retained ? retained etherc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 851 of 950 rej09b0079-0200 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module pirn (n = 0, 1) initialized initialized retained ? retained mahrn (n = 0, 1) initialized initialized retained ? retained malrn (n = 0, 1) initialized initialized retained ? retained rflrn (n = 0, 1) initialized initialized retained ? retained psrn (n = 0, 1) initialized initialized retained ? retained trocrn (n = 0, 1) initialized initialized retained ? retained cdcrn (n = 0, 1) initialized initialized retained ? retained lccrn (n = 0, 1) initialized initialized retained ? retained cndcrn (n = 0, 1) initialized initialized retained ? retained cefcrn (n = 0, 1) initialized initialized retained ? retained frecrn (n = 0, 1) initialized initialized retained ? retained tsfrcrn (n = 0, 1) initialized initialized retained ? retained tlfrcrn (n = 0, 1) initialized initialized retained ? retained rfcrn (n = 0, 1) initialized initialized retained ? retained mafcrn (n = 0, 1) initialized initialized retained ? retained ipgrn (n = 0, 1) initialized initialized retained ? retained arstr initialized initialized retained ? retained tsu_ctrst initialized initialized retained ? retained tsu_fwen0 initialized initialized retained ? retained tsu_fwen1 initialized initialized retained ? retained etherc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 852 of 950 rej09b0079-0200 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module tsu_fcm initialized initialized retained ? retained tsu_bsysl0 initialized initialized retained ? retained tsu_bsysl1 initialized initialized retained ? retained tsu_prisl0 initialized initialized retained ? retained tsu_prisl1 initialized initialized retained ? retained tsu_fwsl0 initialized initialized retained ? retained tsu_fwsl1 initialized initialized retained ? retained tsu_fwslc initialized initialized retained ? retained tsu_qtagm0 initialized initialized retained ? retained tsu_qtagm1 initialized initialized retained ? retained tsu_adqt0 initialized initialized retained ? retained tsu_adqt1 initialized initialized retained ? retained tsu_fwsr initialized initialized retained ? retained tsu_fwinmk initialized initialized retained ? retained tsu_adsbsy initialized initialized retained ? retained tsu_ten initialized initialized retained ? retained tsu_post1 initialized initialized retained ? retained tsu_post2 initialized initialized retained ? retained tsu_post3 initialized initialized retained ? retained tsu_post4 initialized initialized retained ? retained txnlcr0 initialized initialized retained ? retained txalcr0 initialized initialized retained ? retained rxnlcr0 initialized initialized retained ? retained rxalcr0 initialized initialized retained ? retained fwnlcr0 initialized initialized retained ? retained fwalcr0 initialized initialized retained ? retained txnlcr1 initialized initialized retained ? retained txalcr1 initialized initialized retained ? retained rxnlcr1 initialized initialized retained ? retained rxalcr1 initialized initialized retained ? retained fwnlcr1 initialized initialized retained ? retained etherc
section 24 list of registers rev. 2.00 dec. 07, 2005 page 853 of 950 rej09b0079-0200 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module fwalcr1 initialized initialized retained ? retained tsu_adrhn (n = 0 to 31) initialized initialized retained ? retained tsu_adrln (n = 0 to 31) initialized initialized retained ? retained etherc edmrn (n = 0, 1) initialized initialized retained ? retained edtrrn (n = 0, 1) initialized initialized retained ? retained edrrrn (n = 0, 1) initialized initialized retained ? retained tdlarn (n = 0, 1) initialized initialized retained ? retained rdlarn (n = 0, 1) initialized initialized retained ? retained eesrn (n = 0, 1) initialized initialized retained ? retained eesiprn (n = 0, 1) initialized initialized retained ? retained trscern (n = 0, 1) initialized initialized retained ? retained rmfcrn (n = 0, 1) initialized initialized retained ? retained tftrn (n = 0, 1) initialized initialized retained ? retained fdrn (n = 0, 1) initialized initialized retained ? retained rmcrn (n = 0, 1) initialized initialized retained ? retained edocrn (n = 0, 1) initialized initialized retained ? retained rbwarn (n = 0, 1) initialized initialized retained ? retained rdfarn (n = 0, 1) initialized initialized retained ? retained e-dmac
section 24 list of registers rev. 2.00 dec. 07, 2005 page 854 of 950 rej09b0079-0200 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module tbrarn (n = 0, 1) initialized initialized retained ? retained tdfarn (n = 0, 1) initialized initialized retained ? retained fcftrn (n = 0, 1) initialized initialized retained ? retained trimdn (n = 0, 1) initialized initialized retained ? retained e-dmac pacr initialized retained retained ? retained pbcr initialized retained retained ? retained pccr initialized retained retained ? retained petcr initialized retained retained ? retained pfc padr initialized retained retained ? retained pbdr initialized retained retained ? retained pcdr initialized retained retained ? retained i/o port sdir retained retained retained retained retained sdid/sdidh retained retained retained retained retained sdidl retained retained retained retained retained h-udi notes: 1. for the initial values of each register, see the sections for the corresponding modules. if the initial value is undefined, it is shown as initialized since the data is not retained. 2. some bits are initialized in standby mode. see section 8, interrupt controller (intc), for details. 3. if the multiplication rate of pll1 is modified, this register is initialized. 4. some bits are initialized by a power-on reset. see section 15, r ealtime clock (rtc), for details. 5. some bits are initialized by a manual re set. see section 15, realtime clock (rtc), for details.
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 855 of 950 rej09b0079-0200 section 25 electrical characteristics 25.1 absolute maximum ratings table 25.1 shows the absolute maximum ratings. table 25.1 absolute maximum ratings item symbol rating unit power supply voltage (i/o) v cc q v cc q-rtc ?0.3 to 4.6 v power supply voltage (internal) v cc v cc -pll1 v cc -pll2 ?0.3 to 2.1 v input voltage v in ?0.3 to v cc q + 0.3 v operating temperature t opr ?20 to 75 c storage temperature t stg ?55 to 125 c caution: ? operating the chip in excess of the absolute maximum rating may result in permanent damage. ? order of turning on 1.5 v power (vcc, vcc-p ll1, vcc-pll2) and 3.3 v power (vccq, vccq- rtc): 1. the 3.3 v power and the 1.5 v power should be turned on simultaneously or the 3.3 v power should be tuned on first. when the 3.3 v is turned on first, turn on the 1.5 v power within 1 ms. it is recommended that this interval will be as short as possible. 2. until voltage is applied to all power supplies and a low level is input at the resetp pin, internal circuits remain unsettled, and so pin states are also undefined. the system design must ensure that these undefined states do not cause erroneou s system operation. 3. when the power is turned on, make sure that the voltage of the 1.5 v power is lower than that of the 3.3 v power.
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 856 of 950 rej09b0079-0200 ? power-off order 1. in the reverse order of powering-on, first turn off the 1.5 v power, then turn off the 3.3 v power within 1 ms. it is recommended that this interval will be as short as possible. 2. pin states are undefined while only the 1.5 v power is off. the system design must ensure that these undefined states do not cause erroneous system operation. 3. when the power is turned off, make sure that the voltage of the 1.5 v power is lower than that of the 3.3 v power. waveforms and recommended times at power on/off are shown in figure 25.1. tpwu vccq: 3.3 v power vccq (min) voltage vccq (min) attain time vcc (min) attain time vcc: 1.5 v power vcc (min) voltage vcc/2 level voltage normal operation term states undefined term operation stopped clock oscillation started oscillation settling time (10 ms) cancel the power-on reset and go to normal operation tunc gnd tpwd figure 25.1 power on/off sequence recommended power on/off times item symbol max. permitted value unit vccq to vcc power-on time interval tpwu 1 ms vccq to vcc power-off time interval tpwd 1 ms state undefined term tunc 10 ms note: the recommended times shown above do not require strict settings. the state undefined term indicates that pins are at the power rising stag e. the pin state is stabilized at vccq (min.) attain ti me. however, a power-on reset ( resetp ) is accepted successfully only after vccq (min.) attain time and clock oscillation settling time. set the state undefined term less than 10 ms.
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 857 of 950 rej09b0079-0200 25.2 dc characteristics tables 25.2 and 25.3 list dc characteristics. table 25.2 dc characteristics (1) (condition: ta = ?20 to 75c) item symbol min. typ. max. unit measurement conditions v cc q, v cc q-rtc 3.0 3.3 3.6 v power supply voltage v cc , v cc -pll1 v cc -pll2 1.4 1.5 1.6 v i cc ? 250 330 ma v cc = 1.5 v i = 200 mhz normal operation i cc q ? 40 70 ma b = 66.67 mhz i cc ? 110 160 ma in sleep mode * i cc q ? 4 7 v cc q = 3.3 v b = 66.67 mhz i cc ? 1500 2600 a i cc q ? 75 230 t a = 25c (rtc on) v cc q = 3.3 v v cc = 1.5 v i cc ? 1500 2600 a current consumption in standby mode i cc q ? 75 230 t a = 25c (rtc off) v cc q = 3.3 v v cc = 1.5 v input leak current all input pins | i in | ? ? 1.0 a v in = 0.5 to v cc q ? 0.5 v three-state leak current i/o, all output pins (off condition) | i sti | ? ? 1.0 a vin = 0.5 to v cc q ? 0.5 v pull-up resistance port pin r pull 20 60 180 k ? pin capacitance all pins c ? ? 20 pf note: * no external bus cycles except refresh cycles.
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 858 of 950 rej09b0079-0200 table 25.2 dc characteristics (2) (condition: ta = ?20 to 75c) item symbol min. typ. max. unit measurement conditions input high voltage resetp , resetm , nmi irq5 to irq0, md5 to md0, asemd0 , trst , extal, ckio v ih v cc q 0.9 ? v cc q + 0.3 extal2 ? ? ? when this pin is not connected to the crystal resonator, this pin should be connected to the v cc q pin (pulled up). other input pins 2.0 ? v cc q + 0.3 v input low voltage resetp , resetm , nmi irq5 to irq0, md5 to md0, asemd0 , trst , extal, ckio v il ?0.3 ? v cc q 0.1 extal2 ? ? ? when this pin is not connected to the crystal resonator, this pin should be connected to the v cc q pin (pulled up). other input pins ?0.3 ? v cc q 0.2 v output high voltage all output pins v oh 2.4 ? ? v v cc q = 3.0 v, i oh = ?2 ma output low voltage all output pins v ol ? ? 0.55 v v cc q = 3.0 v, i ol = 2 ma notes: 1. even when the rtc is not us ed, power must be supplied between v cc q-rtc and v ss q- rtc.
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 859 of 950 rej09b0079-0200 2. current consumption values are for v ih min. = v cc q ? 0.5 v and v il max. = 0.5 v with all output pins unloaded. table 25.3 permitted output current values (conditions: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c) item symbol min. typ. max. unit output low-level permissible current (per pin) i ol ? ? 2.0 ma output low-level permissible current (total) i ol ? ? 120 ma output high-level permissible current (per pin) ?i oh ? ? 2.0 ma output high-level permissible current (total) (?i oh ) ? ? 40 ma caution: to ensure lsi reliability, do not exceed the value for output current given in table 25.3. 25.3 ac characteristics in general, inputting for this lsi should be clock synchronous. keep the setup and hold times for each input signal unless otherwise specified. table 25.4 maximum operating frequencies (conditions: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c) item symbol min. ty p. max. unit remarks cpu, cache (i ) f 33.34 ? 200 mhz external bus (b ) 33.34 ? 66.67 operating frequency peripheral module (p ) 8.34 ? 33.34
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 860 of 950 rej09b0079-0200 25.3.1 clock timing table 25.5 clock timing (condition: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c, maximum external bus operating frequency: 66.67 mhz) item symbol min. max. unit figure extal clock input frequency f ex 10 66.67 mhz 25.2 extal clock input cycle time t excyc 15 100 ns extal clock input low pulse width t exl 1.5 ? extal clock input high pulse width t exh 1.5 ? extal clock input rise time t exr ? 6 extal clock input fall time t exf ? 6 ckio clock input frequency f cki 33.34 66.67 mhz 25.3 ckio clock input cycle time t ckicyc 15 30 ns ckio clock input low pulse width t ckil 3 ? ckio clock input high pulse width t ckih 3 ? ckio clock input rise time t ckir ? 4 ckio clock input fall time t ckif ? 4 ckio clock output frequency f op 33.34 66.67 mhz 25.4 ckio clock output cycle time t cyc 15 30 ns ckio clock output low pulse width t ckol 3 ? ckio clock output high pulse width t ckoh 3 ? ckio clock output rise time t ckor ? 4 ckio clock output fall time t ckof ? 4 ckio2 clock output delay time t ck2d ? 2.5 ckio2 clock output rise time t ck2or ? 7 ckio2 clock output fall time t ck2of ? 7 power-on oscillation settling time t osc1 10 ? ms 25.5 resetp setup time t resps 20 ? ns 25.5 resetp assert time t respw 20 ? t cyc 25.5, 25.6 resetm assert time t resmw 20 ? t cyc 25.6 standby return oscillation settling time 1 t osc2 10 ? ms 25.6 standby return oscillation settling time 2 t osc3 10 ? ms 25.7 standby return oscillation settling time 3 t osc4 11 ? ms 25.8
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 861 of 950 rej09b0079-0200 item symbol min. max. unit figure pll synchronization settling time 1 t pll1 100 ? s 25.9, 25.10 pll synchronization settling time 2 t pll2 100 ? s 25.11 interrupt determination time (rtc used and standby mode) t irlstb 100 ? s 25.10 t exh t exf t exr t exl t excyc v ih v ih v ih 1/2 v cc q 1/2 v cc q v il v il extal * (input) note: * the clock input from the extal pin. figure 25.2 extal clock input timing t ckih t ckif t ckir t ckil t cki cyc v ih 1/2 v cc q 1/2 v cc q v ih v il v ih v il ckio (input) figure 25.3 ckio clock input timing
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 862 of 950 rej09b0079-0200 t cyc t ckol t ckoh v oh 1/2v cc q ckio (output) 1/2v cc q t ckor t ckof t ck2d t ck2d v oh v ol v ol v oh v oh ckio2 (output) t ck2or t ck2of figure 25.4 ckio clock output timing v cc min t respw t resps t osc1 v cc resetp ckio, internal clock stable oscillation note: oscillation settling time when on-chip oscillator is used figure 25.5 power-on oscillation settling time ckio, internal clock stable oscillation standby t osc2 t respw t resmw resetp r esetm note: oscillation settling time when on-chip oscillator is used figure 25.6 oscillation settling time at standby return (return by reset)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 863 of 950 rej09b0079-0200 ckio, internal clock stable oscillation standby t osc3 nmi note: oscillation settling time when on-chip oscillator is used figure 25.7 oscillation settling time at standby return (return by nmi) ckio, internal clock stable oscillation standby t osc4 irl3 to irl0 irq5 to irq0 note: oscillation settling time when on-chip oscillator is used in oscillation stop mode figure 25.8 oscillation settling time at standby return (return by irq5 to irq0 and irl3 to irl0 ) extal input, ckio input stable input clock reset or nmi interrupt request stable input clock normal normal standby pll output, ckio output internal clock status 0 status 1 pll synchronization note: pll oscillation settling time when clock is input from extal pin t pll1 pll synchronization figure 25.9 pll synchronization settling time by reset or nmi
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 864 of 950 rej09b0079-0200 extal input, ckio input stable input clock irl3 to irl0 /irq5 to irq0 interrupt request stable input clock normal normal pll output, ckio output internal clock status 0 status 1 note: pll oscillation settling time when clock is input from extal pin or ckio pin in oscillation continuous mode. t pll1 pll synchronization standby pll synchronization t irlstb figure 25.10 pll synchronization settling time by irq/irl interrupts extal input * 1 (ckio input) ckio output * 2 (pll output) internal clock multiplication ratio modified t pll2 notes: 1. ckio input in clock mode 7 2. pll output except in clock mode 7 figure 25.11 pll synchronization settlin g time when frequency multiplication ratio modified
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 865 of 950 rej09b0079-0200 25.3.2 control signal timing table 25.6 control signal timing (conditions: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c) 66.67 mhz * 2 item symbol min. max. unit figure resetp pulse width t respw 20 * 3 ? t cyc 25.12 resetp setup time * 1 t resps 20 ? ns resetm pulse width t resmw 20 * 4 ? t cyc resetm setup time t resms 10 ? ns breq setup time t breqs 1/2 t cyc +10 ? 25.14 breq hold time t breqh 1/2 t cyc +3 ? nmi setup time * 1 t nmis 10 ? 25.13 nmi hold time t nmih 3 ? irq5 to irq0 setup time * 1 t irqs 10 ? irq5 to irq0 hold time t irqh 3 ? back delay time t backd ? 1/2 t cyc +13 25.14 status1, status0 delay time t std ? 18 25.15 irqout delay time t irqotd ? 1/2 t cyc +12 25.16 bus tri-state delay time 1 t boff1 0 30 25.14, bus tri-state delay time 2 t boff2 0 30 25.15 bus buffer-on time 1 t bon1 0 30 bus buffer-on time 2 t bon2 0 30 notes: t cyc is the external bus clock cycle (b clock cycle). 1. resetp , nmi, and irq5 to irq0 are asynch ronous. changes are detected at the clock rise when the setup shown is kept. when the setup cannot be kept, detection can be delayed until the next clock rises. 2. the upper limit of the exte rnal bus clock is 66.67 mhz. 3. in standby mode, t respw = t osc2 (10 ms). when the crystal oscillation continues or the clock multiplication ratio is changed in standby mode, t respw = t pll1 (100 s). 4. in standby mode, t resmw = t osc2 (10 ms). when the crystal oscillation continues or the clock multiplication ratio is changed in standby mode, resetm must be kept low until status (0-1) changes to reset (hh).
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 866 of 950 rej09b0079-0200 ckio t resps t resms t resps t resms resetp resetm t respw t resmw figure 25.12 reset input timing ckio nmi t nmih t nmis v ih v il irq5 to irq0 t irqh t irqs v ih v il figure 25.13 interrupt signal input timing ckio breq back a25 to a0, d31 to d0 rd , rd/ wr , ras , cas , csn , wen , bs , cke breqh t breqs t backd t backd t breqh t breqs t bon1 t boff1 t boff2 t bon2 t figure 25.14 bus release timing
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 867 of 950 rej09b0079-0200 ckio t std t boff2 t boff1 t std t bon2 t bon1 status 0 status 1 a25 to a0, d31 to d0 rd , rd/ wr , ras , cas , csn , wen , bs , cke normal mode normal mode standby mode figure 25.15 pin drive timing at standby ckio t irqotd irqout figure 25.16 irqout output delay time
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 868 of 950 rej09b0079-0200 25.3.3 ac bus timing table 25.7 bus timing (1) (conditions: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c, clock mode 0/1/2/4/5/6/7) 66.67 mhz item symbol min. max. unit figure address delay time 1 t ad1 1 12 ns 25.17 to 25.42 address delay time 2 t ad2 ? 1/2 t cyc +12 25.21 address setup time t as 0 ? 25.17 to 25.20 address hold time t ah 0 ? bs delay time t bsd ? 10 25.17 to 25.35, 25.39 to 25.42 cs delay time 1 t csd1 1 10 25.17 to 25.42 read/write delay time 1 t rwd1 1 10 read strobe delay time t rsd ? 1/2 t cyc +10 25.17 to 25.21, 25.39 to 25.40 read data setup time 1 t rds1 1/2 t cyc +6 ? 25.17 to 25.20, 25.39 to 25.42 read data setup time 2 t rds2 6 ? 25.22 to 25.25, 25.30 to 25.32 read data setup time 3 t rds3 1/2 t cyc +6 ? 25.21 read data hold time 1 t rdh1 0 ? 25.17 to 25.20, 25.39 to 25.42 read data hold time 2 t rdh2 2 ? 25.22 to 25.25, 25.30 to 25.32 read data hold time 3 t rdh3 0 ? 25.21 write enable delay time t wed ? 1/2 t cyc +10 25.17 to 25.21, 25.39 to 25.40 write data delay time 1 t wdd1 ? 12 25.17 to 25.20, 25.39 to 25.42 write data delay time 2 t wdd2 ? 12 25.26 to 25.29, 25.33 to 25.35 write data hold time 1 t wdh1 1 ? 25.17 to 25.20 write data hold time 2 t wdh2 1 ? 25.26 to 25.29, 25.33 to 25.35
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 869 of 950 rej09b0079-0200 66.67 mhz item symbol min. max. unit figure write data hold time 4 t wdh4 0 ? 25.17 to 25.20 write data hold time 5 t wdh5 1 ? 25.39 to 25.42 wait setup time t wts 1/2 t cyc +6 ? ns 25.18 to 25.21, 25.40, wait hold time t wth 1/2 t cyc +2 ? 25.42 ras delay time 1 t rasd1 1 10 25.22 to 25.38 cas delay time 1 t casd1 1 10 dqm delay time 1 t dqmd1 1 10 25.22 to 25.35 cke delay time 1 t cked1 1 10 25.37 dack delay time t dacd ? 10 25.17 to 25.35 iciord delay time t icrsd ? 1/2 t cyc +12 25.41, 25.42 iciowr delay time t icwsd ? 1/2 t cyc +12 iois16 setup time t io16s 1/2 t cyc +12 ? 25.42 iois16 hold time t io16h 1/2 t cyc +4 ? refout delay time t refod ? 1/2 t cyc +12 25.43
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 870 of 950 rej09b0079-0200 25.3.4 basic timing t1 t ad1 t ad1 t as t csd1 t csd1 t2 t rwd1 t rwd1 t rsd t rsd t ah t ah t rdh1 t rds1 t wed t wed t bsd t bsd t dacd t dacd t wdh1 t wdh4 t wdd1 ckio a25 to a0 csn rd/ wr rd d31 to d0 wen bs dackn * d31 to d0 read write note: * dackn is a waveform when active-low is specified. figure 25.17 basic bus cycle (no wait)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 871 of 950 rej09b0079-0200 t1 t ad1 t ad1 t as t csd1 t csd1 tw t2 t rwd1 t rwd1 t rsd t rsd t rdh1 t rds1 t wed t wed t ah t ah t bsd t bsd t wth t wts t dacd t dacd t wdh1 t wdh4 t wdd1 ckio a25 to a0 csn rd/ wr rd d31 to d0 wen bs wait dackn * d31 to d0 note: * dackn is a waveform when active-low is specified. read write figure 25.18 basic bus cycle (one software wait)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 872 of 950 rej09b0079-0200 t1 t ad1 t ad1 t as t csd1 t csd1 tw x t2 t rwd1 t rwd1 t rsd t rsd t ah t ah t rdh1 t rds1 t wed t wed t bsd t bsd t wth t wth t wts t wts t dacd t dacd t wdh1 t wdh4 t wdd1 ckio a25 to a0 csn rd/ wr rd d31 to d0 wen bs wait dackn * d31 to d0 read write note: * dackn is a waveform when active-low is specified. figure 25.19 basic bus cycle (one external wait)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 873 of 950 rej09b0079-0200 t ad1 t ad1 t1 t rwd1 t rsd t wed t wed t wed t rds1 t rds1 t as t rsd t rsd t ah t rsd t ah t wed t ah t ah t csd1 t wdd1 t wdh1 t wdh4 t wdh1 t wdh4 t wdd1 t bsd t bsd t dacd t dacd t dacd t dacd t bsd t bsd t rwd1 t rwd1 t rwd1 t csd1 t csd1 t csd1 t as t ad1 t ad1 tw t2 tnop t1 tw t2 tnop dackn * a25 to a0 d15 to d0 csn rd/ wr rd wait d15 to d0 we n bs ckio t wth t wts t wth t wts read write note: * dackn is a waveform when active-low is specified. t rdh1 t rdh1 figure 25.20 basic bus cycle (one software wait, external wait enabled (wm bit = 0), no idle cycle setting)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 874 of 950 rej09b0079-0200 25.3.5 burst rom timing t1 tw twx t2b twb t2b t ad1 t csd1 t ad2 t ad2 t rwd1 t rwd1 t csd1 t rsd t rsd t wed t wed t bsd t bsd t wth t wts t wth t wts t dacd t dacd t rds3 t rdh3 * 1 t rds3 t rdh3 * 1 ckio a25 to a0 csn rd/ wr rd wen bs wait dackn * 2 d31 to d0 notes: 1. t rdh3 is specified by earlier one of change of a25 to a0 or the rd rising edge. 2. dackn is a waveform when active-low is specified. figure 25.21 burst rom read cycle (one access wait, one external wait, one burst wait, two bursts)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 875 of 950 rej09b0079-0200 25.3.6 synchronous dram timing tc1 tr tcw td1 tde t ad1 t ad1 t csd1 t ad1 t rwd1 t rwd1 t csd1 t ad1 t ad1 t ad1 t rdh2 t rds2 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd1 t rasd1 ras row address read a command column address t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. t bsd t dacd figure 25.22 synchronous dram single read bus cycle (auto precharge, cas latency = 2, trcd = 1 cycle, trp = 1 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 876 of 950 rej09b0079-0200 tr w tr tc1 tcw td1 tde tap t ad1 t ad1 t csd1 t ad1 t rwd1 t rwd1 t csd1 t ad1 t ad1 t ad1 t rdh2 t rds2 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd1 t rasd1 ras row address read a command column address t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.23 synchronous dram single read bus cycle (auto precharge, cas latency = 2, trcd = 2 cycle, trp = 2 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 877 of 950 rej09b0079-0200 tc1 tc2 td1 td2 td3 td4 tr tc3 tc4 tde t ad1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t csd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd1 t rasd1 ras row address read a command read command column address (1 to 4) t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t rdh2 t rds2 t rdh2 t rds2 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.24 synchronous dram burst read bus cycle (single read 4), (auto precharge, cas latency = 2, trcd = 1 cycle, trp = 2 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 878 of 950 rej09b0079-0200 tc1 tc2 td1 td2 td3 td4 tr trw tc3 tc4 tde t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd1 t rasd1 ras row address read a command read command column address (1 to 4) t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t rdh2 t rds2 t rdh2 t rds2 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.25 synchronous dram burst read bus cycle (single read 4), (auto precharge, cas latency = 2, trcd = 2 cycle, trp = 1 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 879 of 950 rej09b0079-0200 tr w l tr tc1 t csd1 t csd1 t rwd1 t rwd1 t rwd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd1 t rasd1 ras row address write a command column address t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdd2 t wdh2 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. t rasd1 figure 25.26 synchronous d ram single write bus cycle (auto precharge, trwl = 2 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 880 of 950 rej09b0079-0200 tr w t c 1 tr w l tr tr w t csd1 t csd1 t casd1 t casd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd1 ras row address write a command column address cas t bsd t bsd (high) bs cke t dqmd1 t rwd1 t rwd1 t rasd1 t rasd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdh2 t wdd2 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.27 synchronous d ram single write bus cycle (auto precharge, trcd = 3 cycle, trwl = 2 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 881 of 950 rej09b0079-0200 tc2 tc3 tc4 trwl tr tc1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd1 t rasd1 ras row address write a command write command column address (1-4) t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdh2 t wdh2 t wdd2 t wdd2 t rasd1 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.28 synchronous dram bu rst write bus cycle (single write 4), (auto precharge, trcd = 1 cycle, trwl = 2 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 882 of 950 rej09b0079-0200 tc2 tc3 tc4 trwl tr tc1 tr w t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd1 t rasd1 ras row address write a command write command column address (1-4) t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdh2 t wdh2 t wdd2 t wdd2 t rasd1 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.29 synchronous dram bu rst write bus cycle (single write 4), (auto precharge, trcd = 2 cycle, trwl = 2 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 883 of 950 rej09b0079-0200 tc3 tc4 tde tr tc2 td1 td2 td3 td4 tc1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd1 t rasd1 ras row address read command column address (1-4) t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t rdh2 t rds2 t rdh2 t rds2 t ad1 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.30 synchronous dram burst read bus cycle (single read 4) (bank active mode, actv + read comman ds, cas latency = 2, trcd = 1 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 884 of 950 rej09b0079-0200 tc2 tc4 tde tc1 tc3 td1 td2 td3 td4 t csd1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd1 t rasd1 ras read command column address (1-4) t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t rdh2 t rds2 t rdh2 t rds2 t ad1 t dqmd1 t dacd t bsd t casd1 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.31 synchronous dram burst read bus cycle (single read 4) (bank active mode, read co mmand, same row address, cas latency = 2, trcd = 1 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 885 of 950 rej09b0079-0200 tc3 tc4 tde tc2 td1 td2 td3 td4 tc1 tr tpw tp t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd1 t rasd1 t rasd1 t rasd1 ras read command column address row address (1-4) t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t rdh2 t rds2 t rdh2 t rds2 t csd1 t rasd1 t casd1 t dqmd1 t bsd t dacd notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.32 synchronous dram burst read bus cycle (single read 4) (bank active mode, pre + actv + read commands, different row address, cas la tency = 2, trcd = 1 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 886 of 950 rej09b0079-0200 tc2 tc3 tc4 tr tc1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd1 t rwd1 t rwd1 t rasd1 ras row address write command column address (1-4) t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdh2 t wdh2 t wdd2 t wdd2 t rasd1 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.33 synchronous dram bu rst write bus cycle (single write 4) (bank active mode, actv + write command s, trcd = 1 cycle, trwl = 1 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 887 of 950 rej09b0079-0200 tc2 tc3 tc4 tnop tc1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 ras write command column address (1-4) t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdh2 t wdh2 t wdd2 t wdd2 t rasd1 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.34 synchronous dram bu rst write bus cycle (single write 4) (bank active mode, write command, same row address, trcd = 1 cycle, trwl = 1 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 888 of 950 rej09b0079-0200 tc2 tc3 tc4 tr tpw tp tc1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 t rwd1 t rasd1 t rasd1 t rasd1 t rasd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 ras write command row address (1-4) column address t casd1 t casd1 cas t bsd t bsd (high) bs cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdh2 t wdd2 t wdh2 t wdd2 t rasd1 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.35 synchronous dram bu rst write bus cycle (single write 4) (bank active mode, pre + actv + write commands, different row address, trcd = 1 cycle, trwl = 1 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 889 of 950 rej09b0079-0200 tr c tr c tr r tpw tp tr c t csd1 t csd1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 t rasd1 t rasd1 t rasd1 t rasd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 ras t casd1 t casd1 cas (high) (hi-z) bs cke dqmxx dackn * 2 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.36 synchronous dram au to-refresh timing (trp = 2 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 890 of 950 rej09b0079-0200 tr c tr c tr c tr c tr r tpw tp tr c t csd1 t csd1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 t rasd1 t rasd1 t rasd1 t rasd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 ras t casd1 t casd1 cas (hi-z) bs cke dqmxx dackn * 2 t cked1 t cked1 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.37 synchronous dram se lf-refresh timing (trp = 2 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 891 of 950 rej09b0079-0200 trc trc trc tmw tde tr r tr r tpw tp tr c t csd1 t csd1 t csd1 t csd1 t csd1 t csd1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 pall ref ref mrs t rwd1 t rwd1 t rwd1 t rwd1 t rwd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 ras t casd1 t casd1 t casd1 t casd1 t casd1 t casd1 cas (hi-z) bs cke dqmxx dackn * 2 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.38 synchronous dram mode register write timing (trp = 2 cycle)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 892 of 950 rej09b0079-0200 t rds1 ckio t pcm1 t pcm1w t pcm1w t pcm1w t pcm2 a25 to a0 cexx rd/ wr rd d15 to d0 we d15 to d0 bs t ad1 t csd1 t rwd1 t csd1 t ad1 t rwd1 t rsd t rsd t wed t wdd1 t wed t wdh1 t bsd t rdh1 t wdh5 t bsd read write figure 25.39 pcmcia memory card interface bus timing
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 893 of 950 rej09b0079-0200 t rds1 ckio a25 to a0 cexx rd/ wr rd d15 to d0 we d15 to d0 bs t ad1 t csd1 t rwd1 t csd1 t ad1 t rwd1 t rsd t icrsd t wed t wdd1 t wed t wdh1 t bsd t rdh1 t wdh5 t bsd read write wait t wth t wts t wts t wth tpcm1 tpcm1w tpcm2 tpcm2w tpcm0 tpcm0w tpcm1w tpcm1w tpcm1w figure 25.40 pcmcia memory card interface bus timing (ted[3:0] = b'0010, teh[3:0] = b'0001, one software wait, one hardware wait)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 894 of 950 rej09b0079-0200 t rds1 ckio t pci1 t pci1w t pci1w t pci1w t pci2 a25 to a0 cexx rd/ wr iciord d15 to d0 iciowe d15 to d0 bs t ad1 t csd1 t rwd1 t csd1 t ad1 t rwd1 t icrsd t icrsd t icwsd t wdd1 t icwsd t wdh1 t bsd t rdh1 t wdh5 t bsd read write figure 25.41 pcmcia i/o card interface bus timing
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 895 of 950 rej09b0079-0200 t rds1 ckio tpci1 tpci1w tpci2 tpci2w tpci0 tpci0w tpci1w tpci1w tpci1w a25 to a0 cexx rd/ wr iciord d15 to d0 iciowe d15 to d0 bs t ad1 t csd1 t rwd1 t csd1 t ad1 t rwd1 t icrsd t icrsd t icwsd t wdd1 t icwsd t wdh1 t bsd t rdh1 t wdh5 t bsd t io16h t io16s read write wait iois16 t wth t wts t wts t wth figure 25.42 pcmcia i/o card interface bus timing (ted[3:0] = b'0010, teh[3:0] = b'0001, one software wait, one hardware wait) ckio t refod refout figure 25.43 refout delay time
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 896 of 950 rej09b0079-0200 table 25.8 bus timing (2) (conditions: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c, clock mode 0/1/2/4/5/6/7) item symbol min. max. unit figure address delay time 3 t ad3 1/2 t cyc 1/2 t cyc +12 ns 25.44 to 25.47 cs delay time 2 t csd2 1/2 t cyc 1/2 t cyc +10 25.44 to 25.47 read/write delay time 2 t rwd2 1/2 t cyc 1/2 t cyc +10 25.44 to 25.47 read data setup time 4 t rds4 1/2 t cyc +6 ? 25.44 read data hold time 4 t rdh4 0 ? 25.44 write data delay time 3 t wdd3 ? 1/2 t cyc +12 25.44 write data hold time 3 t wdh3 1/2 t cyc ? 25.44 ras delay time 2 t rasd2 1/2 t cyc 1/2 t cyc +10 25.44 to 25.47 cas delay time 2 t casd2 1/2 t cyc 1/2 t cyc +10 25.44 to 25.47 dqm delay time 2 t dqmd2 1/2 t cyc 1/2 t cyc +10 25.44 cke delay time 2 t cked2 1/2 t cyc 1/2 t cyc +10 25.46
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 897 of 950 rej09b0079-0200 tr td1 tde tap trwl tap tnop tc1 tr tc1 t ad3 t ad3 t ad3 t ad3 t ad3 t ad3 t ad3 t ad3 t ad3 t ad3 t ad3 t csd2 t csd2 t csd2 t csd2 t rwd2 t rwd2 t rwd2 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 t rasd2 t rasd2 t rasd2 t rasd2 ras t casd2 t casd2 t casd2 t casd2 cas t bsd t bsd t bsd t rds4 t rdh4 t bsd bs cke t dqmd2 t dqmd2 t dqmd2 t dqmd2 dqmxx t dacd t dacd t dacd t dacd dackn * 2 t wdh3 t wdd3 tw (high) notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.44 access timing in lo w-frequency mode (auto precharge)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 898 of 950 rej09b0079-0200 tr c tr c tr r tpw tp tr c t csd2 t csd2 t csd2 t csd2 t ad3 t ad3 t ad3 t ad3 t rwd2 t rwd2 t rwd2 t rasd2 t rasd2 t rasd2 t rasd2 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 ras t casd2 t casd2 cas (high) (hi-z) bs cke dqmxx dackn * 2 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.45 synchronous dram auto-refresh timing (trp = 2 cycle, low-frequency mode)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 899 of 950 rej09b0079-0200 tr c tr c tr c tr c tr r tpw tp tr c t csd2 t csd2 t csd2 t csd2 t ad3 t ad3 t ad3 t ad3 t rwd2 t rwd2 t rwd2 t rasd2 t rasd2 t rasd2 t rasd2 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 ras t casd2 t casd2 cas (hi-z) bs cke dqmxx dackn * 2 t cked2 t cked2 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.46 synchronous dram self-refresh timing (trp = 2 cycle, low-frequency mode)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 900 of 950 rej09b0079-0200 trc trc trc tmw tde tr r tr r tpw tp tr c t csd2 t csd2 t csd2 t csd2 t csd2 t csd2 t csd2 t csd2 t ad3 t ad3 t ad3 t ad3 t ad3 pall ref ref mrs t rwd2 t rwd2 t rwd2 t rwd2 t rwd2 t rasd2 t rasd2 t rasd2 t rasd2 t rasd2 t rasd2 t rasd2 t rasd2 ckio a25 to a0 csn rd/ wr a12/a11 * 1 d31 to d0 ras t casd2 t casd2 t casd2 t casd2 t casd2 t casd2 cas (hi-z) bs cke dqmxx dackn * 2 notes: 1. address pin to be connected to a10 of sdram. 2. dackn is a waveform when active-low is specified. figure 25.47 synchronous dram mode register write timing (trp = 2 cycle, low-frequency mode)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 901 of 950 rej09b0079-0200 25.3.7 dmac signal timing table 25.9 dmac signal timing (conditions: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c) module item symbol min. max. unit figure dmac dreqn setup time t drqs 10 ? ns 25.48 dreqn hold time t drqh 3 ? tendn, dackn delay time t dacd ? 10 25.49 t drqs t drqh ckio dreqn figure 25.48 dreqn input timing ckio tendn dackn t dacd t dacd figure 25.49 tendn, dackn output timing
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 902 of 950 rej09b0079-0200 25.3.8 rtc signal timing table 25.10 rtc signal timing (conditions: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c) module item symbol min. max. unit figure rtc oscillation settling time t rosc 3 ? s 25.50 v cc v ccmin t rosc rtc crystal oscillator stable oscillation figure 25.50 oscillation settling time wh en rtc crystal oscillator is turned on
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 903 of 950 rej09b0079-0200 25.3.9 scif module signal timing table 25.11 scif module signal timing (conditions: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c) module item symbol min. max. unit figure clock synchronization 12 ? scif0, scif1 input clock cycle asynchroniza- tion t scyc 4 ? t pcyc 25.51 25.52 input clock rise time t sckr ? 1.5 25.51 input clock fall time t sckf ? 1.5 input clock pulse width t sckw 0.4 0.6 t scyc transmission data delay time t txd ? 3 t pcyc * + 50 ns 25.52 receive data setup time (clock synchronization) t rxs 2 t pcyc * ? receive data hold time (clock synchronization) t rxh 2 t pcyc * ? rts delay time t rtsd ? 100 cts setup time (clock synchronization) t ctss 100 ? cts hold time (clock synchronization) t ctsh 100 ? note: * t pcyc indicates a peripheral clock (p ) cycle. t sckw t sckr t sckf t scyc scifnck figure 25.51 scifnck input clock timing
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 904 of 950 rej09b0079-0200 t scyc t txd t rxh t rxs t rtsd t ctsh t ctss scifnck rts cts txd (data trans- mission) rxd (data reception) figure 25.52 scif input/output timing in clock synchronous mode 25.3.10 siof module signal timing table 25.12 siof module signal timing (conditions: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c) item symbol min. max. unit figure siomclk clock input cycle time t mcyc 30 ? ns 25.53 siomclk input high-level width t mwh 0.4 t mcyc ? siomclk input low-level width t mwl 0.4 t mcyc ? sck_sio clock cycle time t sicyc 2 t pcyc ? 25.54 to 25.58 sck_sio output high-level width t swho 0.4 t sicyc ? 25.54 to 25.57 sck_sio output low-level width t swlo 0.4 t sicyc ? siofsync output delay time t fsd ? 20 sck_sio input high-level width t swhi 0.4 t sicyc ? 25.58 sck_sio input low-level width t swli 0.4 t sicyc ? siofsync input setup time t fss 20 ? siofsync input hold time t fsh 20 ? txd_sio output delay time t stdd ? 20 25.54 to 25.58 rxd_sio input setup time t srds 20 ? rxd_sio input hold time t srdh 20 ? note: t pcyc is the cycle time (ns) of the peripheral clock (p ).
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 905 of 950 rej09b0079-0200 t mwh siomclk t mwl t mcyc figure 25.53 siomclk input timing t srds t srdh sck_sio (output) siofsync (output) txd_sio rxd_sio t fsd t sicyc t swlo t swho t fsd t stdd t stdd figure 25.54 siof transmit/receive timi ng (master mode 1: fall sampling time)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 906 of 950 rej09b0079-0200 t srds t srdh sck_sio (output) siofsync (output) txd_sio rxd_sio t fsd t sicyc t swlo t swho t fsd t stdd t stdd figure 25.55 siof transmit/receive timing (master mode 1: ri se sampling time) t srds t srdh sck_sio (output) siofsync (output) txd_sio rxd_sio t fsd t sicyc t swlo t swho t fsd t stdd t stdd t stdd t stdd figure 25.56 siof transmit/receive timi ng (master mode 2: fall sampling time)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 907 of 950 rej09b0079-0200 t srds t srdh sck_sio (output) siofsync (output) txd_sio rxd_sio t fsd t sicyc t swlo t swho t fsd t stdd t stdd t stdd t stdd figure 25.57 siof transmit/receive timing (master mode 2: ri se sampling time) t srds t srdh sck_sio (input) siofsync (input) txd_sio rxd_sio t fss t sicyc t swli t swhi t fsh t stdd t stdd figure 25.58 siof transmit/receive timi ng (slave mode 1 and slave mode 2)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 908 of 950 rej09b0079-0200 25.3.11 ethernet controller timing table 25.13 ethernet controller timing (conditions: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c) item symbol min. typ. max. unit figure tx-clk cycle time t tcyc 40 ? ? ns 25.59 tx-en output delay time t tend 3 ? 20 etxd[3:0] output delay time t etdd 3 ? 20 crs setup time t crss 10 ? ? crs hold time t crsh 10 ? ? col setup time t cols 10 ? ? 25.60 col hold time t colh 10 ? ? rx-clk cycle time t rcyc 40 ? ? 25.61 rx-dv setup time t rdvs 10 ? ? rx-dv hold time t rdvh 3 ? ? erxd[3:0] setup time t erds 10 ? ? erxd[3:0] hold time t erdh 3 ? ? rx-er setup time t rers 10 ? ? 25.62 rx-er hold time t rerh 3 ? ? mdio setup time t mdios 10 ? ? 25.63 mdio hold time t mdioh 10 ? ? mdio output data hold time * t mdiodh 5 ? 18 25.64 wol output delay time t wold 1 ? 18 25.65 exout output delay time t exoutd 1 ? 28 25.66 camsen setup time t cams 10 ? ? 25.67 camsen hold time t camh 3 ? ? arbusy output delay time t arbyd ? ? 1/2 t cyc +12 25.68 note: * the user must ensure that the code satisfies this condition.
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 909 of 950 rej09b0079-0200 t tend sfd data crc t crsh tx-clk tx-en etxd[3:0] tx-er crs col t crss t etdd preamble figure 25.59 mii transmit timing (normal operation) preamble jam t colh t cols tx-clk tx-en tx-er crs col etxd[3:0] figure 25.60 mii transmit timing (case of conflict)
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 910 of 950 rej09b0079-0200 t rdvs sfd data crc rx-clk rx-dv erxd[3:0] rx-er t erds t erdh t rdvh preamble figure 25.61 mii receive timing (normal operation) sfd data xxxx rx-clk erxd[3:0] rx-er rx-dv t rers t rerh preamble figure 25.62 mii receive timing (case of error) mdc t mdios t mdioh mdio figure 25.63 mdio input timing mdc t mdiodh mdio figure 25.64 mdio output timing
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 911 of 950 rej09b0079-0200 rx-clk t wold wol figure 25.65 wol output timing ckio t exoutd exout figure 25.66 exout output timing sfd data rx-clk t cams preamble dest address source address t camh rx-dv erxd[3:0] camsen figure 25.67 camsen input timing ckio t arbyd arbusy figure 25.68 arbuby output timing
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 912 of 950 rej09b0079-0200 25.3.12 port input/output timing table 25.14 port input/output timing (conditions: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c) module item symbol min. max. unit figure output data delay time t portd ? 17 b:p clock ratio = 1:1 15 ? b:p clock ratio = 2:1 t cyc +15 ? input data setup time b:p clock ratio = 4:1 t ports 3 t cyc +15 ? port input data hold time t porth 8 ? ns 25.69 note: t cyc is the output cycle time of the ckio clock. t ports ckio t porth t portd port 7 to 0 (read) port 7 to 0 (write) figure 25.69 i/o port timing
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 913 of 950 rej09b0079-0200 25.3.13 h-udi related pin timing table 25.15 h-udi related pin timing (conditions: v cc q = v cc q-rtc = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, v ss q = v ss = v ss q-rtc = v ss -pll1 = v ss -pll2 = 0 v, t a = ?20 to 75c) item symbol min. max. unit figure tck cycle time t tckcyc 50 ? ns 25.70 tck high-pulse width t tckh 12 ? ns tck low-pulse width t tckl 12 ? ns tck rise/fall time t tckr /t tckf ? 4 ns trst setup time t trsts 12 ? ns 25.71 trst hold time t trsth 50 ? t cyc tdi setup time t tdis 10 ? ns 25.72 tdi hold time t tdih 10 ? ns tms setup time t tmss 10 ? ns tms hold time t tmsh 10 ? ns tdo delay time t tdod ? 15 ns asemd0 setup time t asemd0s 12 ? ns 25.73 asemd0 hold time t asemd0h 12 ? ns asebrkak delay time t asbrakd ? 15 ns 25.74 t tckh t tckf t tckr t tckl t tckcyc v ih v ih v ih 1/2 v cc q 1/2 v cc q v il v il figure 25.70 tck input timing
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 914 of 950 rej09b0079-0200 t trsts t trsth trst resetp figure 25.71 trst input timing (reset hold) t tmss t tmsh t tdod t tckcyc t tdih t tdis tck tdi tms tdo figure 25.72 h-udi data transfer timing t asemd0h t asemd0s resetp asemd0 figure 25.73 asemd0 input timing ckio t asbrakd asebrkak figure 25.74 asebrkak delay time
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 915 of 950 rej09b0079-0200 25.3.14 ac characteristics measurement conditions ? i/o signal reference level: v cc q/2 (v cc q = 3.0 to 3.6 v, v cc = 1.4 to 1.6 v) ? input pulse level: v ss q to 3.0 v (where resetp , resetm , asemd0 , nmi, irq5 to irq0, ckio, and md5 to md0 are within v ss q to v cc q) ? input rise and fall times: 1 ns i ol i oh c l v ref lsi output pin output load switching reference voltage notes: c l is the total value that includes the capacitance of measurement instruments, etc., and is set as follows for each pin. 30 pf: ckio, ras , cas , cs0 , cs2 to cs6b , back 50 pf: all other pins i ol = 2 ma , i oh = ?2 ma 1. 2. v figure 25.75 output load circuit
section 25 electric al characteristics rev. 2.00 dec. 07, 2005 page 916 of 950 rej09b0079-0200 25.4 delay time variation due to load capacitance a graph (reference data) of the variation in dela y time when a load capacitance greater than that stipulated (30 pf) is connected to this lsi?s pins is shown below. the graph shown in figure 25.76 should be taken into considerati on in the design process if the st ipulated capacitance is exceeded in connecting an external device. if the connected load capacitance exceeds the range shown in figure 25.76, the graph will not be a straight line. +4.0 ns +3.0 ns +2.0 ns +1.0 ns +0.0 ns +0 pf +25 pf +50 pf load capacitance [pf] delay time [ns] figure 25.76 load capacitance vs. delay time
appendix rev. 2.00 dec. 07, 2005 page 917 of 950 rej09b0079-0200 appendix a. pin states and states of unused pins reset power-down states pin name i/o power-on reset manual reset software standby sleep release of bus mastership handling of unused pins refout / irqout / arbusy o/o/o h h z h h open breq i i i z i i pull-up back o o o z o l open cs0 o h h hz * 4 o z open cs4 o h h hz * 4 o z open cs5a o h h hz * 4 o z open cs6a o h h hz * 4 o z open wait i i i z i z pull-up rd o h h hz * 4 o z open bs o h h hz * 4 o z open d0 io z z z io z pull-up d1 io z z z io z pull-up d2 io z z z io z pull-up d3 io z z z io z pull-up d4 io z z z io z pull-up d5 io z z z io z pull-up d6 io z z z io z pull-up d7 io z z z io z pull-up d8 io z z z io z pull-up d9 io z z z io z pull-up d10 io z z z io z pull-up d11 io z z z io z pull-up d12 io z z z io z pull-up d13 io z z z io z pull-up
appendix rev. 2.00 dec. 07, 2005 page 918 of 950 rej09b0079-0200 reset power-down states pin name i/o power- on reset manual reset software standby sleep release of bus mastership handling of unused pins d14 io z z z io z pull-up d15 io z z z io z pull-up we0 ( be0 )/dqmll o/o h h hz * 4 o z open we1 ( be1 )/dqmlu / we o/o/o h h hz * 4 o z open rd/ wr o h h hz * 4 o z open ckio io io * 1 z * 4 io * 1 z * 4 io * 1 io * 1 z * 4 io * 1 open cas o h h hz * 4 o hz * 4 open cke o h o hz * 4 o oz * 5 open ras o h h hz * 4 o hz * 4 open cs2 o h h hz * 4 o z open cs3 o h h hz * 4 o z open a0 o o o oz * 5 o z open a1 o o o oz * 5 o z open a2 o o o oz * 5 o z open a3 o o o oz * 5 o z open a4 o o o oz * 5 o z open a5 o o o oz * 5 o z open a6 o o o oz * 5 o z open a7 o o o oz * 5 o z open a8 o o o oz * 5 o z open a9 o o o oz * 5 o z open a10 o o o oz * 5 o z open a11 o o o oz * 5 o z open a12 o o o oz * 5 o z open a13 o o o oz * 5 o z open a14 o o o oz * 5 o z open a15 o o o oz * 5 o z open a16 o o o oz * 5 o z open a17 o o o oz * 5 o z open
appendix rev. 2.00 dec. 07, 2005 page 919 of 950 rej09b0079-0200 reset power-down states pin name i/o power-on reset manual reset software standby sleep release of bus mastership handling of unused pins we2 ( be2 )/ dqmul/ iciord o/o/o h h hz * 4 o z open we3 ( be3 )/ dqmuu/ iciowr o/o/o h h hz * 4 o z open d16 io z z z io z pull-up d17 io z z z io z pull-up d18 io z z z io z pull-up d19 io z z z io z pull-up d20 io z z z io z pull-up d21 io z z z io z pull-up d22 io z z z io z pull-up d23 io z z z io z pull-up d24 io z z z io z pull-up d25 io z z z io z pull-up d26 io z z z io z pull-up d27 io z z z io z pull-up d28 io z z z io z pull-up d29 io z z z io z pull-up d30 io z z z io z pull-up d31 io z z z io z pull-up a18 o o o oz * 5 o z open a19 o o o oz * 5 o z open a20 o o o oz * 5 o z open a21 o o o oz * 5 o z open a22 o o o oz * 5 o z open a23 o o o oz * 5 o z open a24 o o o oz * 5 o z open a25 o o o oz * 5 o z open ptb0 io v p * 2 z k * 3 z p * 2 p * 2 z open ptb1/ cts1 io/i v p * 2 i k * 3 z p * 2 i p * 2 i open
appendix rev. 2.00 dec. 07, 2005 page 920 of 950 rej09b0079-0200 reset power-down states pin name i/o power-on reset manual reset software standby sleep release of bus mastership handling of unused pins ptb2/ rts1 io/o v p * 2 o k * 3 z p * 2 o p * 2 o open ptb3/rxd1 io/i v p * 2 z k * 3 z p * 2 i p * 2 z open ptb4/txd1 io/o v p * 2 z k * 3 z p * 2 o p * 2 z open ptb5/scif1ck io/io v p * 2 z k * 3 z p p * 2 z open ptb6/ cts0 io/i v p * 2 i k * 3 z p * 2 i p * 2 i open ptb7/ rts0 io/o v p * 2 o k * 3 z p * 2 o p * 2 o open pta0/rxd0 io/i v p * 2 z k * 3 z p * 2 i p * 2 z open pta1/txd0 io/o v p * 2 z k * 3 z p * 2 o p * 2 z open pta2/scif0ck io/io v p * 2 z k * 3 z p p * 2 z open pta3/sck_sio0 io/io v p * 2 i k * 3 z p p * 2 i open pta4/siomclk0 io/i v p * 2 i k * 3 z p * 2 i p * 2 i open pta5/rxd_sio0 io/i v p * 2 i k * 3 z p * 2 i p * 2 i open pta6/txd_sio0 io/o v p * 2 o k * 3 z p * 2 o p * 2 o open pta7/siofsync0 io/io v p * 2 i k * 3 z p p * 2 i open crs1 i i i z i i pull-down col1 i i i z i i pull-down etxd13 o o o o o o open etxd12 o o o o o o open etxd11 o o o o o o open etxd10 o o o o o o open tx-en1 o o o o o o open tx-clk1 i i i z i i pull-down tx-er1 o o o o o o open rx-er1 i i i z i i pull-down rx-clk1 i i i z i i pull-down rx-dv1 i i i z i i pull-down erxd10 i i i z i i pull-down erxd11 i i i z i i pull-down erxd12 i i i z i i pull-down erxd13 i i i z i i pull-down
appendix rev. 2.00 dec. 07, 2005 page 921 of 950 rej09b0079-0200 reset power-down states pin name i/o power-on reset manual reset software standby sleep release of bus mastership handling of unused pins mdc1 o o o o o o open mdio1 io i i z i i pull-down wol1 o o o o o o open lnksta1 i i i z i i pull-down exout1/tend1 o/o o o o o o open camsen1/irq5 i/i i i zi * 6 i i pull-down crs0 i i i z i i pull-down col0 i i i z i i pull-down etxd03 o o o o o o open etxd02 o o o o o o open etxd01 o o o o o o open etxd00 o o o o o o open tx-en0 o o o o o o open tx-clk0 i i i z i i pull-down tx-er0 o o o o o o open rx-er0 i i i z i i pull-down rx-clk0 i i i z i i pull-down rx-dv0 i i i z i i pull-down erxd00 i i i z i i pull-down erxd01 i i i z i i pull-down erxd02 i i i z i i pull-down erxd03 i i i z i i pull-down mdc0 o o o o o o open mdio0 io i i z i i pull-down wol0 o o o o o o open lnksta0 i i i z i i pull-down exout0/tend0 o/o o o o o o open camsen0/irq4 i/i i i zi * 6 i i pull-down md4 i i i z i i must be used
appendix rev. 2.00 dec. 07, 2005 page 922 of 950 rej09b0079-0200 reset power-down states pin name i/o power-on reset manual reset software standby sleep release of bus mastership handling of unused pins md5 i i i i i i must be used xtal2 o o o o o o open extal2 i i i i i i pull-up asemd0 i m v z v v must be used tdi i m m v m m open tms i m m v m m open tdo o z z z o z open trst i m m v m m must be used tck i m m v m m open asebrkak o v o o o o open audsync o z o o o o open audck o o o o o o open audata3 o z o o o o open audata2 o z o o o o open audata1 o z o o o o open audata0 o z o o o o open resetm i i i i i i pull-up resetp i i i i i i must be used nmi i i i i i i pull-up irq0/ irl0 i z i i i i pull-up irq1/ irl1 i z i i i i pull-up irq2/ irl2 i z i i i i pull-up irq3/ irl3 i z i i i i pull-up status0 o h h h l l open status1 o h h l h l open ckio2 o o o oz * 5 o oz * 5 open dack0 o z o z o o open
appendix rev. 2.00 dec. 07, 2005 page 923 of 950 rej09b0079-0200 reset power-down states pin name i/o power-on reset manual reset software standby sleep release of bus mastership handling of unused pins dack1 o z o z o o open dreq0 i i z z i i pull-up dreq1 i i z z i i pull-up ptc0/sck_sio1 io/io v p * 2 i k * 3 z p p * 2 i open ptc1/siomclk1 io/i v p * 2 i k * 3 z p * 2 i p * 2 i open ptc2/rxd_sio1 io/i v p * 2 i k * 3 z p * 2 i p * 2 i open ptc3/txd_sio1 io/o v p * 2 o k * 3 z p * 2 o p * 2 o open ptc4/siofsync1 io/io v p * 2 i k * 3 z p p * 2 i open ptc5/ ce2a io/o v p * 2 o k * 3 h p * 2 o p * 2 z open ptc6/ ce2b io/o v p * 2 o k * 3 h p * 2 o p * 2 z open ptc7/ iois16 io/i v p * 2 i k * 3 z p * 2 i p * 2 i open cs5b/ ce1a o/o h h hz * 4 o z open cs6b/ ce1b o/o h h hz * 4 o z open md0 i i i i i i must be used md1 i i i i i i must be used md2 i i i i i i must be used md3 i i i z i i must be used xtal o o o o o o open extal i i i i i i pull-up vccq ? ? ? ? ? vccq vssq ? ? ? ? ? vssq vcc ? ? ? ? ? vcc vss ? ? ? ? ? vss vccq-rtc ? ? ? ? ? vccq vssq-rtc ? ? ? ? ? vssq vcc-pll1 ? ? ? ? ? vcc * 7
appendix rev. 2.00 dec. 07, 2005 page 924 of 950 rej09b0079-0200 reset power-down states pin name i/o power-on reset manual reset software standby sleep release of bus mastership handling of unused pins vss-pll1 ? ? ? ? ? vss * 7 vcc-pll2 ? ? ? ? ? vcc * 7 vss-pll2 ? ? ? ? ? vss * 7 [legend] i: input state i: input state (however, input is fixed by the internal logic) o: output state (undefined altho ugh the level is high or low) l: low-level output h: high-level output z: high impedance (input or output buffer off) v: input/output buffer off, pull-up on m: input buffer on, output buffer off, pull-up on k: output buffer on or input buffer off (pu ll-up on or off), depending on register settings p: input or output depending on register settings notes: 1. depends on clock mode. 2. the state is p when the port function is used. 3. the state is k when the port function is used. 4. the state is z or h depending on register settings. 5. the state is z or o depending on register settings. 6. the state is z when the ethernet controller function is used. 7. to avoid the power friction, vcc-pll1, vcc-pll2, vss-pll1, vss-pll2, and other vcc and vss should be wired in three independent patterns from the board power-supply source.
appendix rev. 2.00 dec. 07, 2005 page 925 of 950 rej09b0079-0200 b. package dimensions figure b.1 and figure b.2 show the sh7710 package dimensions.
appendix rev. 2.00 dec. 07, 2005 page 926 of 950 rej09b0079-0200 e * 3 f xm y p b * 1 * 2 129 128 192 193 65 64 1 256 d e d e z z h d h e 1 p 1 terminal cross section b c c b prqp0256la-b p-hqfp256-28x28-0.40 1.40 28 1.3 0.08 0 8 0.4 0.12 0.17 0.22 0.13 0.18 0.23 0.25 0.40 0.50 3.95 30.4 30.6 30.8 3.20 28 0.16 0.15 0.3 0.5 0.7 0.11 30.8 30.6 30.4 1.40 reference symbol dimension in millimeters min nom max previous code jeita package code renesas code fp-256g/fp-256gv 5.4g mass[typ.] 1 e d 1 1 p 1 e d 2 l z z y x c b b a h a e d a c e l h detail f 1 1 2 c l a l aa note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. figure b.1 package dimensions (hqfp2828-256 (fp-256g/gv))
appendix rev. 2.00 dec. 07, 2005 page 927 of 950 rej09b0079-0200 e a max nom min dimension in millimeters symbol reference a b x y 1 17.0 0.10 0.80 0.45 0.50 0.55 0.35 0.40 0.45 1.40 17.0 0.08 v w 0.9 0.9 y0.2 1 0.20 0.15 previous code jeita package code renesas code bp-256h/bp-256hv 0.6g mass[typ.] e d z z e d z z e d s s e d p-lfbga256-17x17-0.80 plbg0256ga-a 1 1 a a b s s y s wa s wb v s y 1 234567891011121314151617181920 b c d e f g h j k l m n p r t u v w y a a e e b a s b m 4 d e figure b.2 package dimensions (p-lfbga1717-256 (bp-256h/hv))
appendix rev. 2.00 dec. 07, 2005 page 928 of 950 rej09b0079-0200
rev. 2.00 dec. 07, 2005 page 929 of 950 rej09b0079-0200 main revisions and add itions in this edition item page revision (see manual for details) 4 realtime clock (rtc) * 1 5 ? detects short frames and long frames ? conforms to mii (media independent interface) standard * 2 : ? wol (wake-on-lan) signal output with magic packet * 3 detection notes: 1. as the power supply is connected, power should always be supplied to all power supplies even if only rtc operates. 2. +5 v i/o is not supported. 3. magic packet is t he registered trademark of advanced micro devices inc. section 1 overview and pin function 1.1 features 6 product lineup added 1.2 block diagram figure 1.1 block diagram 7 superh cpu core x/y memory instructions/data for cpu/dsp 16 kbytes user break controller (ubc) dsp core cache access controller (ccn) memory management unit (mmu) cache memory 32 kbytes cpu bus (i clock) internal bus (b clock) x bus y bus advanced user debugger (aud) l bus 1.3 pin description 1.3.1 pin assignment 8, 9 hqfp2828-256 (fp-256g/gv) figure 1.3 pin assignment (p-lfbga1717-256 (bp- 256h/hv)) added
rev. 2.00 dec. 07, 2005 page 930 of 950 rej09b0079-0200 item page revision (see manual for details) table 1.1 pin assignment 10 pin no. (fp-256g/gv) pin no. (bp-256h/hv) pin name 1 b2 refout / irqout/ arbusy 2 c2 breq 3 d2 vccq 4 b1 vssq 5 e2 back : : : notes: 1. vccq-rtc must be supp lied even if the realtime clock (rtc) is not used. 2. rtc in this lsi does not operate even if vccq-rtc is turned on. the crystal oscillator circuit for rtc operates with vccq-rtc. the control circuit and the rtc counter operate with vcc (common to the internal circuit). therefore, all power supplies other than vccq-rtc should always be turned on even if only rtc operates. 3. vcc-pll1/vcc-pll2 must be supplied even if the on-chip cpg is not used. 4. vccq (3.3 v), vcc (1.5 v), vssq, and vss must be connected to the system power supply (for uninterrupted supply). section 2 cpu 2.4.2 memory data formats 42 note: the cpu instruction codes of this lsi must be stored in word units. in big endian mode, the instruction code must be stored from upper byte to lower byte in this order from the word boundary of the memory. section 3 dsp operating unit 3.6.3 single-data transfer instructions table 3.37 single data transfer instructions 143 instruction operation movs.w @as + lx, ds (as) msw of ds, 0 lsw of ds, as + lx as
rev. 2.00 dec. 07, 2005 page 931 of 950 rej09b0079-0200 item page revision (see manual for details) 3.6.4 dsp operation instructions table 3.39 dsp operation instructions 145 instruction operation psub sx,sy,du pmuls se,sf,dg sx-sy ->du se * sf ->dg (signed) prnd sx,dz sx + h'00008000 ->dz h'0000 ->lsw of dz prnd sy,dz sy + h'00008000 ->dz h'0000 ->lsw of dz 3.6.5 operation code map in dsp mode table 3.40 operation code map 151 the shade of blanks in table 3.40 deleted. section 4 exception handling 4.2.5 exception source acceptance timing and priority table 4.1 exception event vectors 163 exception event priority * 1 exception order process at bl = 1 vector code vector offset h-udi reset 1 1 reset h'000 ? 4.3 individual exception operations 4.3.1 resets h-udi reset 165 added section 7 x/y memory 7.3.5 address error 234 added section 11 on-chip oscillation circuits 11.2.2 input/output pins table 11.1 pin configuration 315 note: to prevent device malfunction, the value of the mode control pin is sampled only by a power-on reset.
rev. 2.00 dec. 07, 2005 page 932 of 950 rej09b0079-0200 item page revision (see manual for details) 11.9 notes on board design bypass capacitors: 329 pin assignments of hqfp2828-256 (fp-256g/gv) vss/vssq and vcc/vccq pair of digital circuitry : vss/vssq and vcc/vccq pair of the on-chip oscillator 193 and 196, 251 and 252, 253 and 254 pin assignments of p-lfga1717-256 (bp-256h/hv) vss/vssq and vcc/vccq pair of digital circuitry d2-b1, e1-f4, g2-g3, j2-j4, l3-l2, n3-n2, r4-p2, u2-w1, v4-y4, y6-u7, w8-v8, v10-w10, v11-w11, v13-w13, u15-w14, w17-y 19, u18-u20, p17-n19, n18-p20, l17-l20, j18-j19, e20-e17, d19-b20, c19-a20, d15-b14, c14-a15, b11-d11, c10-b10, c8-b8, d6-b7 vss/vssq and vcc/vccq pair of the on-chip oscillator b19-a19, c3-b5, and c5-c4 section 12 bus state controller (bsc) 12.4 register descriptions 341 ? refresh timer control/status register (rtcsr) * 1 ? refresh timer counter (rtcnt) * 1 ? refresh time constant register (rtcor) * 1 ? sdram mode register for area 2 (sdmr2) * 2 ? sdram mode register for area 3 (sdmr3) * 2 notes: 1. this register only accepts 32-bit writing to prevent incorrect writing. in this case, the upper 16 bits of the data must be h'a55a. otherwise, writing cannot be performed. in reading, the upper 16 bits are read as h'0000. 2. the contents of this register are stored in sdram. when this register space is accessed, the corresponding register in sdram is written to. for details, see description of power-on sequence in section 12.5.5, sdram interface.
rev. 2.00 dec. 07, 2005 page 933 of 950 rej09b0079-0200 item page revision (see manual for details) 12.4.3 csn space wait control register (csnwcr) (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) normal space, byte-selection sram: ? cs2wcr, cs3wcr ? cs4wcr ? cs5awcr ? cs5bwcr ? cs6awcr 352 to 361 bit bit name description 10 9 8 7 wr3 wr2 wr1 wr0 number of access wait cycles specify the number of wait cycles that are necessary for read/write access. 0000: 0 cycle : burst rom (clock asynchronous): ? cs0wcr ? cs4wcr 363 to 365 bit bit name description 10 9 8 7 w3 w2 w1 w0 number of access wait cycles specify the number of wait cycles to be inserted in the first read/write access cycle. : sdram * ? cs2wcr 367 bit bit name initial value r/w description 31 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 ? 1 r reserved these bits are always read as 1. the write value should always be 1. 9 ? 0 r reserved these bits are always read as 0. the write value should always be 0. 8 7 a2cl1 a2cl0 1 0 r/w r/w cas latency for area 2 specify the cas latency for area 2. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles
rev. 2.00 dec. 07, 2005 page 934 of 950 rej09b0079-0200 item page revision (see manual for details) ? cs3wcr 368 bit bit name description 14 13 trp1 trp0 number of wait cycles waiting completion of precharge specify the number of minimum wait cycles to be inserted to wait the completion of precharge. the setting for areas 2 and 3 is common. (1) from starting auto-charge to issuing the actv command for the same bank (2) from issuing the pre/pall command to issuing the actv command for the same bank (3) to transiting to power-down mode/deep power-down mode (4) from issuing the pall command at auto- refresh to issuing the ref command (5) from issuing the pall command at self- refresh to issuing the self command 00: 0 cycle 01: 1 cycles 10: 2 cycles 11: 3 cycles 11 10 trcd1 trcd0 number of wait cycles from actv command to read (a)/writ (a) command specify the number of minimum wait cycles from issuing the actv command to issuing the read (a)/writ (a) command. the setting for areas 2 and 3 is common. 00: 0 cycle (no wait cycle) 01: 1 cycle 10: 2 cycles 11: 3 cycles
rev. 2.00 dec. 07, 2005 page 935 of 950 rej09b0079-0200 item page revision (see manual for details) ? cs3wcr 370 bit bit name description 4 3 trwl1 trwl0 number of wait cycles waiting start of precharge specify the number of minimum wait cycles to be inserted to wait the start of precharge. the setting for areas 2 and 3 is common. (1) this lsi is in non-bank active mode from the issue of the writa co mmand to the start of auto-precharge in sdram, and issues the actv command for the same bank after issuing the writa command. confirm how many cycles are required from the reception of the writa command to the start of auto- precharge in each sdram data sheet. set this bit so that the nu mber of cycles is not above the cycles specified by this bit. (2) this lsi is in bank active mode from issuing the writ command to issuing the pre command, and the access to different row address in the same bank is performed. 00: 0 cycle (no wait cycle) 01: 1 cycle 10: 2 cycles 11: 3 cycles 1 0 trc1 trc0 number of idle cycles from ref command/self- refresh release to ac tv/ref/mrs command specify the number of minimum idle cycles between the commands in the following cases. the setting for areas 2 and 3 is common. (1) from issuing the ref command to issuing the actv/ref/msr command (2) from releasing self-refresh to issuing the actv/ref/msr command 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles
rev. 2.00 dec. 07, 2005 page 936 of 950 rej09b0079-0200 item page revision (see manual for details) burst rom (clock synchronous) ? cs0wcr 375 bit bit name r/w description 10 9 8 7 w3 w2 w1 w0 r/w r/w r/w r/w number of access wait cyclesspecify the number of wait cycles to be inserted in the first read/write access cycle. : 12.4.4 sdram control register (sdcr) 378 bit bit name description 9 pdown power-down mode specify whether sdram is put in power-down mode or not after the access to memory other than sdram is completed. this bit, when set to 1, drives the cke pin low and places sdram in power-down mode by using an access to a memory other than sdram as a trigger. table 12.12 relationship between a2/3bsz[1:0], a2 /3row[1:0], a2/3col[1:0], and address multiplex output (1) 401 output pin of this lsi row address output column address output synchronous dram pin function a14 a22 * 2 a22 * 2 a12 (ba1) * 3 a13 a21 * 2 a21 * 2 a11 (ba0) specifies bank notes: 1. l/h is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. bank address specification 3. if the number of 16-mbit pins (512 kwords 16 bits 2 banks: pin with 8-bit column) is two, the bank address specification is not required. therefore, the bank address should be not used.
rev. 2.00 dec. 07, 2005 page 937 of 950 rej09b0079-0200 item page revision (see manual for details) table 12.15 relationship between a2/3bsz[1:0], a2 /3row[1:0], a2/3col[1:0], and address multiplex output (4)-1 408 output pin of this lsi row address output column address output synchronous dram pin function a17 a25 a17 a16 a24 a16 a15 a23 a15 a14 a22 a14 a13 a21 a21 unused a12 a20*2 a20 * 2 a11 (ba0) specifies bank burst read: 414 in this lsi, wait cycles can be inserted by specifying each bit in csnwcr to connect the sdram in variable frequencies. figure 12.15 shows an example in which wait cycles are inserted. the number of cycles from the tr cycle where the actv command is output to the tc1 cycle where the reada command is output can be specified using the trcd1 and trcd0 bits in cs3wcr. if the trcd1 and trcd0 bits specify one cycle or more, a trw cycle where the nop command is issued is inserted between the tr cycle and tc1 cycle. 1. auto-refreshing 428 a nop cycle is inserted between the tp cycle and trr cycle when the setting value of the trp[1:0] bits in csnwcr is longer than or equal to 1 cycle. figure 12.38 example of pcmcia interface connection 447 this lsi pc card (memory i/o) a25 to a0 d7 to d0 ce1 ce2 oe we / pgm a25 to a0 d7 to d0 d15 to d8 rd/ wr ce1a ce2a rd g g dir g dir d15 to d8
rev. 2.00 dec. 07, 2005 page 938 of 950 rej09b0079-0200 item page revision (see manual for details) section 15 realtime clock (rtc) 15.2 input/output pins table 15.1 pin configuration 507 note: 1. pull up (vccq-rtc) the extal2 pin, and open (nc) the xtal2 pin when the realtime clock (rtc) is not used. 2. rtc in this lsi does not operate even if vccq-rtc is turned on. the crystal oscillator circuit for rtc operates with vccq- rtc. the control ci rcuit and the rtc counter operate with vcc (common to the internal circuit). therefore, all power supplies other than vccq-rtc should always be turned on even if only rtc operates. 15.5.4 usage note about rtc power supply 530 added section 17 serial i/o with fifo (siof) 17.4 operation 17.4.1 serial clocks table 17.2 siof serial clock frequency 614 sampling rate frame length 8 khz 96 khz 32 bits 256 khz 3.072 mhz figure 17.13 transmission and reception timings (8-bit monaural data (1)) 631 trmd = 00or10, tdle = 1, rdle = 1, cd0e = 0, redg = 0, tdla3 to tdla0 = 0000, rdla3 to rdla0 = 0000, cd0a3 to cd0a0 = 0000, fl = 0000 (frame legth: 8 bits) tdre = 0, rdre = 0, cd1e = 0, tdra3 to tdra0 = 0000, rdra3 to rdra0 = 0000, cd1a3 to cd1a0 = 0000 setting: figure 17.15 transmission and reception timings (16-bit monaural data (1)) 632 trmd = 00 or 10, tdle = 1, rdle = 1, cd0e = 0, redg = 0, tdla3 to tdla0 = 0000, rdla3 to rdla0 = 0000, cd0a3 to cd0a0 = 0000, fl = 1101 (frame length: 64 bits) tdre = 0, rdre = 0, cd1e = 0, tdra3 to tdra0 = 0000, rdra3 to rdra0 = 0000, cd1a3 to cd1a0 = 0000 setting: figure 17.17 transmission and reception timings (16-bit stereo data (2)) 633 trmd = 01, tdle = 1, rdle = 1, cd0e = 0, redg = 1, tdla3 to tdla0 = 0000, rdla3 to rdla0 = 0001, cd0a3 to cd0a0 = 0000, fl = 1101 (frame length: 64 bits), tdre = 1, rdre = 1, cd1e = 0, tdra3 to tdra0 = 0010, rdra3 to rdra0 = 0011, cd1a3 to cd1a0 = 0000 setting: figure 17.18 transmission and reception timings (16-bit stereo data (3)) 633 trmd = 00 or 10, tdle = 1, rdle = 1, cd0e = 1, redg = 0, tdla3 to tdla0 = 0000, rdla3 to rdla0 = 0000, cd0a3 to cd0a0 = 0001, fl = 1110 (frame length: 128 bits), tdre = 1, rdre = 1, cd1e = 1, tdra3 to tdra0 = 0010, rdra3 to rdra0 = 0010, cd1a3 to cd1a0 = 0011 setting: section 18 ethernet controller (etherc) 18.3.2 etherc mode register (ecmr) 645 bit bit name r/w 13 mct r/w
rev. 2.00 dec. 07, 2005 page 939 of 950 rej09b0079-0200 item page revision (see manual for details) 18.3.36 added qtag value set register (port 0 to 1) (tsu_adqt0) 679 bit bit name r/w 12 ? r 18.3.37 added qtag value set register (port 1 to 0) (tsu_adqt1) 680 bit bit name r/w 12 ? r 18.4.4 cam function 712 the internal ca m entry table has 32 entries and 32 post tables, and the post table can be specified in each entry. the external connection cam logic configuration is based on pi ns because post tables (total of 2) are allocated to the camsen0 and camsen1 pins. 18.5 connection to lsi figure 18.13 example of connection to dp83847 725 figure 18.13 shows the example of connection to a dp83847 (national semiconductor corporation). tx-er etxd3 etxd2 etxd1 etxd0 tx-en tx-clk mdc mdio erxd3 erxd2 erxd1 erxd0 rx-clk crs col rx-dv rx-er tx_er txd[3] txd[2] txd[1] txd[0] tx_en tx_clk mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv rx_er this lsi dp83847 mii (media independent interface) figure 18.14 example of connection to dp83846avhg 726 deleted section 19 ethernet controller direct memory access controller (e-dmac) 19.1 features 727 deleted ? improves software handling capability by padding in receive data
rev. 2.00 dec. 07, 2005 page 940 of 950 rej09b0079-0200 item page revision (see manual for details) 19.2 register descriptions 729 deleted ? receive data padding insert register (rpadir0) ? receive data padding insert register (rpadir1) 19.2.2 e-dmac transmit request register (edtrr) 731 if the tact bit of a transmit descriptor is cleared to 0 (invalid), the e-dmac clears the tr bit and stops transmit dmac operation. for details of writing to t he tr bit, see section 19.4.1, using of edtrr and edrrr. 19.2.3 e-dmac receive request register (edrrr) 732 if the ract bit of the receive descriptor is cleared to 0 (invalid), the e-dmac clears the rr bit and stops receive dmac operation. for details of writing to t he rr bit, see section 19.4.1, using of edtrr and edrrr.
rev. 2.00 dec. 07, 2005 page 941 of 950 rej09b0079-0200 item page revision (see manual for details) 19.2.8 transmit/receive status copy enable register (trscer) 743 trscer indicates whether multicast address frame receive status information re ported by bit 7 in eesr is reflected in the rfe bit in the corresponding register (for details of descriptor descriptions, see section 19.3.1, descriptors and descriptor list). the rmafce bit in this register corresponds to bit 7 in eer. when the rmafce bit is cleared to 0, the receive status (bit 7 in essr) is reflected in the ref bit in the receive descriptor. when this bit is set to 0, the status is not reflected in the descriptor even if the corresponding source occurs. the rmafce bit is cleared to 0 after a power-on reset and manual reset. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value sh ould always be 0. 7 rmafce 0 r/w rmaf bit copy directive 0: reflects the rmaf bit status in the rfe bit of the receive descriptor 1: occurrence of the corresponding source is not reflected in the rfe bit of the receive descriptor 6 to 0 ? all 0 r reserved these bits are always read as 0. the write value sh ould always be 0. 19.2.19 receive data padding insert register (rpadir) 753 deleted
rev. 2.00 dec. 07, 2005 page 942 of 950 rej09b0079-0200 item page revision (see manual for details) 19.3.1 descriptors and descriptor list (2) receive descriptor (a) receive descriptor 0 (rd0) 765 bit bit name initial value r/w description 27 rfe 0 r/w receive frame error occurrence indicates that an error occurred in the receive frame. the errors occurred in rfs8 (bit 8), or rfs3 to rfs0 (bits 3 to 0). trscer can specify whether the multicast address frame receive information is reflected in this bit or not. 26 to 0 rfs26 to rfs0 all 0 r/w receive frame status indicate the status of the corresponding frame. a bit below, when set to 1, indicates the occurrence of the corresponding event. if the events of rfs8, or rfs4 to rfs0 occur, frames are incompletely received. rfs26 to rfs10: reserved rfs9: receive fifo overflow (corresponding to the rfof bit in eesr) rfs8: receive abort detected note: the rfs8 bit is set if any bit of rfs3 to rfs0 is set. rfs7: multicast address frame received (corresponding to the rmaf bit in eesr) rfs6 and rfs5: reserved (only 0 should be written to these bits) :
rev. 2.00 dec. 07, 2005 page 943 of 950 rej09b0079-0200 item page revision (see manual for details) 19.3.5 padding insertion in receive data 773 deleted 19.3.5 receive fifo overflow alert signal ( arbusy ) 773 the arbusy signal synchronized with the bus clock (b clock) signal is also output to an external pin of this lsi. when the capacity of data received in receive fifo or the number of receive frames reach the threshold (rff2 to rff0, or rfd2 to rfd0) specified in fcftr in e-dmac, arbusy is valid. 19.4 usage notes 776 added section 24 list of registers 24.1 register addresses (by functional module, in order of the corresponding section numbers) 816 rpadir0 deleted rpadir1 deleted 843 register abbrevia- tion bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? trscern (n = 0, 1) ? ? ? ? ? 844 rpadirn (n = 0, 1) deleted 24.2 register bits 844 register abbrevia- tion bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? edocrn (n = 0, 1) ? fec aec ? ?
rev. 2.00 dec. 07, 2005 page 944 of 950 rej09b0079-0200 item page revision (see manual for details) 24.3 register states in each operating mode 847 register abbreviation manual reset * 1 cmncr retained cs0bcr retained cs2bcr retained cs3bcr retained cs4bcr retained cs5abcr retained cs5bbcr retained cs6abcr retained cs6bbcr retained cs0wcr retained cs2wcr retained cs3wcr retained cs4wcr retained cs5awcr retained cs5bwcr retained 848 register abbreviation manual reset * 1 cs6awcr retained cs6bwcr retained sdcr retained rtcsr retained rtcnt retained rtcor retained 24.3 register states in each operating mode 854 rpadirn (n = 0,1) deleted section 25 electrical characteristics 25.3.2 control signal timing table 25.6 control signal timing 865 66.67 mhz item symbol min. max. irqout delay time t irqotd ? 1/2 t cyc +12
rev. 2.00 dec. 07, 2005 page 945 of 950 rej09b0079-0200 item page revision (see manual for details) table 25.7 bus timing (1) 868 66.67 mhz item symbol min. max. table 25.13 ethernet controller timing 908 item symbol max. arbusy output delay time t arbyd 1/2 t cyc +12 25.3.13 h-udi related pin timing table 25.15 h-udi related pin timing 913 item symbol tck rise/fall time t tckf /t tckr figure 25.70 tck input timing 913 t tckh t tckf t tckr t tckl t tckcyc v ih v ih v ih 1/2 v cc q 1/2 v cc q v il v il appendix b. package dimensions 926, 927 figure b.1 package dimensions (hqfp2828-256 (fp-256g/gv)) figure b.2 package dimensions (p-lfbga1717-256 (bp-256h/hv)) added
rev. 2.00 dec. 07, 2005 page 946 of 950 rej09b0079-0200
rev. 2.00 dec. 07, 2005 page 947 of 950 rej09b0079-0200 index numerics 16-bit/32-bit displacement ........................ 45 a absolute addresses ................................... 45 acceptance priority and test priority ...... 162 address space identifier (asid)............. 189 address transition ................................... 188 auto-refreshing....................................... 428 auto-request mode ................................. 477 b baud rate generator (brg)..................... 613 big endian mode....................................... 42 c control by slot position .......................... 620 control registers ....................................... 32 d delayed branching .................................... 44 double data transfer instructions .............. 94 dsp registers .................................... 77, 106 e exception hand ling state........................... 27 exception request of instruction synchronous type and instruction asynchronous type .................................. 161 extension of status register (sr) .............. 74 external request mode .................... 477, 487 g general registers ....................................... 32 global base register (gbr)....................... 40 i instruction length ...................................... 44 ipg settings............................................. 723 l literal co nstant.......................................... 45 little endian mode .................................... 43 load/sstore architecture ........................... 44 low-power consum ption state .................. 27 m magic packet........................................... 722 mii registers.................................... 719, 720 modulo register (mod) ............................ 75 multiplexed pins ..................................... 781 multiply and accumulate registers ............ 36 o on-chip peripheral module request......... 478 p p0/u0 area................................................. 29 p1 area....................................................... 29 p2 area....................................................... 29 p3 area....................................................... 29 p4 area....................................................... 29 physical address space ............................ 188 procedure register ..................................... 36
rev. 2.00 dec. 07, 2005 page 948 of 950 rej09b0079-0200 program counter ....................................... 32 program execution state............................ 27 q qtags....................................................... 723 r receive descriptor .................................. 760 receive fifo overflow alert signal ......... 773 re-execution type and processing- completion type exceptions .................... 161 registers arstr ............................... 644, 817, 851 bamra ............................. 267, 811, 847 bamrb.............................. 270, 811, 847 bara................................. 266, 811, 847 barb ................................. 269, 811, 847 basra............................... 280, 811, 847 basrb............................... 281, 811, 847 bbra ................................. 267, 811, 847 bbrb ................................. 272, 811, 847 bdmrb.............................. 271, 811, 847 bdrb ................................. 270, 811, 847 betr.................................. 278, 811, 847 brcr ................................. 274, 811, 847 brdr ................................. 280, 811, 847 brsr.................................. 279, 811, 847 ccr1 .................................. 217, 810, 846 ccr2 .................................. 218, 810, 846 ccr3 .................................. 221, 810, 846 cdcr ................................. 654, 816, 851 cefcr ............................... 655, 816, 851 chcr ................................. 464, 812, 848 cmncr.............................. 342, 811, 847 cndcr .............................. 654, 816, 851 csnbcr ............................. 345, 811, 847 csnwcr ............................ 350, 812, 848 dar.................................... 463, 812, 848 dmaor ............................. 469, 813, 848 dmars .............................. 471, 813, 848 dmatcr ........................... 464, 812, 848 ecmr ................................. 645, 815, 850 ecsipr............................... 649, 815, 850 ecsr .................................. 648, 815, 850 edmr................................. 730, 820, 853 edocr............................... 749, 820, 853 edrrr ............................... 732, 820, 853 edtrr ............................... 731, 820, 853 eesipr ............................... 740, 820, 853 eesr................................... 734, 820, 853 expevt ............................. 157, 810, 846 fcftr ................................ 751, 820, 854 fdr..................................... 747, 820, 853 frecr................................ 655, 816, 851 frqcr ............................... 320, 811, 847 fwalcr............................ 702, 818, 852 fwnlcr............................ 701, 818, 852 icr0.................................... 248, 810, 846 icr1.................................... 249, 810, 846 intevt.............................. 157, 810, 846 intevt2............................ 158, 810, 846 ipgr ................................... 657, 816, 851 ipr ...................................... 246, 810, 846 irr0.................................... 251, 811, 846 irr1.................................... 251, 811, 846 irr2.................................... 253, 811, 846 irr3.................................... 254, 811, 846 irr4.................................... 255, 811, 846 irr5.................................... 256, 811, 847 irr7.................................... 257, 811, 847 irr8.................................... 258, 811, 847 lccr.................................. 654, 816, 851 mafcr .............................. 657, 816, 851 mahr ................................ 651, 816, 851 malr................................. 651, 816, 851 mmucr ............................. 191, 810, 846 pacr.................................. 783, 821, 854 padr.................................. 789, 821, 854
rev. 2.00 dec. 07, 2005 page 949 of 950 rej09b0079-0200 pbcr.................................. 784, 821, 854 pbdr.................................. 790, 821, 854 pccr.................................. 785, 821, 854 pcdr.................................. 792, 821, 854 petcr................................ 786, 821, 854 pir...................................... 650, 816, 851 psr ..................................... 653, 816, 851 pteh .................................. 190, 810, 846 ptel................................... 191, 810, 846 r64cnt ............................. 508, 813, 849 rbwar ............................. 750, 820, 853 rcr1 .................................. 520, 814, 849 rcr2 .................................. 522, 814, 849 rcr3 .................................. 524, 814, 849 rdayar ........................... 517, 814, 849 rdaycnt......................... 512, 814, 849 rdfar............................... 750, 820, 853 rdlar............................... 734, 820, 853 rfcr.................................. 656, 816, 851 rflr .................................. 652, 816, 851 rhrar .............................. 515, 814, 849 rhrcnt ............................ 509, 813, 849 rmcr................................. 748, 820, 853 rmfcr .............................. 744, 820, 853 rminar ............................ 514, 814, 849 rmincnt.......................... 509, 813, 849 rmonar........................... 518, 814, 849 rmoncnt ........................ 512, 814, 849 rsecar............................. 514, 814, 849 rseccnt .......................... 508, 813, 849 rtcnt ............................... 381, 812, 848 rtcor............................... 382, 812, 848 rtcsr ............................... 380, 812, 848 rwkar ............................. 516, 814, 849 rwkcnt........................... 510, 814, 849 rxalcr............................ 701, 818, 852 rxnlcr............................ 700, 818, 852 ryrar .............................. 519, 814, 849 ryrcnt ............................ 513, 814, 849 sar .................................... 463, 812, 848 scbrr................................ 553, 814, 849 scfcr ................................ 554, 814, 849 scfdr................................ 556, 814, 850 scfrdr ............................. 536, 814, 849 scfsr ................................ 545, 814, 849 scftdr ............................. 537, 814, 849 sclsr ................................ 558, 814, 850 scrsr ................................................ 536 scscr ................................ 541, 814, 849 scsmr ............................... 537, 814, 849 sctsr ................................................ 537 sdbpr................................................ 795 sdbsr................................................ 796 sdcr .................................. 377, 812, 848 sdid ................................... 803, 821, 854 sdir ................................... 795, 821, 854 sicdar.............................. 596, 815, 850 sictr ................................. 598, 815, 850 sifctr............................... 601, 815, 850 siier .................................. 607, 815, 850 simdr................................ 591, 815, 850 sircr................................. 612, 815, 850 sirdar.............................. 595, 815, 850 sirdr................................. 610, 815, 850 siscr ................................. 593, 815, 850 sistr.................................. 603, 815, 850 sitcr ................................. 611, 815, 850 sitdar .............................. 594, 815, 850 sitdr................................. 609, 815, 850 stbcr................................ 298, 811, 847 stbcr2.............................. 300, 811, 847 stbcr3.............................. 301, 811, 847 tbrar ............................... 750, 821, 854 tcnt .................................. 499, 813, 848 tcor.................................. 499, 813, 848 tcr..................................... 498, 813, 848 tdfar ............................... 751, 821, 854 tdlar ............................... 733, 820, 853 tea..................................... 158, 810, 846 tftr................................... 745, 820, 853
rev. 2.00 dec. 07, 2005 page 950 of 950 rej09b0079-0200 tlfrcr ............................. 656, 816, 851 tra .................................... 156, 810, 846 trimd ............................... 753, 820, 854 trocr............................... 653, 816, 851 trscer ............................. 743, 820, 853 tsfrcr ............................. 655, 816, 851 tstr .................................. 497, 813, 848 tsu_adqt0 ..................... 679, 817, 852 tsu_adqt1 ..................... 680, 817, 852 tsu_adrh ....................... 698, 818, 853 tsu_adrl........................ 699, 818, 853 tsu_adsbsy................... 681, 817, 852 tsu_bsysl0 .................... 661, 817, 852 tsu_bsysl1 .................... 662, 817, 852 tsu_ctrst ...................... 658, 817, 851 tsu_fcm .......................... 660, 817, 852 tsu_fwen0 ..................... 658, 817, 851 tsu_fwen1 ..................... 659, 817, 851 tsu_fwinmk .................. 675, 817, 852 tsu_fwsl0...................... 666, 817, 852 tsu_fwsl1...................... 667, 817, 852 tsu_fwslc ..................... 669, 817, 852 tsu_fwsr........................ 673, 817, 852 tsu_post1....................... 686, 817, 852 tsu_post2....................... 689, 817, 852 tsu_post3....................... 692, 817, 852 tsu_post4....................... 695, 817, 852 tsu_prisl0...................... 663, 817, 852 tsu_prisl1...................... 664, 817, 852 tsu_qtagm0 .................. 671, 817, 852 tsu_qtagm1 .................. 672, 817, 852 tsu_ten........................... 682, 817, 852 ttb .................................... 191, 810, 846 txalcr ............................ 700, 817, 852 txnlcr ............................ 699, 817, 852 wtcnt .............................. 324, 811, 847 wtcsr............................... 324, 811, 847 registers addresses ................................. 809 registers bits........................................... 809 registers states........................................ 809 repeat end regi ster (re)........................... 75 repeat start register (rs) .......................... 75 reset state ................................................. 27 round-robin mode .................................. 480 s save program counter (spc) .................... 40 save status regi ster (ssr)......................... 40 secondary fs .......................................... 621 self-refreshing ........................................ 429 single data transfer instructions................ 95 single virtual memory mode and multiple virtual memory mode................ 189 software standby mode........................... 303 status register (sr) ................................... 38 system control instructions....................... 95 system registers ........................................ 32 t t bit........................................................... 44 the rtc crystal oscillator circuit ............ 528 transmit descriptor ................................. 754 v vector base register (vbr)....................... 40 virtual address space .............................. 183
renesas 32-bit risc microcomputer hardware manual sh7710 group publication date: 1st edition, jan. 21, 2004 rev.2.00, dec. 07, 2005 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2005. renesas technology corp., all rights reserved. printed in japan.
sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 205, azia center, no.133 yincheng rd (n), pudong district, shanghai 200120, china tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 5.0

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